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| author | Junyang Shao <shaojunyang@google.com> | 2026-04-08 22:08:30 +0000 |
|---|---|---|
| committer | Junyang Shao <shaojunyang@google.com> | 2026-04-13 13:36:26 -0700 |
| commit | 14685c05aae4e87c455f8489258ad9ee13b0273c (patch) | |
| tree | 5e414827dc2145bc0be882c51a26a223da353c2a /src/cmd/internal/obj/util.go | |
| parent | 1aa9d9a69bbf1c9bf1a5806d554ab932c587efd0 (diff) | |
| download | go-14685c05aae4e87c455f8489258ad9ee13b0273c.tar.xz | |
cmd/asm, cmd/internal/obj/arm64: support memory with extensions in SVE
This CL is generated by CL 764800.
Supported addressing patterns:
(Z7.D.SXTW<<2)(Z6.D), where Z6.D is the base, Z7.D is the indices.
SXTW/UXTW represents signed/unsigned extension, << represents LSL.
Change-Id: Ifc6c47833d5113be7cfe96943d369ab977b3a6ee
Reviewed-on: https://go-review.googlesource.com/c/go/+/764780
Reviewed-by: David Chase <drchase@google.com>
LUCI-TryBot-Result: golang-scoped@luci-project-accounts.iam.gserviceaccount.com <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
Commit-Queue: Junyang Shao <shaojunyang@google.com>
Diffstat (limited to 'src/cmd/internal/obj/util.go')
| -rw-r--r-- | src/cmd/internal/obj/util.go | 41 |
1 files changed, 34 insertions, 7 deletions
diff --git a/src/cmd/internal/obj/util.go b/src/cmd/internal/obj/util.go index 9b440ebd58..4349f4d741 100644 --- a/src/cmd/internal/obj/util.go +++ b/src/cmd/internal/obj/util.go @@ -222,6 +222,11 @@ func (ctxt *Link) CanReuseProgs() bool { return ctxt.Debugasm == 0 } +func isZReg(r int) bool { + return (r >= RBaseARM64+96 && r <= RBaseARM64+127) || + (r >= RBaseARM64+2048 && r < RBaseARM64+3072) +} + // Dconv accepts an argument 'a' within a prog 'p' and returns a string // with a formatted version of the argument. func Dconv(p *Prog, a *Addr) string { @@ -297,13 +302,35 @@ func writeDconv(w io.Writer, p *Prog, a *Addr, abiDetail bool) { a.writeNameTo(w, abiDetail) case TYPE_MEM: - a.WriteNameTo(w) - if a.Index != REG_NONE { - if a.Scale == 0 { - // arm64 shifted or extended register offset, scale = 0. - fmt.Fprintf(w, "(%v)", Rconv(int(a.Index))) - } else { - fmt.Fprintf(w, "(%v*%d)", Rconv(int(a.Index)), int(a.Scale)) + if buildcfg.GOARCH == "arm64" && (a.Scale < 0 || isZReg(int(a.Reg)) || isZReg(int(a.Index))) { + // SVE extended addressing pattern + amount := 0 + mod := 0 + if a.Scale < 0 { + amount = int((a.Scale >> 12) & 0x7) + mod = int((a.Scale >> 9) & 0x7) + } + modStr := "" + switch mod { + case 1: + modStr = ".UXTW" + case 2: + modStr = ".SXTW" + } + amountStr := "" + if amount != 0 { + amountStr = fmt.Sprintf("<<%d", amount) + } + fmt.Fprintf(w, "(%v%s%s)(%v)", Rconv(int(a.Reg)), modStr, amountStr, Rconv(int(a.Index))) + } else { + a.WriteNameTo(w) + if a.Index != REG_NONE { + if a.Scale == 0 { + // arm64 shifted or extended register offset, scale = 0. + fmt.Fprintf(w, "(%v)", Rconv(int(a.Index))) + } else { + fmt.Fprintf(w, "(%v*%d)", Rconv(int(a.Index)), int(a.Scale)) + } } } |
