diff options
| author | Joel Sing <joel@sing.id.au> | 2020-03-03 03:41:43 +1100 |
|---|---|---|
| committer | Joel Sing <joel@sing.id.au> | 2020-03-15 08:15:09 +0000 |
| commit | 25da2ea72c18a63f5efdb7c506669aa733693bea (patch) | |
| tree | df3bf3e98f2350bd057bcb74af29e00cf355e3ba /src/cmd/internal/obj/riscv | |
| parent | dc3255391a59474eda08e71eaf8090753b0a84db (diff) | |
| download | go-25da2ea72c18a63f5efdb7c506669aa733693bea.tar.xz | |
cmd/internal/obj/riscv: add NEG/NEGW pseudo-instructions
Provide NEG/NEGW pseudo-instructions, which translate to SUB/SUBW with the
zero register as a source.
Change-Id: I2c1ec1e75611c234c5ee8e39390dd188f8e42bae
Reviewed-on: https://go-review.googlesource.com/c/go/+/221689
Reviewed-by: Cherry Zhang <cherryyz@google.com>
Diffstat (limited to 'src/cmd/internal/obj/riscv')
| -rw-r--r-- | src/cmd/internal/obj/riscv/anames.go | 2 | ||||
| -rw-r--r-- | src/cmd/internal/obj/riscv/cpu.go | 2 | ||||
| -rw-r--r-- | src/cmd/internal/obj/riscv/obj.go | 11 |
3 files changed, 15 insertions, 0 deletions
diff --git a/src/cmd/internal/obj/riscv/anames.go b/src/cmd/internal/obj/riscv/anames.go index 9edf8f0e65..fa236d81e5 100644 --- a/src/cmd/internal/obj/riscv/anames.go +++ b/src/cmd/internal/obj/riscv/anames.go @@ -239,6 +239,8 @@ var Anames = []string{ "MOVHU", "MOVW", "MOVWU", + "NEG", + "NEGW", "NOT", "SEQZ", "SNEZ", diff --git a/src/cmd/internal/obj/riscv/cpu.go b/src/cmd/internal/obj/riscv/cpu.go index c1fc67f4ab..632b3e6690 100644 --- a/src/cmd/internal/obj/riscv/cpu.go +++ b/src/cmd/internal/obj/riscv/cpu.go @@ -589,6 +589,8 @@ const ( AMOVHU AMOVW AMOVWU + ANEG + ANEGW ANOT ASEQZ ASNEZ diff --git a/src/cmd/internal/obj/riscv/obj.go b/src/cmd/internal/obj/riscv/obj.go index e003584dad..ed5d533402 100644 --- a/src/cmd/internal/obj/riscv/obj.go +++ b/src/cmd/internal/obj/riscv/obj.go @@ -1849,6 +1849,17 @@ func instructionsForProg(p *obj.Prog) []*instruction { ins.rs1 = uint32(p.From.Reg) ins.rs2 = REG_F0 + case ANEG, ANEGW: + // NEG rs, rd -> SUB rs, X0, rd + ins.as = ASUB + if p.As == ANEGW { + ins.as = ASUBW + } + ins.rs1 = REG_ZERO + if ins.rd == obj.REG_NONE { + ins.rd = ins.rs2 + } + case ANOT: // NOT rs, rd -> XORI $-1, rs, rd ins.as = AXORI |