diff options
| author | fanzha02 <fannie.zhang@arm.com> | 2018-09-10 02:22:48 +0000 |
|---|---|---|
| committer | Cherry Zhang <cherryyz@google.com> | 2018-09-12 15:45:13 +0000 |
| commit | e7f5f3eca42a98340e4eb4fc5d490a9aa4bd5054 (patch) | |
| tree | b21f9398016f2eaa4e4ab13400845488bc665b56 /src/cmd/internal/obj/arm64 | |
| parent | d5377c2026b18e1307c6fd243ece98afc6330b71 (diff) | |
| download | go-e7f5f3eca42a98340e4eb4fc5d490a9aa4bd5054.tar.xz | |
cmd/internal/obj/arm64: add error report for invalid base register
The current assembler accepts the non-integer register as the base register,
which should be an illegal combination.
Add the test cases.
Change-Id: Ia21596bbb5b1e212e34bd3a170748ae788860422
Reviewed-on: https://go-review.googlesource.com/134575
Reviewed-by: Cherry Zhang <cherryyz@google.com>
Run-TryBot: Cherry Zhang <cherryyz@google.com>
TryBot-Result: Gobot Gobot <gobot@golang.org>
Diffstat (limited to 'src/cmd/internal/obj/arm64')
| -rw-r--r-- | src/cmd/internal/obj/arm64/asm7.go | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/src/cmd/internal/obj/arm64/asm7.go b/src/cmd/internal/obj/arm64/asm7.go index 09ffc5dccf..46fdcdcf7d 100644 --- a/src/cmd/internal/obj/arm64/asm7.go +++ b/src/cmd/internal/obj/arm64/asm7.go @@ -1426,6 +1426,10 @@ func (c *ctxt7) aclass(a *obj.Addr) int { return C_LIST case obj.TYPE_MEM: + // The base register should be an integer register. + if int16(REG_F0) <= a.Reg && a.Reg <= int16(REG_V31) { + break + } switch a.Name { case obj.NAME_EXTERN, obj.NAME_STATIC: if a.Sym == nil { @@ -2968,7 +2972,7 @@ func (c *ctxt7) asmout(p *obj.Prog, o *Optab, out []uint32) { } case 22: /* movT (R)O!,R; movT O(R)!, R -> ldrT */ - if p.As != AFMOVS && p.As != AFMOVD && p.From.Reg != REGSP && p.From.Reg == p.To.Reg { + if p.From.Reg != REGSP && p.From.Reg == p.To.Reg { c.ctxt.Diag("constrained unpredictable behavior: %v", p) } @@ -2986,7 +2990,7 @@ func (c *ctxt7) asmout(p *obj.Prog, o *Optab, out []uint32) { o1 |= ((uint32(v) & 0x1FF) << 12) | (uint32(p.From.Reg&31) << 5) | uint32(p.To.Reg&31) case 23: /* movT R,(R)O!; movT O(R)!, R -> strT */ - if p.As != AFMOVS && p.As != AFMOVD && p.To.Reg != REGSP && p.From.Reg == p.To.Reg { + if p.To.Reg != REGSP && p.From.Reg == p.To.Reg { c.ctxt.Diag("constrained unpredictable behavior: %v", p) } |