cmd/asm, cmd/internal/obj/arm64: support memory with extensions in SVE

This CL is generated by CL 764800.

Supported addressing patterns:
(Z7.D.SXTW<<2)(Z6.D), where Z6.D is the base, Z7.D is the indices.
SXTW/UXTW represents signed/unsigned extension, << represents LSL.

Change-Id: Ifc6c47833d5113be7cfe96943d369ab977b3a6ee
Reviewed-on: https://go-review.googlesource.com/c/go/+/764780
Reviewed-by: David Chase <drchase@google.com>
LUCI-TryBot-Result: golang-scoped@luci-project-accounts.iam.gserviceaccount.com <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
Commit-Queue: Junyang Shao <shaojunyang@google.com>

6 files changed, 3179 insertions, 133 deletions

diff --git a/src/cmd/internal/obj/arm64/anames_gen.go b/src/cmd/internal/obj/arm64/anames_gen.go
index 0bb768900d..87620b1e10 100644
--- a/src/cmd/internal/obj/arm64/anames_gen.go
+++ b/src/cmd/internal/obj/arm64/anames_gen.go
@@ -97,6 +97,7 @@ var sveAnames = []string{
 	"ZADDQP",
 	"ZADDQV",
 	"ZADDSUBP",
+	"ZADR",
 	"ZAESD",
 	"ZAESE",
 	"ZAESIMC",
@@ -327,6 +328,51 @@ var sveAnames = []string{
 	"ZLASTBH",
 	"ZLASTBS",
 	"ZLASTBW",
+	"ZLD1B",
+	"ZLD1D",
+	"ZLD1H",
+	"ZLD1Q",
+	"ZLD1ROB",
+	"ZLD1ROD",
+	"ZLD1ROH",
+	"ZLD1ROW",
+	"ZLD1RQB",
+	"ZLD1RQD",
+	"ZLD1RQH",
+	"ZLD1RQW",
+	"ZLD1SB",
+	"ZLD1SH",
+	"ZLD1SW",
+	"ZLD1W",
+	"ZLD2B",
+	"ZLD2D",
+	"ZLD2H",
+	"ZLD2Q",
+	"ZLD2W",
+	"ZLD3B",
+	"ZLD3D",
+	"ZLD3H",
+	"ZLD3Q",
+	"ZLD3W",
+	"ZLD4B",
+	"ZLD4D",
+	"ZLD4H",
+	"ZLD4Q",
+	"ZLD4W",
+	"ZLDFF1B",
+	"ZLDFF1D",
+	"ZLDFF1H",
+	"ZLDFF1SB",
+	"ZLDFF1SH",
+	"ZLDFF1SW",
+	"ZLDFF1W",
+	"ZLDNT1B",
+	"ZLDNT1D",
+	"ZLDNT1H",
+	"ZLDNT1SB",
+	"ZLDNT1SH",
+	"ZLDNT1SW",
+	"ZLDNT1W",
 	"ZLSL",
 	"ZLSLR",
 	"ZLSR",
@@ -477,6 +523,30 @@ var sveAnames = []string{
 	"ZSSUBLTB",
 	"ZSSUBWB",
 	"ZSSUBWT",
+	"ZST1B",
+	"ZST1D",
+	"ZST1H",
+	"ZST1Q",
+	"ZST1W",
+	"ZST2B",
+	"ZST2D",
+	"ZST2H",
+	"ZST2Q",
+	"ZST2W",
+	"ZST3B",
+	"ZST3D",
+	"ZST3H",
+	"ZST3Q",
+	"ZST3W",
+	"ZST4B",
+	"ZST4D",
+	"ZST4H",
+	"ZST4Q",
+	"ZST4W",
+	"ZSTNT1B",
+	"ZSTNT1D",
+	"ZSTNT1H",
+	"ZSTNT1W",
 	"ZSUB",
 	"ZSUBHNB",
 	"ZSUBHNT",
diff --git a/src/cmd/internal/obj/arm64/asm7.go b/src/cmd/internal/obj/arm64/asm7.go
index 972980defe..eb6974e567 100644
--- a/src/cmd/internal/obj/arm64/asm7.go
+++ b/src/cmd/internal/obj/arm64/asm7.go
@@ -8465,7 +8465,11 @@ func EncodeRegisterExtension(a *obj.Addr, ext string, reg, num int16, isAmount,
 			a.Reg = REG_ZARNGELEM + (reg & 31) + int16((arng&15)<<5)
 			a.Index = num
 		} else {
-			a.Reg = REG_ZARNG + (reg & 31) + int16((arng&15)<<5)
+			if a.Type == obj.TYPE_MEM {
+				a.Index = REG_ZARNG + (reg & 31) + int16((arng&15)<<5)
+			} else {
+				a.Reg = REG_ZARNG + (reg & 31) + int16((arng&15)<<5)
+			}
 		}
 	} else if REG_P0 <= reg && reg <= REG_PN15 {
 		var arng int
diff --git a/src/cmd/internal/obj/arm64/encoding_gen.go b/src/cmd/internal/obj/arm64/encoding_gen.go
index 2743a2d7cf..dbd4b67cf9 100644
--- a/src/cmd/internal/obj/arm64/encoding_gen.go
+++ b/src/cmd/internal/obj/arm64/encoding_gen.go
@@ -2,6 +2,34 @@
 
 package arm64
 
+import "cmd/internal/obj"
+
+// stripRawZ first checks if v is a raw Z register, if so
+// it tries to verify that it's indeed a Z register, if it's not
+// it will return ok as false.
+// Otherwise, it will strip additional information and return ok as true.
+func stripRawZ(v *uint32) bool {
+	if *v >= obj.RBaseARM64 {
+		if !(*v >= REG_Z0 && *v <= REG_Z31) && !(*v >= REG_ZARNG && *v < REG_ZARNGELEM) {
+			return false
+		}
+	}
+	*v = *v & 31
+	return true
+}
+
+// checkIsR checks if v is a scalar register.
+// In the encoding scheme, R is always assumed to be passed in as raw, i.e.
+// starting at RBaseARM64. If it's not a raw R register, it will strip
+// additional information and return ok as true.
+// Otherwise, it will return ok as false.
+func checkIsR(v uint32) bool {
+	if v > REG_R31 && v != REG_RSP {
+		return false
+	}
+	return true
+}
+
 const (
 	enc_NIL component = iota
 	enc_i1_tsz
@@ -37,6 +65,7 @@ const (
 	enc_Zk
 	enc_Zm
 	enc_Zn
+	enc_Zt
 	enc_i1
 	enc_i2
 	enc_imm13
@@ -48,13 +77,27 @@ const (
 	enc_imm6
 	enc_imm7
 	enc_imm8
+	enc_msz
 	enc_rot
 	enc_size
 	enc_size0
 	enc_sz
 	enc_tsz
+	enc_xs
 )
 
+// encodeNoModCheck is the implementation of the following encoding logic:
+// Check that there is no modifier (UXTW, SXTW, LSL)
+func encodeNoModCheck(v uint32) (uint32, bool) {
+	return 0, v == 0
+}
+
+// encodeNoAmtCheck is the implementation of the following encoding logic:
+// Check that there is no modifier amount
+func encodeNoAmtCheck(v uint32) (uint32, bool) {
+	return 0, v == 0
+}
+
 // encodeXCheck is the implementation of the following encoding logic:
 // Check this is a 64-bit scalar register
 func encodeXCheck(v uint32) (uint32, bool) {
@@ -133,6 +176,69 @@ func encodeFimm0_0_56(v uint32) (uint32, bool) {
 	return 0, true
 }
 
+// encodeModAmt1Check is the implementation of the following encoding logic:
+// Check this is mod amount and is 1
+func encodeModAmt1Check(v uint32) (uint32, bool) {
+	if v == 1 {
+		return 0, true
+	}
+	return 0, false
+}
+
+// encodeModAmt2Check is the implementation of the following encoding logic:
+// Check this is mod amount and is 2
+func encodeModAmt2Check(v uint32) (uint32, bool) {
+	if v == 2 {
+		return 0, true
+	}
+	return 0, false
+}
+
+// encodeModAmt3Check is the implementation of the following encoding logic:
+// Check this is mod amount and is 3
+func encodeModAmt3Check(v uint32) (uint32, bool) {
+	if v == 3 {
+		return 0, true
+	}
+	return 0, false
+}
+
+// encodeModAmt4Check is the implementation of the following encoding logic:
+// Check this is mod amount and is 4
+func encodeModAmt4Check(v uint32) (uint32, bool) {
+	if v == 4 {
+		return 0, true
+	}
+	return 0, false
+}
+
+// encodeModLSLCheck is the implementation of the following encoding logic:
+// Check this is mod and is LSL
+func encodeModLSLCheck(v uint32) (uint32, bool) {
+	if v&0b100 != 0 {
+		return 0, true
+	}
+	return 0, false
+}
+
+// encodeModSXTWCheck is the implementation of the following encoding logic:
+// Check this is mod and is SXTW
+func encodeModSXTWCheck(v uint32) (uint32, bool) {
+	if v&0b10 != 0 {
+		return 0, true
+	}
+	return 0, false
+}
+
+// encodeModUXTWCheck is the implementation of the following encoding logic:
+// Check this is mod and is UXTW
+func encodeModUXTWCheck(v uint32) (uint32, bool) {
+	if v&0b1 != 0 {
+		return 0, true
+	}
+	return 0, false
+}
+
 // encodeI2_1921_16To32Bit is the implementation of the following encoding logic:
 // For the "16-bit to 32-bit" variant: is the immediate index of a pair of 16-bit elements within each 128-bit vector segment, in the range 0 to 3, encoded in the "i2" field.
 // bit range mappings:
@@ -160,6 +266,9 @@ func encodeI1_2021_16To64Bit(v uint32) (uint32, bool) {
 // bit range mappings:
 // Zm: [16:20)
 func encodeZm1620_16To64Bit(v uint32) (uint32, bool) {
+	if !stripRawZ(&v) {
+		return 0, false
+	}
 	if v > 15 {
 		return 0, false
 	}
@@ -171,6 +280,9 @@ func encodeZm1620_16To64Bit(v uint32) (uint32, bool) {
 // bit range mappings:
 // Zm: [16:19)
 func encodeZm1619_16Bit32Bit(v uint32) (uint32, bool) {
+	if !stripRawZ(&v) {
+		return 0, false
+	}
 	if v > 7 {
 		return 0, false
 	}
@@ -205,6 +317,9 @@ func encodeI3hI3l_1923_16Bit(v uint32) (uint32, bool) {
 // bit range mappings:
 // Zm: [16:19)
 func encodeZm_1619_Range0_7V1(v uint32) (uint32, bool) {
+	if !stripRawZ(&v) {
+		return 0, false
+	}
 	if v <= 7 {
 		return v << 16, true
 	}
@@ -250,6 +365,9 @@ func encodeI3hI3l_1119_32Bit(v uint32) (uint32, bool) {
 // bit range mappings:
 // Zm: [16:20)
 func encodeZm_1620_Range0_15(v uint32) (uint32, bool) {
+	if !stripRawZ(&v) {
+		return 0, false
+	}
 	if v <= 15 {
 		return v << 16, true
 	}
@@ -261,6 +379,9 @@ func encodeZm_1620_Range0_15(v uint32) (uint32, bool) {
 // bit range mappings:
 // Zm: [16:19)
 func encodeZm1619_32Bit(v uint32) (uint32, bool) {
+	if !stripRawZ(&v) {
+		return 0, false
+	}
 	if v > 7 {
 		return 0, false
 	}
@@ -295,6 +416,9 @@ func encodeI2hI2l_1120_64Bit(v uint32) (uint32, bool) {
 // bit range mappings:
 // Zm: [16:20)
 func encodeZm1620_64Bit(v uint32) (uint32, bool) {
+	if !stripRawZ(&v) {
+		return 0, false
+	}
 	if v > 15 {
 		return 0, false
 	}
@@ -329,6 +453,9 @@ func encodeI2_1921_8To32Bit(v uint32) (uint32, bool) {
 // bit range mappings:
 // Zm: [16:19)
 func encodeZm1619_8To32Bit(v uint32) (uint32, bool) {
+	if !stripRawZ(&v) {
+		return 0, false
+	}
 	if v > 7 {
 		return 0, false
 	}
@@ -411,6 +538,9 @@ func encodeI1_2021_DoublePrecision(v uint32) (uint32, bool) {
 // bit range mappings:
 // Zm: [16:20)
 func encodeZm1620_DoublePrecision(v uint32) (uint32, bool) {
+	if !stripRawZ(&v) {
+		return 0, false
+	}
 	if v > 15 {
 		return 0, false
 	}
@@ -445,6 +575,9 @@ func encodeImm5Signed_1621V2(v uint32) (uint32, bool) {
 // bit range mappings:
 // Zm: [16:19)
 func encodeZm1619_HalfSinglePrecision(v uint32) (uint32, bool) {
+	if !stripRawZ(&v) {
+		return 0, false
+	}
 	if v > 7 {
 		return 0, false
 	}
@@ -479,6 +612,9 @@ func encodeI2_1921_Half(v uint32) (uint32, bool) {
 // bit range mappings:
 // Zm: [16:19)
 func encodeZm_1619_Half(v uint32) (uint32, bool) {
+	if !stripRawZ(&v) {
+		return 0, false
+	}
 	if v <= 7 {
 		return v << 16, true
 	}
@@ -574,6 +710,9 @@ func encodeI1_2021_Single(v uint32) (uint32, bool) {
 // bit range mappings:
 // Zm: [16:20)
 func encodeZm_1620_Single(v uint32) (uint32, bool) {
+	if !stripRawZ(&v) {
+		return 0, false
+	}
 	if v <= 15 {
 		return v << 16, true
 	}
@@ -727,6 +866,9 @@ func encodeImm8UnsignedLsl8(v uint32) (uint32, bool) {
 // bit range mappings:
 // Rdn: [0:5)
 func encodeWdn05(v uint32) (uint32, bool) {
+	if !checkIsR(v) {
+		return 0, false
+	}
 	if v == REG_RSP {
 		return 0, false
 	}
@@ -746,6 +888,9 @@ func encodeVd0564(v uint32) (uint32, bool) {
 // bit range mappings:
 // Rd: [0:5)
 func encodeRd05_SPAllowed(v uint32) (uint32, bool) {
+	if !checkIsR(v) {
+		return 0, false
+	}
 	if v == REG_R31 {
 		return 0, false
 	}
@@ -760,6 +905,9 @@ func encodeRd05_SPAllowed(v uint32) (uint32, bool) {
 // bit range mappings:
 // Rd: [0:5)
 func encodeRd05(v uint32) (uint32, bool) {
+	if !checkIsR(v) {
+		return 0, false
+	}
 	if v == REG_RSP {
 		return 0, false
 	}
@@ -771,17 +919,54 @@ func encodeRd05(v uint32) (uint32, bool) {
 // bit range mappings:
 // Rn: [5:10)
 func encodeRn510(v uint32) (uint32, bool) {
+	if !checkIsR(v) {
+		return 0, false
+	}
 	if v == REG_RSP {
 		return 0, false
 	}
 	return (v & 31) << 5, true
 }
 
-// encodeRm1621 is the implementation of the following encoding logic:
+// encodeRn510SPV2 is the implementation of the following encoding logic:
+// Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
+// bit range mappings:
+// Rn: [5:10)
+func encodeRn510SPV2(v uint32) (uint32, bool) {
+	if !checkIsR(v) {
+		return 0, false
+	}
+	if v == REG_R31 {
+		return 0, false
+	}
+	if v == REG_RSP {
+		return 31 << 5, true
+	}
+	return (v & 31) << 5, true
+}
+
+// encodeRm1621V2 is the implementation of the following encoding logic:
+// Is the 64-bit name of the general-purpose offset register, encoded in the "Rm" field.
+// bit range mappings:
+// Rm: [16:21)
+func encodeRm1621V2(v uint32) (uint32, bool) {
+	if !checkIsR(v) {
+		return 0, false
+	}
+	if v == REG_RSP {
+		return 0, false
+	}
+	return (v & 31) << 16, true
+}
+
+// encodeRm1621V1 is the implementation of the following encoding logic:
 // Is the 64-bit name of the second source general-purpose register, encoded in the "Rm" field.
 // bit range mappings:
 // Rm: [16:21)
-func encodeRm1621(v uint32) (uint32, bool) {
+func encodeRm1621V1(v uint32) (uint32, bool) {
+	if !checkIsR(v) {
+		return 0, false
+	}
 	if v == REG_RSP {
 		return 0, false
 	}
@@ -793,6 +978,9 @@ func encodeRm1621(v uint32) (uint32, bool) {
 // bit range mappings:
 // Rdn: [0:5)
 func encodeXdn05(v uint32) (uint32, bool) {
+	if !checkIsR(v) {
+		return 0, false
+	}
 	if v == REG_RSP {
 		return 0, false
 	}
@@ -804,6 +992,9 @@ func encodeXdn05(v uint32) (uint32, bool) {
 // bit range mappings:
 // Rn: [16:21)
 func encodeRn1621_SPAllowed(v uint32) (uint32, bool) {
+	if !checkIsR(v) {
+		return 0, false
+	}
 	if v == REG_R31 {
 		return 0, false
 	}
@@ -1107,6 +1298,83 @@ func encodeShiftTsz58Range1(v uint32) (uint32, bool) {
 	return codeShift588102224, false
 }
 
+// encodeMsz1012 is the implementation of the following encoding logic:
+// Is the index extend and shift specifier,
+// msz	<mod>
+// 00	[absent]
+// x1	LSL
+// 10	LSL
+// bit range mappings:
+// msz: [10:12)
+func encodeMsz1012(v uint32) (uint32, bool) {
+	// This does not accept UXTW and SXTW, check that
+	if v&0b11 != 0 {
+		return 0, false
+	}
+	// Note: this encoding function's semantic is entailed by its peer that
+	// encode <amount>, so just do nothing.
+	return codeNoOp, false
+}
+
+// encodeXs1415 is the implementation of the following encoding logic:
+// Is the index extend and shift specifier,
+// xs	<mod>
+// 0	UXTW
+// 1	SXTW
+// bit range mappings:
+// xs: [14:15)
+func encodeXs1415(v uint32) (uint32, bool) {
+	if v&0b1 != 0 {
+		return 0, true
+	} else if v&0b10 != 0 {
+		return 1 << 14, true
+	}
+	return 0, false
+}
+
+// encodeXs2223 is the implementation of the following encoding logic:
+// Is the index extend and shift specifier,
+// xs	<mod>
+// 0	UXTW
+// 1	SXTW
+// bit range mappings:
+// xs: [22:23)
+func encodeXs2223(v uint32) (uint32, bool) {
+	if v&0b1 != 0 {
+		return 0, true
+	} else if v&0b10 != 0 {
+		return 1 << 22, true
+	}
+	return 0, false
+}
+
+// encodeMsz1012Amount is the implementation of the following encoding logic:
+// Is the index shift amount,
+// msz	<amount>
+// 00	[absent]
+// 01	#1
+// 10	#2
+// 11	#3
+// bit range mappings:
+// msz: [10:12)
+func encodeMsz1012Amount(v uint32) (uint32, bool) {
+	if v <= 3 {
+		return v << 10, true
+	}
+	return 0, false
+}
+
+// encodeZn510V2 is the implementation of the following encoding logic:
+// Is the name of the base scalable vector register, encoded in the "Zn" field.
+// bit range mappings:
+// Zn: [5:10)
+func encodeZn510V2(v uint32) (uint32, bool) {
+	if !stripRawZ(&v) {
+		return 0, false
+	}
+	return v << 5, true
+}
+
 // encodeVd is the implementation of the following encoding logic:
 // Is the name of the destination SIMD&FP register, encoded in the "Vd" field.
 // bit range mappings:
@@ -1140,6 +1408,9 @@ func encodePd(v uint32) (uint32, bool) {
 // bit range mappings:
 // Zd: [0:5)
 func encodeZd(v uint32) (uint32, bool) {
+	if !stripRawZ(&v) {
+		return 0, false
+	}
 	return v, true
 }
 
@@ -1170,9 +1441,23 @@ func encodePd04(v uint32) (uint32, bool) {
 // bit range mappings:
 // Zn: [5:10)
 func encodeZn510MultiSrc1(v uint32) (uint32, bool) {
+	if !stripRawZ(&v) {
+		return 0, false
+	}
 	return v << 5, true
 }
 
+// encodeZt051 is the implementation of the following encoding logic:
+// Is the name of the first scalable vector register to be transferred, encoded in the "Zt" field.
+// bit range mappings:
+// Zt: [0:5)
+func encodeZt051(v uint32) (uint32, bool) {
+	if !stripRawZ(&v) {
+		return 0, false
+	}
+	return v, true
+}
+
 // encodePdnDest is the implementation of the following encoding logic:
 // Is the name of the first source and destination scalable predicate register, encoded in the "Pdn" field.
 // bit range mappings:
@@ -1186,6 +1471,9 @@ func encodePdnDest(v uint32) (uint32, bool) {
 // bit range mappings:
 // Zdn: [0:5)
 func encodeZdnDest(v uint32) (uint32, bool) {
+	if !stripRawZ(&v) {
+		return 0, false
+	}
 	return v, true
 }
 
@@ -1209,11 +1497,14 @@ func encodePn59(v uint32) (uint32, bool) {
 	return v << 5, true
 }
 
-// encodeZn510 is the implementation of the following encoding logic:
+// encodeZn510V1 is the implementation of the following encoding logic:
 // Is the name of the first source scalable vector register, encoded in the "Zn" field.
 // bit range mappings:
 // Zn: [5:10)
-func encodeZn510(v uint32) (uint32, bool) {
+func encodeZn510V1(v uint32) (uint32, bool) {
+	if !stripRawZ(&v) {
+		return 0, false
+	}
 	return v << 5, true
 }
 
@@ -1225,6 +1516,17 @@ func encodeZn510Table1(v uint32) (uint32, bool) {
 	return v << 5, true
 }
 
+// encodeZt054 is the implementation of the following encoding logic:
+// Is the name of the fourth scalable vector register to be transferred, encoded as "Zt" plus 3 modulo 32.
+// bit range mappings:
+// Zt: [0:5)
+func encodeZt054(v uint32) (uint32, bool) {
+	if !stripRawZ(&v) {
+		return 0, false
+	}
+	return (v - 3) % 32, true
+}
+
 // encodePg1013 is the implementation of the following encoding logic:
 // Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
 // bit range mappings:
@@ -1260,6 +1562,28 @@ func encodePg59(v uint32) (uint32, bool) {
 	return v << 5, true
 }
 
+// encodeZm1621V3 is the implementation of the following encoding logic:
+// Is the name of the offset scalable vector register, encoded in the "Zm" field.
+// bit range mappings:
+// Zm: [16:21)
+func encodeZm1621V3(v uint32) (uint32, bool) {
+	if !stripRawZ(&v) {
+		return 0, false
+	}
+	return v << 16, true
+}
+
+// encodeZt05 is the implementation of the following encoding logic:
+// Is the name of the scalable vector register to be transferred, encoded in the "Zt" field.
+// bit range mappings:
+// Zt: [0:5)
+func encodeZt05(v uint32) (uint32, bool) {
+	if !stripRawZ(&v) {
+		return 0, false
+	}
+	return v, true
+}
+
 // encodePd14Plus1 is the implementation of the following encoding logic:
 // Is the name of the second destination scalable predicate register, encoded as "Pd" times 2 plus 1.
 // bit range mappings:
@@ -1285,9 +1609,23 @@ func encodePd04Plus1(v uint32) (uint32, bool) {
 // bit range mappings:
 // Zn: [5:10)
 func encodeZn510MultiSrc2(v uint32) (uint32, bool) {
+	if !stripRawZ(&v) {
+		return 0, false
+	}
 	return (v - 1) << 5, true
 }
 
+// encodeZt052 is the implementation of the following encoding logic:
+// Is the name of the second scalable vector register to be transferred, encoded as "Zt" plus 1 modulo 32.
+// bit range mappings:
+// Zt: [0:5)
+func encodeZt052(v uint32) (uint32, bool) {
+	if !stripRawZ(&v) {
+		return 0, false
+	}
+	return (v - 1) % 32, true
+}
+
 // encodePdmDest is the implementation of the following encoding logic:
 // Is the name of the second source and destination scalable predicate register, encoded in the "Pdm" field.
 // bit range mappings:
@@ -1301,6 +1639,9 @@ func encodePdmDest(v uint32) (uint32, bool) {
 // bit range mappings:
 // Zda: [0:5)
 func encodeZdaDest(v uint32) (uint32, bool) {
+	if !stripRawZ(&v) {
+		return 0, false
+	}
 	return v, true
 }
 
@@ -1328,6 +1669,9 @@ func encodeZm_1619_Range0_7V2(v uint32) (uint32, bool) {
 // bit range mappings:
 // Zm: [16:21)
 func encodeZm1621V2(v uint32) (uint32, bool) {
+	if !stripRawZ(&v) {
+		return 0, false
+	}
 	return v << 16, true
 }
 
@@ -1336,6 +1680,9 @@ func encodeZm1621V2(v uint32) (uint32, bool) {
 // bit range mappings:
 // Zm: [5:10)
 func encodeZm510V1(v uint32) (uint32, bool) {
+	if !stripRawZ(&v) {
+		return 0, false
+	}
 	return (v & 31) << 5, true
 }
 
@@ -1360,6 +1707,9 @@ func encodePdnSrcDst(v uint32) (uint32, bool) {
 // bit range mappings:
 // Zdn: [0:5)
 func encodeZdnSrcDst(v uint32) (uint32, bool) {
+	if !stripRawZ(&v) {
+		return 0, false
+	}
 	return v, true
 }
 
@@ -1384,6 +1734,9 @@ func encodePn59v2(v uint32) (uint32, bool) {
 // bit range mappings:
 // Zm: [16:21)
 func encodeZm1621V1(v uint32) (uint32, bool) {
+	if !stripRawZ(&v) {
+		return 0, false
+	}
 	return v << 16, true
 }
 
@@ -1392,6 +1745,9 @@ func encodeZm1621V1(v uint32) (uint32, bool) {
 // bit range mappings:
 // Zm: [5:10)
 func encodeZm510V2(v uint32) (uint32, bool) {
+	if !stripRawZ(&v) {
+		return 0, false
+	}
 	return (v & 31) << 5, true
 }
 
@@ -1400,6 +1756,9 @@ func encodeZm510V2(v uint32) (uint32, bool) {
 // bit range mappings:
 // Zn: [5:10)
 func encodeZn510Src(v uint32) (uint32, bool) {
+	if !stripRawZ(&v) {
+		return 0, false
+	}
 	return (v & 31) << 5, true
 }
 
@@ -1411,11 +1770,25 @@ func encodeZn510Table3(v uint32) (uint32, bool) {
 	return v << 5, true
 }
 
+// encodeZt053 is the implementation of the following encoding logic:
+// Is the name of the third scalable vector register to be transferred, encoded as "Zt" plus 2 modulo 32.
+// bit range mappings:
+// Zt: [0:5)
+func encodeZt053(v uint32) (uint32, bool) {
+	if !stripRawZ(&v) {
+		return 0, false
+	}
+	return (v - 2) % 32, true
+}
+
 // encodeZda3RdSrcDst is the implementation of the following encoding logic:
 // Is the name of the third source and destination scalable vector register, encoded in the "Zda" field.
 // bit range mappings:
 // Zda: [0:5)
 func encodeZda3RdSrcDst(v uint32) (uint32, bool) {
+	if !stripRawZ(&v) {
+		return 0, false
+	}
 	return v, true
 }
 
@@ -1424,6 +1797,9 @@ func encodeZda3RdSrcDst(v uint32) (uint32, bool) {
 // bit range mappings:
 // Za: [16:21)
 func encodeZa16213Rd(v uint32) (uint32, bool) {
+	if !stripRawZ(&v) {
+		return 0, false
+	}
 	return v << 16, true
 }
 
@@ -1432,6 +1808,9 @@ func encodeZa16213Rd(v uint32) (uint32, bool) {
 // bit range mappings:
 // Za: [5:10)
 func encodeZa5103Rd(v uint32) (uint32, bool) {
+	if !stripRawZ(&v) {
+		return 0, false
+	}
 	return v << 5, true
 }
 
@@ -1440,6 +1819,9 @@ func encodeZa5103Rd(v uint32) (uint32, bool) {
 // bit range mappings:
 // Zk: [5:10)
 func encodeZk5103Rd(v uint32) (uint32, bool) {
+	if !stripRawZ(&v) {
+		return 0, false
+	}
 	return v << 5, true
 }
 
@@ -1472,6 +1854,9 @@ func encodePv59(v uint32) (uint32, bool) {
 // bit range mappings:
 // Rd: [0:5)
 func encodeRd05ZR(v uint32) (uint32, bool) {
+	if !checkIsR(v) {
+		return 0, false
+	}
 	if v == REG_RSP {
 		return 0, false
 	}
@@ -1479,11 +1864,14 @@ func encodeRd05ZR(v uint32) (uint32, bool) {
 	return v & 31, true
 }
 
-// encodeRn510SP is the implementation of the following encoding logic:
+// encodeRn510SPV1 is the implementation of the following encoding logic:
 // Is the number [0-30] of the general-purpose source register or the name SP (31), encoded in the "Rn" field.
 // bit range mappings:
 // Rn: [5:10)
-func encodeRn510SP(v uint32) (uint32, bool) {
+func encodeRn510SPV1(v uint32) (uint32, bool) {
+	if !checkIsR(v) {
+		return 0, false
+	}
 	if v == REG_R31 {
 		return 0, false
 	}
@@ -1498,6 +1886,9 @@ func encodeRn510SP(v uint32) (uint32, bool) {
 // bit range mappings:
 // Rdn: [0:5)
 func encodeRdn05ZR(v uint32) (uint32, bool) {
+	if !checkIsR(v) {
+		return 0, false
+	}
 	if v == REG_RSP {
 		return 0, false
 	}
@@ -1509,6 +1900,9 @@ func encodeRdn05ZR(v uint32) (uint32, bool) {
 // bit range mappings:
 // Rm: [16:21)
 func encodeRm1621ZR(v uint32) (uint32, bool) {
+	if !checkIsR(v) {
+		return 0, false
+	}
 	if v == REG_RSP {
 		return 0, false
 	}
@@ -1520,6 +1914,9 @@ func encodeRm1621ZR(v uint32) (uint32, bool) {
 // bit range mappings:
 // Rm: [5:10)
 func encodeRm510ZR(v uint32) (uint32, bool) {
+	if !checkIsR(v) {
+		return 0, false
+	}
 	if v == REG_RSP {
 		return 0, false
 	}
@@ -1531,6 +1928,9 @@ func encodeRm510ZR(v uint32) (uint32, bool) {
 // bit range mappings:
 // Rn: [5:10)
 func encodeRn510ZR(v uint32) (uint32, bool) {
+	if !checkIsR(v) {
+		return 0, false
+	}
 	if v == REG_RSP {
 		return 0, false
 	}
@@ -1569,6 +1969,21 @@ func encodeVdn05(v uint32) (uint32, bool) {
 	return v & 31, true
 }
 
+// encodeRm1621XZR is the implementation of the following encoding logic:
+// Is the optional 64-bit name of the general-purpose offset register, defaulting to XZR, encoded in the "Rm" field.
+// bit range mappings:
+// Rm: [16:21)
+func encodeRm1621XZR(v uint32) (uint32, bool) {
+	if v == 0 {
+		// absent case, according to the spec this should be ZR (R31)
+		return 31, true
+	}
+	if !checkIsR(v) {
+		return 0, false
+	}
+	return (v & 31) << 16, true
+}
+
 // encodeI189 is the implementation of the following encoding logic:
 // Is the portion index, in the range 0 to 1, encoded in the "i1" field.
 // bit range mappings:
@@ -1696,6 +2111,30 @@ func encodeSizeImm13NoOp(v uint32) (uint32, bool) {
 	return codeNoOp, false
 }
 
+// encodeSize2123V1 is the implementation of the following encoding logic:
+// Is the size specifier,
+// size	<T>
+// 00	B
+// 01	H
+// 10	S
+// 11	D
+// bit range mappings:
+// size: [21:23)
+func encodeSize2123V1(v uint32) (uint32, bool) {
+	switch v {
+	case ARNG_B:
+		return 0, true
+	case ARNG_H:
+		return 1 << 21, true
+	case ARNG_S:
+		return 2 << 21, true
+	case ARNG_D:
+		return 3 << 21, true
+	default:
+		return 0, false
+	}
+}
+
 // encodeSizeBHSD2224 is the implementation of the following encoding logic:
 // Is the size specifier,
 // size	<T>
@@ -1803,6 +2242,27 @@ func encodeSizeHSD1719(v uint32) (uint32, bool) {
 	return 0, false
 }
 
+// encodeSize2123V2 is the implementation of the following encoding logic:
+// Is the size specifier,
+// size	<T>
+// 00	RESERVED
+// 01	H
+// 10	S
+// 11	D
+// bit range mappings:
+// size: [21:23)
+func encodeSize2123V2(v uint32) (uint32, bool) {
+	switch v {
+	case ARNG_H:
+		return 1 << 21, true
+	case ARNG_S:
+		return 2 << 21, true
+	case ARNG_D:
+		return 3 << 21, true
+	}
+	return 0, false
+}
+
 // encodeSizeHSD2224 is the implementation of the following encoding logic:
 // Is the size specifier,
 // size	<T>
diff --git a/src/cmd/internal/obj/arm64/goops_gen.go b/src/cmd/internal/obj/arm64/goops_gen.go
index ceb403eb66..53816d3ead 100644
--- a/src/cmd/internal/obj/arm64/goops_gen.go
+++ b/src/cmd/internal/obj/arm64/goops_gen.go
@@ -98,6 +98,7 @@ const (
 	AZADDQP
 	AZADDQV
 	AZADDSUBP
+	AZADR
 	AZAESD
 	AZAESE
 	AZAESIMC
@@ -328,6 +329,51 @@ const (
 	AZLASTBH
 	AZLASTBS
 	AZLASTBW
+	AZLD1B
+	AZLD1D
+	AZLD1H
+	AZLD1Q
+	AZLD1ROB
+	AZLD1ROD
+	AZLD1ROH
+	AZLD1ROW
+	AZLD1RQB
+	AZLD1RQD
+	AZLD1RQH
+	AZLD1RQW
+	AZLD1SB
+	AZLD1SH
+	AZLD1SW
+	AZLD1W
+	AZLD2B
+	AZLD2D
+	AZLD2H
+	AZLD2Q
+	AZLD2W
+	AZLD3B
+	AZLD3D
+	AZLD3H
+	AZLD3Q
+	AZLD3W
+	AZLD4B
+	AZLD4D
+	AZLD4H
+	AZLD4Q
+	AZLD4W
+	AZLDFF1B
+	AZLDFF1D
+	AZLDFF1H
+	AZLDFF1SB
+	AZLDFF1SH
+	AZLDFF1SW
+	AZLDFF1W
+	AZLDNT1B
+	AZLDNT1D
+	AZLDNT1H
+	AZLDNT1SB
+	AZLDNT1SH
+	AZLDNT1SW
+	AZLDNT1W
 	AZLSL
 	AZLSLR
 	AZLSR
@@ -478,6 +524,30 @@ const (
 	AZSSUBLTB
 	AZSSUBWB
 	AZSSUBWT
+	AZST1B
+	AZST1D
+	AZST1H
+	AZST1Q
+	AZST1W
+	AZST2B
+	AZST2D
+	AZST2H
+	AZST2Q
+	AZST2W
+	AZST3B
+	AZST3D
+	AZST3H
+	AZST3Q
+	AZST3W
+	AZST4B
+	AZST4D
+	AZST4H
+	AZST4Q
+	AZST4W
+	AZSTNT1B
+	AZSTNT1D
+	AZSTNT1H
+	AZSTNT1W
 	AZSUB
 	AZSUBHNB
 	AZSUBHNT
diff --git a/src/cmd/internal/obj/arm64/inst.go b/src/cmd/internal/obj/arm64/inst.go
index 688e990bcf..0bf4b9950d 100644
--- a/src/cmd/internal/obj/arm64/inst.go
+++ b/src/cmd/internal/obj/arm64/inst.go
@@ -143,6 +143,9 @@ func aclass(a *obj.Addr) AClass {
 			return AC_REGLIST4
 		}
 	}
+	if a.Type == obj.TYPE_MEM {
+		return AC_MEMEXT
+	}
 	panic("unknown AClass")
 }
 
@@ -329,6 +332,39 @@ func addrComponent(a *obj.Addr, acl AClass, index int) uint32 {
 		default:
 			panic(fmt.Errorf("unknown elm index at %d in AClass %d", index, acl))
 		}
+	//	AClass: AC_MEMEXT
+	//	GNU mnemonic: [<reg1>.<T1>, <reg2>.<T2>, <mod> <amount>]
+	//	Go mnemonic:
+	//		(reg2.T2.mod<<amount)(reg1.T1)
+	//	Encoding:
+	//		Type = TYPE_MEM
+	//		Reg = Index register (with arrangement if applicable)
+	//		Index = Base register (with arrangement if applicable)
+	//		Scale = Packed mod and amount
+	case AC_MEMEXT:
+		switch index {
+		case 0:
+			return uint32(a.Index)
+		case 1:
+			return uint32((a.Index >> 5) & 15)
+		case 2:
+			return uint32(a.Reg)
+		case 3:
+			return uint32((a.Reg >> 5) & 15)
+		case 4:
+			// mod is either 1 (UXTW), 2 (SXTW), or 4 (LSL)
+			mod := uint32((a.Scale >> 9) & 0x7)
+			amount := uint32((a.Scale >> 12) & 0x7)
+			if mod == 0 && amount > 0 {
+				// LSL is implied when no extension is specified but amount > 0
+				mod |= 1 << 2
+			}
+			return mod
+		case 5:
+			return uint32((a.Scale >> 12) & 0x7)
+		default:
+			panic(fmt.Errorf("unknown elm index at %d in AClass %d", index, acl))
+		}
 	}
 	// TODO: handle more AClasses.
 	panic(fmt.Errorf("unknown AClass %d", acl))
@@ -696,7 +732,8 @@ func (i *instEncoder) tryEncode(p *obj.Prog) (uint32, bool) {
 					}
 					return 0, false
 				}
-				if enc.comp != enc_NIL {
+				if enc.comp != enc_NIL && specialB != codeNoOp {
+					// NoOp encodings don't need bookkeeping.
 					encoded[enc.comp] = b
 				}
 			} else {
@@ -704,6 +741,5 @@ func (i *instEncoder) tryEncode(p *obj.Prog) (uint32, bool) {
 			}
 		}
 	}
-
 	return bin, true
 }
diff --git a/src/cmd/internal/obj/arm64/inst_gen.go b/src/cmd/internal/obj/arm64/inst_gen.go
index ada9c32fa7..6c68daa26b 100644
--- a/src/cmd/internal/obj/arm64/inst_gen.go
+++ b/src/cmd/internal/obj/arm64/inst_gen.go
@@ -927,6 +927,27 @@ var insts = [][]instEncoder{
 			args:      Zm_T__Zn_T__Zd_T__1,
 		},
 	},
+	// ZADR
+	{
+		// ZADR [<Zn>.D, <Zm>.D, SXTW{<amount>}], <Zd>.D
+		{
+			goOp:      AZADR,
+			fixedBits: 0x420a000,
+			args:      Zn_D__Zm_D__SXTWamount___Zd_D,
+		},
+		// ZADR [<Zn>.D, <Zm>.D, UXTW{<amount>}], <Zd>.D
+		{
+			goOp:      AZADR,
+			fixedBits: 0x460a000,
+			args:      Zn_D__Zm_D__UXTWamount___Zd_D,
+		},
+		// ZADR [<Zn>.<T>, <Zm>.<T>{, <mod> <amount>}], <Zd>.<T>
+		{
+			goOp:      AZADR,
+			fixedBits: 0x4a0a000,
+			args:      Zn_T__Zm_T__mod_amount___Zd_T,
+		},
+	},
 	// ZAESD
 	{
 		// ZAESD <Zm>.B, <Zdn>.B, <Zdn>.B
@@ -4011,6 +4032,939 @@ var insts = [][]instEncoder{
 			args:      Zn_T__Pg__Rd,
 		},
 	},
+	// ZLD1B
+	{
+		// ZLD1B [<Xn|SP>, <Xm>], <Pg>/Z, { <Zt>.B }
+		{
+			goOp:      AZLD1B,
+			fixedBits: 0xa4004000,
+			args:      XnSP__Xm___PgZ___Zt_B_,
+		},
+		// ZLD1B [<Xn|SP>, <Xm>], <Pg>/Z, { <Zt>.D }
+		{
+			goOp:      AZLD1B,
+			fixedBits: 0xa4604000,
+			args:      XnSP__Xm___PgZ___Zt_D_,
+		},
+		// ZLD1B [<Xn|SP>, <Xm>], <Pg>/Z, { <Zt>.H }
+		{
+			goOp:      AZLD1B,
+			fixedBits: 0xa4204000,
+			args:      XnSP__Xm___PgZ___Zt_H_,
+		},
+		// ZLD1B [<Xn|SP>, <Xm>], <Pg>/Z, { <Zt>.S }
+		{
+			goOp:      AZLD1B,
+			fixedBits: 0xa4404000,
+			args:      XnSP__Xm___PgZ___Zt_S_,
+		},
+		// ZLD1B [<Xn|SP>, <Zm>.D], <Pg>/Z, { <Zt>.D }
+		{
+			goOp:      AZLD1B,
+			fixedBits: 0xc440c000,
+			args:      XnSP__Zm_D___PgZ___Zt_D_,
+		},
+		// ZLD1B [<Xn|SP>, <Zm>.D, <mod>], <Pg>/Z, { <Zt>.D }
+		{
+			goOp:      AZLD1B,
+			fixedBits: 0xc4004000,
+			args:      XnSP__Zm_D__mod___PgZ___Zt_D_,
+		},
+		// ZLD1B [<Xn|SP>, <Zm>.S, <mod>], <Pg>/Z, { <Zt>.S }
+		{
+			goOp:      AZLD1B,
+			fixedBits: 0x84004000,
+			args:      XnSP__Zm_S__mod___PgZ___Zt_S_,
+		},
+	},
+	// ZLD1D
+	{
+		// ZLD1D [<Xn|SP>, <Zm>.D, LSL #3], <Pg>/Z, { <Zt>.D }
+		{
+			goOp:      AZLD1D,
+			fixedBits: 0xc5e0c000,
+			args:      XnSP__Zm_D__LSL_c3___PgZ___Zt_D_,
+		},
+		// ZLD1D [<Xn|SP>, <Zm>.D], <Pg>/Z, { <Zt>.D }
+		{
+			goOp:      AZLD1D,
+			fixedBits: 0xc5c0c000,
+			args:      XnSP__Zm_D___PgZ___Zt_D_,
+		},
+		// ZLD1D [<Xn|SP>, <Zm>.D, <mod>], <Pg>/Z, { <Zt>.D }
+		{
+			goOp:      AZLD1D,
+			fixedBits: 0xc5804000,
+			args:      XnSP__Zm_D__mod___PgZ___Zt_D_,
+		},
+		// ZLD1D [<Xn|SP>, <Zm>.D, <mod> #3], <Pg>/Z, { <Zt>.D }
+		{
+			goOp:      AZLD1D,
+			fixedBits: 0xc5a04000,
+			args:      XnSP__Zm_D__mod_c3___PgZ___Zt_D_,
+		},
+	},
+	// ZLD1H
+	{
+		// ZLD1H [<Xn|SP>, <Xm>, LSL #1], <Pg>/Z, { <Zt>.D }
+		{
+			goOp:      AZLD1H,
+			fixedBits: 0xa4e04000,
+			args:      XnSP__Xm__LSL_c1___PgZ___Zt_D_,
+		},
+		// ZLD1H [<Xn|SP>, <Xm>, LSL #1], <Pg>/Z, { <Zt>.H }
+		{
+			goOp:      AZLD1H,
+			fixedBits: 0xa4a04000,
+			args:      XnSP__Xm__LSL_c1___PgZ___Zt_H_,
+		},
+		// ZLD1H [<Xn|SP>, <Xm>, LSL #1], <Pg>/Z, { <Zt>.S }
+		{
+			goOp:      AZLD1H,
+			fixedBits: 0xa4c04000,
+			args:      XnSP__Xm__LSL_c1___PgZ___Zt_S_,
+		},
+		// ZLD1H [<Xn|SP>, <Zm>.D, LSL #1], <Pg>/Z, { <Zt>.D }
+		{
+			goOp:      AZLD1H,
+			fixedBits: 0xc4e0c000,
+			args:      XnSP__Zm_D__LSL_c1___PgZ___Zt_D_,
+		},
+		// ZLD1H [<Xn|SP>, <Zm>.D], <Pg>/Z, { <Zt>.D }
+		{
+			goOp:      AZLD1H,
+			fixedBits: 0xc4c0c000,
+			args:      XnSP__Zm_D___PgZ___Zt_D_,
+		},
+		// ZLD1H [<Xn|SP>, <Zm>.D, <mod>], <Pg>/Z, { <Zt>.D }
+		{
+			goOp:      AZLD1H,
+			fixedBits: 0xc4804000,
+			args:      XnSP__Zm_D__mod___PgZ___Zt_D_,
+		},
+		// ZLD1H [<Xn|SP>, <Zm>.D, <mod> #1], <Pg>/Z, { <Zt>.D }
+		{
+			goOp:      AZLD1H,
+			fixedBits: 0xc4a04000,
+			args:      XnSP__Zm_D__mod_c1___PgZ___Zt_D_,
+		},
+		// ZLD1H [<Xn|SP>, <Zm>.S, <mod>], <Pg>/Z, { <Zt>.S }
+		{
+			goOp:      AZLD1H,
+			fixedBits: 0x84804000,
+			args:      XnSP__Zm_S__mod___PgZ___Zt_S_,
+		},
+		// ZLD1H [<Xn|SP>, <Zm>.S, <mod> #1], <Pg>/Z, { <Zt>.S }
+		{
+			goOp:      AZLD1H,
+			fixedBits: 0x84a04000,
+			args:      XnSP__Zm_S__mod_c1___PgZ___Zt_S_,
+		},
+	},
+	// ZLD1Q
+	{
+		// ZLD1Q [<Zn>.D{, <Xm>}], <Pg>/Z, { <Zt>.Q }
+		{
+			goOp:      AZLD1Q,
+			fixedBits: 0xc400a000,
+			args:      Zn_D__Xm___PgZ___Zt_Q_,
+		},
+	},
+	// ZLD1ROB
+	{
+		// ZLD1ROB [<Xn|SP>, <Xm>], <Pg>/Z, { <Zt>.B }
+		{
+			goOp:      AZLD1ROB,
+			fixedBits: 0xa4200000,
+			args:      XnSP__Xm___PgZ___Zt_B_,
+		},
+	},
+	// ZLD1ROD
+	{
+		// ZLD1ROD [<Xn|SP>, <Xm>, LSL #3], <Pg>/Z, { <Zt>.D }
+		{
+			goOp:      AZLD1ROD,
+			fixedBits: 0xa5a00000,
+			args:      XnSP__Xm__LSL_c3___PgZ___Zt_D_,
+		},
+	},
+	// ZLD1ROH
+	{
+		// ZLD1ROH [<Xn|SP>, <Xm>, LSL #1], <Pg>/Z, { <Zt>.H }
+		{
+			goOp:      AZLD1ROH,
+			fixedBits: 0xa4a00000,
+			args:      XnSP__Xm__LSL_c1___PgZ___Zt_H_,
+		},
+	},
+	// ZLD1ROW
+	{
+		// ZLD1ROW [<Xn|SP>, <Xm>, LSL #2], <Pg>/Z, { <Zt>.S }
+		{
+			goOp:      AZLD1ROW,
+			fixedBits: 0xa5200000,
+			args:      XnSP__Xm__LSL_c2___PgZ___Zt_S_,
+		},
+	},
+	// ZLD1RQB
+	{
+		// ZLD1RQB [<Xn|SP>, <Xm>], <Pg>/Z, { <Zt>.B }
+		{
+			goOp:      AZLD1RQB,
+			fixedBits: 0xa4000000,
+			args:      XnSP__Xm___PgZ___Zt_B_,
+		},
+	},
+	// ZLD1RQD
+	{
+		// ZLD1RQD [<Xn|SP>, <Xm>, LSL #3], <Pg>/Z, { <Zt>.D }
+		{
+			goOp:      AZLD1RQD,
+			fixedBits: 0xa5800000,
+			args:      XnSP__Xm__LSL_c3___PgZ___Zt_D_,
+		},
+	},
+	// ZLD1RQH
+	{
+		// ZLD1RQH [<Xn|SP>, <Xm>, LSL #1], <Pg>/Z, { <Zt>.H }
+		{
+			goOp:      AZLD1RQH,
+			fixedBits: 0xa4800000,
+			args:      XnSP__Xm__LSL_c1___PgZ___Zt_H_,
+		},
+	},
+	// ZLD1RQW
+	{
+		// ZLD1RQW [<Xn|SP>, <Xm>, LSL #2], <Pg>/Z, { <Zt>.S }
+		{
+			goOp:      AZLD1RQW,
+			fixedBits: 0xa5000000,
+			args:      XnSP__Xm__LSL_c2___PgZ___Zt_S_,
+		},
+	},
+	// ZLD1SB
+	{
+		// ZLD1SB [<Xn|SP>, <Xm>], <Pg>/Z, { <Zt>.D }
+		{
+			goOp:      AZLD1SB,
+			fixedBits: 0xa5804000,
+			args:      XnSP__Xm___PgZ___Zt_D_,
+		},
+		// ZLD1SB [<Xn|SP>, <Xm>], <Pg>/Z, { <Zt>.H }
+		{
+			goOp:      AZLD1SB,
+			fixedBits: 0xa5c04000,
+			args:      XnSP__Xm___PgZ___Zt_H_,
+		},
+		// ZLD1SB [<Xn|SP>, <Xm>], <Pg>/Z, { <Zt>.S }
+		{
+			goOp:      AZLD1SB,
+			fixedBits: 0xa5a04000,
+			args:      XnSP__Xm___PgZ___Zt_S_,
+		},
+		// ZLD1SB [<Xn|SP>, <Zm>.D], <Pg>/Z, { <Zt>.D }
+		{
+			goOp:      AZLD1SB,
+			fixedBits: 0xc4408000,
+			args:      XnSP__Zm_D___PgZ___Zt_D_,
+		},
+		// ZLD1SB [<Xn|SP>, <Zm>.D, <mod>], <Pg>/Z, { <Zt>.D }
+		{
+			goOp:      AZLD1SB,
+			fixedBits: 0xc4000000,
+			args:      XnSP__Zm_D__mod___PgZ___Zt_D_,
+		},
+		// ZLD1SB [<Xn|SP>, <Zm>.S, <mod>], <Pg>/Z, { <Zt>.S }
+		{
+			goOp:      AZLD1SB,
+			fixedBits: 0x84000000,
+			args:      XnSP__Zm_S__mod___PgZ___Zt_S_,
+		},
+	},
+	// ZLD1SH
+	{
+		// ZLD1SH [<Xn|SP>, <Xm>, LSL #1], <Pg>/Z, { <Zt>.D }
+		{
+			goOp:      AZLD1SH,
+			fixedBits: 0xa5004000,
+			args:      XnSP__Xm__LSL_c1___PgZ___Zt_D_,
+		},
+		// ZLD1SH [<Xn|SP>, <Xm>, LSL #1], <Pg>/Z, { <Zt>.S }
+		{
+			goOp:      AZLD1SH,
+			fixedBits: 0xa5204000,
+			args:      XnSP__Xm__LSL_c1___PgZ___Zt_S_,
+		},
+		// ZLD1SH [<Xn|SP>, <Zm>.D, LSL #1], <Pg>/Z, { <Zt>.D }
+		{
+			goOp:      AZLD1SH,
+			fixedBits: 0xc4e08000,
+			args:      XnSP__Zm_D__LSL_c1___PgZ___Zt_D_,
+		},
+		// ZLD1SH [<Xn|SP>, <Zm>.D], <Pg>/Z, { <Zt>.D }
+		{
+			goOp:      AZLD1SH,
+			fixedBits: 0xc4c08000,
+			args:      XnSP__Zm_D___PgZ___Zt_D_,
+		},
+		// ZLD1SH [<Xn|SP>, <Zm>.D, <mod>], <Pg>/Z, { <Zt>.D }
+		{
+			goOp:      AZLD1SH,
+			fixedBits: 0xc4800000,
+			args:      XnSP__Zm_D__mod___PgZ___Zt_D_,
+		},
+		// ZLD1SH [<Xn|SP>, <Zm>.D, <mod> #1], <Pg>/Z, { <Zt>.D }
+		{
+			goOp:      AZLD1SH,
+			fixedBits: 0xc4a00000,
+			args:      XnSP__Zm_D__mod_c1___PgZ___Zt_D_,
+		},
+		// ZLD1SH [<Xn|SP>, <Zm>.S, <mod>], <Pg>/Z, { <Zt>.S }
+		{
+			goOp:      AZLD1SH,
+			fixedBits: 0x84800000,
+			args:      XnSP__Zm_S__mod___PgZ___Zt_S_,
+		},
+		// ZLD1SH [<Xn|SP>, <Zm>.S, <mod> #1], <Pg>/Z, { <Zt>.S }
+		{
+			goOp:      AZLD1SH,
+			fixedBits: 0x84a00000,
+			args:      XnSP__Zm_S__mod_c1___PgZ___Zt_S_,
+		},
+	},
+	// ZLD1SW
+	{
+		// ZLD1SW [<Xn|SP>, <Xm>, LSL #2], <Pg>/Z, { <Zt>.D }
+		{
+			goOp:      AZLD1SW,
+			fixedBits: 0xa4804000,
+			args:      XnSP__Xm__LSL_c2___PgZ___Zt_D_,
+		},
+		// ZLD1SW [<Xn|SP>, <Zm>.D, LSL #2], <Pg>/Z, { <Zt>.D }
+		{
+			goOp:      AZLD1SW,
+			fixedBits: 0xc5608000,
+			args:      XnSP__Zm_D__LSL_c2___PgZ___Zt_D_,
+		},
+		// ZLD1SW [<Xn|SP>, <Zm>.D], <Pg>/Z, { <Zt>.D }
+		{
+			goOp:      AZLD1SW,
+			fixedBits: 0xc5408000,
+			args:      XnSP__Zm_D___PgZ___Zt_D_,
+		},
+		// ZLD1SW [<Xn|SP>, <Zm>.D, <mod>], <Pg>/Z, { <Zt>.D }
+		{
+			goOp:      AZLD1SW,
+			fixedBits: 0xc5000000,
+			args:      XnSP__Zm_D__mod___PgZ___Zt_D_,
+		},
+		// ZLD1SW [<Xn|SP>, <Zm>.D, <mod> #2], <Pg>/Z, { <Zt>.D }
+		{
+			goOp:      AZLD1SW,
+			fixedBits: 0xc5200000,
+			args:      XnSP__Zm_D__mod_c2___PgZ___Zt_D_,
+		},
+	},
+	// ZLD1W
+	{
+		// ZLD1W [<Xn|SP>, <Zm>.D, LSL #2], <Pg>/Z, { <Zt>.D }
+		{
+			goOp:      AZLD1W,
+			fixedBits: 0xc560c000,
+			args:      XnSP__Zm_D__LSL_c2___PgZ___Zt_D_,
+		},
+		// ZLD1W [<Xn|SP>, <Zm>.D], <Pg>/Z, { <Zt>.D }
+		{
+			goOp:      AZLD1W,
+			fixedBits: 0xc540c000,
+			args:      XnSP__Zm_D___PgZ___Zt_D_,
+		},
+		// ZLD1W [<Xn|SP>, <Zm>.D, <mod>], <Pg>/Z, { <Zt>.D }
+		{
+			goOp:      AZLD1W,
+			fixedBits: 0xc5004000,
+			args:      XnSP__Zm_D__mod___PgZ___Zt_D_,
+		},
+		// ZLD1W [<Xn|SP>, <Zm>.D, <mod> #2], <Pg>/Z, { <Zt>.D }
+		{
+			goOp:      AZLD1W,
+			fixedBits: 0xc5204000,
+			args:      XnSP__Zm_D__mod_c2___PgZ___Zt_D_,
+		},
+		// ZLD1W [<Xn|SP>, <Zm>.S, <mod>], <Pg>/Z, { <Zt>.S }
+		{
+			goOp:      AZLD1W,
+			fixedBits: 0x85004000,
+			args:      XnSP__Zm_S__mod___PgZ___Zt_S_,
+		},
+		// ZLD1W [<Xn|SP>, <Zm>.S, <mod> #2], <Pg>/Z, { <Zt>.S }
+		{
+			goOp:      AZLD1W,
+			fixedBits: 0x85204000,
+			args:      XnSP__Zm_S__mod_c2___PgZ___Zt_S_,
+		},
+	},
+	// ZLD2B
+	{
+		// ZLD2B [<Xn|SP>, <Xm>], <Pg>/Z, { <Zt1>.B, <Zt2>.B }
+		{
+			goOp:      AZLD2B,
+			fixedBits: 0xa420c000,
+			args:      XnSP__Xm___PgZ___Zt1_B__Zt2_B_,
+		},
+	},
+	// ZLD2D
+	{
+		// ZLD2D [<Xn|SP>, <Xm>, LSL #3], <Pg>/Z, { <Zt1>.D, <Zt2>.D }
+		{
+			goOp:      AZLD2D,
+			fixedBits: 0xa5a0c000,
+			args:      XnSP__Xm__LSL_c3___PgZ___Zt1_D__Zt2_D_,
+		},
+	},
+	// ZLD2H
+	{
+		// ZLD2H [<Xn|SP>, <Xm>, LSL #1], <Pg>/Z, { <Zt1>.H, <Zt2>.H }
+		{
+			goOp:      AZLD2H,
+			fixedBits: 0xa4a0c000,
+			args:      XnSP__Xm__LSL_c1___PgZ___Zt1_H__Zt2_H_,
+		},
+	},
+	// ZLD2Q
+	{
+		// ZLD2Q [<Xn|SP>, <Xm>, LSL #4], <Pg>/Z, { <Zt1>.Q, <Zt2>.Q }
+		{
+			goOp:      AZLD2Q,
+			fixedBits: 0xa4a08000,
+			args:      XnSP__Xm__LSL_c4___PgZ___Zt1_Q__Zt2_Q_,
+		},
+	},
+	// ZLD2W
+	{
+		// ZLD2W [<Xn|SP>, <Xm>, LSL #2], <Pg>/Z, { <Zt1>.S, <Zt2>.S }
+		{
+			goOp:      AZLD2W,
+			fixedBits: 0xa520c000,
+			args:      XnSP__Xm__LSL_c2___PgZ___Zt1_S__Zt2_S_,
+		},
+	},
+	// ZLD3B
+	{
+		// ZLD3B [<Xn|SP>, <Xm>], <Pg>/Z, { <Zt1>.B, <Zt2>.B, <Zt3>.B }
+		{
+			goOp:      AZLD3B,
+			fixedBits: 0xa440c000,
+			args:      XnSP__Xm___PgZ___Zt1_B__Zt2_B__Zt3_B_,
+		},
+	},
+	// ZLD3D
+	{
+		// ZLD3D [<Xn|SP>, <Xm>, LSL #3], <Pg>/Z, { <Zt1>.D, <Zt2>.D, <Zt3>.D }
+		{
+			goOp:      AZLD3D,
+			fixedBits: 0xa5c0c000,
+			args:      XnSP__Xm__LSL_c3___PgZ___Zt1_D__Zt2_D__Zt3_D_,
+		},
+	},
+	// ZLD3H
+	{
+		// ZLD3H [<Xn|SP>, <Xm>, LSL #1], <Pg>/Z, { <Zt1>.H, <Zt2>.H, <Zt3>.H }
+		{
+			goOp:      AZLD3H,
+			fixedBits: 0xa4c0c000,
+			args:      XnSP__Xm__LSL_c1___PgZ___Zt1_H__Zt2_H__Zt3_H_,
+		},
+	},
+	// ZLD3Q
+	{
+		// ZLD3Q [<Xn|SP>, <Xm>, LSL #4], <Pg>/Z, { <Zt1>.Q, <Zt2>.Q, <Zt3>.Q }
+		{
+			goOp:      AZLD3Q,
+			fixedBits: 0xa5208000,
+			args:      XnSP__Xm__LSL_c4___PgZ___Zt1_Q__Zt2_Q__Zt3_Q_,
+		},
+	},
+	// ZLD3W
+	{
+		// ZLD3W [<Xn|SP>, <Xm>, LSL #2], <Pg>/Z, { <Zt1>.S, <Zt2>.S, <Zt3>.S }
+		{
+			goOp:      AZLD3W,
+			fixedBits: 0xa540c000,
+			args:      XnSP__Xm__LSL_c2___PgZ___Zt1_S__Zt2_S__Zt3_S_,
+		},
+	},
+	// ZLD4B
+	{
+		// ZLD4B [<Xn|SP>, <Xm>], <Pg>/Z, { <Zt1>.B, <Zt2>.B, <Zt3>.B, <Zt4>.B }
+		{
+			goOp:      AZLD4B,
+			fixedBits: 0xa460c000,
+			args:      XnSP__Xm___PgZ___Zt1_B__Zt2_B__Zt3_B__Zt4_B_,
+		},
+	},
+	// ZLD4D
+	{
+		// ZLD4D [<Xn|SP>, <Xm>, LSL #3], <Pg>/Z, { <Zt1>.D, <Zt2>.D, <Zt3>.D, <Zt4>.D }
+		{
+			goOp:      AZLD4D,
+			fixedBits: 0xa5e0c000,
+			args:      XnSP__Xm__LSL_c3___PgZ___Zt1_D__Zt2_D__Zt3_D__Zt4_D_,
+		},
+	},
+	// ZLD4H
+	{
+		// ZLD4H [<Xn|SP>, <Xm>, LSL #1], <Pg>/Z, { <Zt1>.H, <Zt2>.H, <Zt3>.H, <Zt4>.H }
+		{
+			goOp:      AZLD4H,
+			fixedBits: 0xa4e0c000,
+			args:      XnSP__Xm__LSL_c1___PgZ___Zt1_H__Zt2_H__Zt3_H__Zt4_H_,
+		},
+	},
+	// ZLD4Q
+	{
+		// ZLD4Q [<Xn|SP>, <Xm>, LSL #4], <Pg>/Z, { <Zt1>.Q, <Zt2>.Q, <Zt3>.Q, <Zt4>.Q }
+		{
+			goOp:      AZLD4Q,
+			fixedBits: 0xa5a08000,
+			args:      XnSP__Xm__LSL_c4___PgZ___Zt1_Q__Zt2_Q__Zt3_Q__Zt4_Q_,
+		},
+	},
+	// ZLD4W
+	{
+		// ZLD4W [<Xn|SP>, <Xm>, LSL #2], <Pg>/Z, { <Zt1>.S, <Zt2>.S, <Zt3>.S, <Zt4>.S }
+		{
+			goOp:      AZLD4W,
+			fixedBits: 0xa560c000,
+			args:      XnSP__Xm__LSL_c2___PgZ___Zt1_S__Zt2_S__Zt3_S__Zt4_S_,
+		},
+	},
+	// ZLDFF1B
+	{
+		// ZLDFF1B [<Xn|SP>{, <Xm>}], <Pg>/Z, { <Zt>.B }
+		{
+			goOp:      AZLDFF1B,
+			fixedBits: 0xa4006000,
+			args:      XnSP__Xm___PgZ___Zt_B__V2,
+		},
+		// ZLDFF1B [<Xn|SP>{, <Xm>}], <Pg>/Z, { <Zt>.D }
+		{
+			goOp:      AZLDFF1B,
+			fixedBits: 0xa4606000,
+			args:      XnSP__Xm___PgZ___Zt_D__V2,
+		},
+		// ZLDFF1B [<Xn|SP>{, <Xm>}], <Pg>/Z, { <Zt>.H }
+		{
+			goOp:      AZLDFF1B,
+			fixedBits: 0xa4206000,
+			args:      XnSP__Xm___PgZ___Zt_H__V2,
+		},
+		// ZLDFF1B [<Xn|SP>{, <Xm>}], <Pg>/Z, { <Zt>.S }
+		{
+			goOp:      AZLDFF1B,
+			fixedBits: 0xa4406000,
+			args:      XnSP__Xm___PgZ___Zt_S__V2,
+		},
+		// ZLDFF1B [<Xn|SP>, <Zm>.D], <Pg>/Z, { <Zt>.D }
+		{
+			goOp:      AZLDFF1B,
+			fixedBits: 0xc440e000,
+			args:      XnSP__Zm_D___PgZ___Zt_D_,
+		},
+		// ZLDFF1B [<Xn|SP>, <Zm>.D, <mod>], <Pg>/Z, { <Zt>.D }
+		{
+			goOp:      AZLDFF1B,
+			fixedBits: 0xc4006000,
+			args:      XnSP__Zm_D__mod___PgZ___Zt_D_,
+		},
+		// ZLDFF1B [<Xn|SP>, <Zm>.S, <mod>], <Pg>/Z, { <Zt>.S }
+		{
+			goOp:      AZLDFF1B,
+			fixedBits: 0x84006000,
+			args:      XnSP__Zm_S__mod___PgZ___Zt_S_,
+		},
+	},
+	// ZLDFF1D
+	{
+		// ZLDFF1D [<Xn|SP>{, <Xm>, LSL #3}], <Pg>/Z, { <Zt>.D }
+		{
+			goOp:      AZLDFF1D,
+			fixedBits: 0xa5e06000,
+			args:      XnSP__Xm__LSL_c3___PgZ___Zt_D__V2,
+		},
+		// ZLDFF1D [<Xn|SP>, <Zm>.D, LSL #3], <Pg>/Z, { <Zt>.D }
+		{
+			goOp:      AZLDFF1D,
+			fixedBits: 0xc5e0e000,
+			args:      XnSP__Zm_D__LSL_c3___PgZ___Zt_D_,
+		},
+		// ZLDFF1D [<Xn|SP>, <Zm>.D], <Pg>/Z, { <Zt>.D }
+		{
+			goOp:      AZLDFF1D,
+			fixedBits: 0xc5c0e000,
+			args:      XnSP__Zm_D___PgZ___Zt_D_,
+		},
+		// ZLDFF1D [<Xn|SP>, <Zm>.D, <mod>], <Pg>/Z, { <Zt>.D }
+		{
+			goOp:      AZLDFF1D,
+			fixedBits: 0xc5806000,
+			args:      XnSP__Zm_D__mod___PgZ___Zt_D_,
+		},
+		// ZLDFF1D [<Xn|SP>, <Zm>.D, <mod> #3], <Pg>/Z, { <Zt>.D }
+		{
+			goOp:      AZLDFF1D,
+			fixedBits: 0xc5a06000,
+			args:      XnSP__Zm_D__mod_c3___PgZ___Zt_D_,
+		},
+	},
+	// ZLDFF1H
+	{
+		// ZLDFF1H [<Xn|SP>{, <Xm>, LSL #1}], <Pg>/Z, { <Zt>.D }
+		{
+			goOp:      AZLDFF1H,
+			fixedBits: 0xa4e06000,
+			args:      XnSP__Xm__LSL_c1___PgZ___Zt_D__V2,
+		},
+		// ZLDFF1H [<Xn|SP>{, <Xm>, LSL #1}], <Pg>/Z, { <Zt>.H }
+		{
+			goOp:      AZLDFF1H,
+			fixedBits: 0xa4a06000,
+			args:      XnSP__Xm__LSL_c1___PgZ___Zt_H__V2,
+		},
+		// ZLDFF1H [<Xn|SP>{, <Xm>, LSL #1}], <Pg>/Z, { <Zt>.S }
+		{
+			goOp:      AZLDFF1H,
+			fixedBits: 0xa4c06000,
+			args:      XnSP__Xm__LSL_c1___PgZ___Zt_S__V2,
+		},
+		// ZLDFF1H [<Xn|SP>, <Zm>.D, LSL #1], <Pg>/Z, { <Zt>.D }
+		{
+			goOp:      AZLDFF1H,
+			fixedBits: 0xc4e0e000,
+			args:      XnSP__Zm_D__LSL_c1___PgZ___Zt_D_,
+		},
+		// ZLDFF1H [<Xn|SP>, <Zm>.D], <Pg>/Z, { <Zt>.D }
+		{
+			goOp:      AZLDFF1H,
+			fixedBits: 0xc4c0e000,
+			args:      XnSP__Zm_D___PgZ___Zt_D_,
+		},
+		// ZLDFF1H [<Xn|SP>, <Zm>.D, <mod>], <Pg>/Z, { <Zt>.D }
+		{
+			goOp:      AZLDFF1H,
+			fixedBits: 0xc4806000,
+			args:      XnSP__Zm_D__mod___PgZ___Zt_D_,
+		},
+		// ZLDFF1H [<Xn|SP>, <Zm>.D, <mod> #1], <Pg>/Z, { <Zt>.D }
+		{
+			goOp:      AZLDFF1H,
+			fixedBits: 0xc4a06000,
+			args:      XnSP__Zm_D__mod_c1___PgZ___Zt_D_,
+		},
+		// ZLDFF1H [<Xn|SP>, <Zm>.S, <mod>], <Pg>/Z, { <Zt>.S }
+		{
+			goOp:      AZLDFF1H,
+			fixedBits: 0x84806000,
+			args:      XnSP__Zm_S__mod___PgZ___Zt_S_,
+		},
+		// ZLDFF1H [<Xn|SP>, <Zm>.S, <mod> #1], <Pg>/Z, { <Zt>.S }
+		{
+			goOp:      AZLDFF1H,
+			fixedBits: 0x84a06000,
+			args:      XnSP__Zm_S__mod_c1___PgZ___Zt_S_,
+		},
+	},
+	// ZLDFF1SB
+	{
+		// ZLDFF1SB [<Xn|SP>{, <Xm>}], <Pg>/Z, { <Zt>.D }
+		{
+			goOp:      AZLDFF1SB,
+			fixedBits: 0xa5806000,
+			args:      XnSP__Xm___PgZ___Zt_D__V2,
+		},
+		// ZLDFF1SB [<Xn|SP>{, <Xm>}], <Pg>/Z, { <Zt>.H }
+		{
+			goOp:      AZLDFF1SB,
+			fixedBits: 0xa5c06000,
+			args:      XnSP__Xm___PgZ___Zt_H__V2,
+		},
+		// ZLDFF1SB [<Xn|SP>{, <Xm>}], <Pg>/Z, { <Zt>.S }
+		{
+			goOp:      AZLDFF1SB,
+			fixedBits: 0xa5a06000,
+			args:      XnSP__Xm___PgZ___Zt_S__V2,
+		},
+		// ZLDFF1SB [<Xn|SP>, <Zm>.D], <Pg>/Z, { <Zt>.D }
+		{
+			goOp:      AZLDFF1SB,
+			fixedBits: 0xc440a000,
+			args:      XnSP__Zm_D___PgZ___Zt_D_,
+		},
+		// ZLDFF1SB [<Xn|SP>, <Zm>.D, <mod>], <Pg>/Z, { <Zt>.D }
+		{
+			goOp:      AZLDFF1SB,
+			fixedBits: 0xc4002000,
+			args:      XnSP__Zm_D__mod___PgZ___Zt_D_,
+		},
+		// ZLDFF1SB [<Xn|SP>, <Zm>.S, <mod>], <Pg>/Z, { <Zt>.S }
+		{
+			goOp:      AZLDFF1SB,
+			fixedBits: 0x84002000,
+			args:      XnSP__Zm_S__mod___PgZ___Zt_S_,
+		},
+	},
+	// ZLDFF1SH
+	{
+		// ZLDFF1SH [<Xn|SP>{, <Xm>, LSL #1}], <Pg>/Z, { <Zt>.D }
+		{
+			goOp:      AZLDFF1SH,
+			fixedBits: 0xa5006000,
+			args:      XnSP__Xm__LSL_c1___PgZ___Zt_D__V2,
+		},
+		// ZLDFF1SH [<Xn|SP>{, <Xm>, LSL #1}], <Pg>/Z, { <Zt>.S }
+		{
+			goOp:      AZLDFF1SH,
+			fixedBits: 0xa5206000,
+			args:      XnSP__Xm__LSL_c1___PgZ___Zt_S__V2,
+		},
+		// ZLDFF1SH [<Xn|SP>, <Zm>.D, LSL #1], <Pg>/Z, { <Zt>.D }
+		{
+			goOp:      AZLDFF1SH,
+			fixedBits: 0xc4e0a000,
+			args:      XnSP__Zm_D__LSL_c1___PgZ___Zt_D_,
+		},
+		// ZLDFF1SH [<Xn|SP>, <Zm>.D], <Pg>/Z, { <Zt>.D }
+		{
+			goOp:      AZLDFF1SH,
+			fixedBits: 0xc4c0a000,
+			args:      XnSP__Zm_D___PgZ___Zt_D_,
+		},
+		// ZLDFF1SH [<Xn|SP>, <Zm>.D, <mod>], <Pg>/Z, { <Zt>.D }
+		{
+			goOp:      AZLDFF1SH,
+			fixedBits: 0xc4802000,
+			args:      XnSP__Zm_D__mod___PgZ___Zt_D_,
+		},
+		// ZLDFF1SH [<Xn|SP>, <Zm>.D, <mod> #1], <Pg>/Z, { <Zt>.D }
+		{
+			goOp:      AZLDFF1SH,
+			fixedBits: 0xc4a02000,
+			args:      XnSP__Zm_D__mod_c1___PgZ___Zt_D_,
+		},
+		// ZLDFF1SH [<Xn|SP>, <Zm>.S, <mod>], <Pg>/Z, { <Zt>.S }
+		{
+			goOp:      AZLDFF1SH,
+			fixedBits: 0x84802000,
+			args:      XnSP__Zm_S__mod___PgZ___Zt_S_,
+		},
+		// ZLDFF1SH [<Xn|SP>, <Zm>.S, <mod> #1], <Pg>/Z, { <Zt>.S }
+		{
+			goOp:      AZLDFF1SH,
+			fixedBits: 0x84a02000,
+			args:      XnSP__Zm_S__mod_c1___PgZ___Zt_S_,
+		},
+	},
+	// ZLDFF1SW
+	{
+		// ZLDFF1SW [<Xn|SP>{, <Xm>, LSL #2}], <Pg>/Z, { <Zt>.D }
+		{
+			goOp:      AZLDFF1SW,
+			fixedBits: 0xa4806000,
+			args:      XnSP__Xm__LSL_c2___PgZ___Zt_D__V2,
+		},
+		// ZLDFF1SW [<Xn|SP>, <Zm>.D, LSL #2], <Pg>/Z, { <Zt>.D }
+		{
+			goOp:      AZLDFF1SW,
+			fixedBits: 0xc560a000,
+			args:      XnSP__Zm_D__LSL_c2___PgZ___Zt_D_,
+		},
+		// ZLDFF1SW [<Xn|SP>, <Zm>.D], <Pg>/Z, { <Zt>.D }
+		{
+			goOp:      AZLDFF1SW,
+			fixedBits: 0xc540a000,
+			args:      XnSP__Zm_D___PgZ___Zt_D_,
+		},
+		// ZLDFF1SW [<Xn|SP>, <Zm>.D, <mod>], <Pg>/Z, { <Zt>.D }
+		{
+			goOp:      AZLDFF1SW,
+			fixedBits: 0xc5002000,
+			args:      XnSP__Zm_D__mod___PgZ___Zt_D_,
+		},
+		// ZLDFF1SW [<Xn|SP>, <Zm>.D, <mod> #2], <Pg>/Z, { <Zt>.D }
+		{
+			goOp:      AZLDFF1SW,
+			fixedBits: 0xc5202000,
+			args:      XnSP__Zm_D__mod_c2___PgZ___Zt_D_,
+		},
+	},
+	// ZLDFF1W
+	{
+		// ZLDFF1W [<Xn|SP>{, <Xm>, LSL #2}], <Pg>/Z, { <Zt>.D }
+		{
+			goOp:      AZLDFF1W,
+			fixedBits: 0xa5606000,
+			args:      XnSP__Xm__LSL_c2___PgZ___Zt_D__V2,
+		},
+		// ZLDFF1W [<Xn|SP>{, <Xm>, LSL #2}], <Pg>/Z, { <Zt>.S }
+		{
+			goOp:      AZLDFF1W,
+			fixedBits: 0xa5406000,
+			args:      XnSP__Xm__LSL_c2___PgZ___Zt_S__V2,
+		},
+		// ZLDFF1W [<Xn|SP>, <Zm>.D, LSL #2], <Pg>/Z, { <Zt>.D }
+		{
+			goOp:      AZLDFF1W,
+			fixedBits: 0xc560e000,
+			args:      XnSP__Zm_D__LSL_c2___PgZ___Zt_D_,
+		},
+		// ZLDFF1W [<Xn|SP>, <Zm>.D], <Pg>/Z, { <Zt>.D }
+		{
+			goOp:      AZLDFF1W,
+			fixedBits: 0xc540e000,
+			args:      XnSP__Zm_D___PgZ___Zt_D_,
+		},
+		// ZLDFF1W [<Xn|SP>, <Zm>.D, <mod>], <Pg>/Z, { <Zt>.D }
+		{
+			goOp:      AZLDFF1W,
+			fixedBits: 0xc5006000,
+			args:      XnSP__Zm_D__mod___PgZ___Zt_D_,
+		},
+		// ZLDFF1W [<Xn|SP>, <Zm>.D, <mod> #2], <Pg>/Z, { <Zt>.D }
+		{
+			goOp:      AZLDFF1W,
+			fixedBits: 0xc5206000,
+			args:      XnSP__Zm_D__mod_c2___PgZ___Zt_D_,
+		},
+		// ZLDFF1W [<Xn|SP>, <Zm>.S, <mod>], <Pg>/Z, { <Zt>.S }
+		{
+			goOp:      AZLDFF1W,
+			fixedBits: 0x85006000,
+			args:      XnSP__Zm_S__mod___PgZ___Zt_S_,
+		},
+		// ZLDFF1W [<Xn|SP>, <Zm>.S, <mod> #2], <Pg>/Z, { <Zt>.S }
+		{
+			goOp:      AZLDFF1W,
+			fixedBits: 0x85206000,
+			args:      XnSP__Zm_S__mod_c2___PgZ___Zt_S_,
+		},
+	},
+	// ZLDNT1B
+	{
+		// ZLDNT1B [<Xn|SP>, <Xm>], <Pg>/Z, { <Zt>.B }
+		{
+			goOp:      AZLDNT1B,
+			fixedBits: 0xa400c000,
+			args:      XnSP__Xm___PgZ___Zt_B_,
+		},
+		// ZLDNT1B [<Zn>.D{, <Xm>}], <Pg>/Z, { <Zt>.D }
+		{
+			goOp:      AZLDNT1B,
+			fixedBits: 0xc400c000,
+			args:      Zn_D__Xm___PgZ___Zt_D_,
+		},
+		// ZLDNT1B [<Zn>.S{, <Xm>}], <Pg>/Z, { <Zt>.S }
+		{
+			goOp:      AZLDNT1B,
+			fixedBits: 0x8400a000,
+			args:      Zn_S__Xm___PgZ___Zt_S_,
+		},
+	},
+	// ZLDNT1D
+	{
+		// ZLDNT1D [<Xn|SP>, <Xm>, LSL #3], <Pg>/Z, { <Zt>.D }
+		{
+			goOp:      AZLDNT1D,
+			fixedBits: 0xa580c000,
+			args:      XnSP__Xm__LSL_c3___PgZ___Zt_D_,
+		},
+		// ZLDNT1D [<Zn>.D{, <Xm>}], <Pg>/Z, { <Zt>.D }
+		{
+			goOp:      AZLDNT1D,
+			fixedBits: 0xc580c000,
+			args:      Zn_D__Xm___PgZ___Zt_D_,
+		},
+	},
+	// ZLDNT1H
+	{
+		// ZLDNT1H [<Xn|SP>, <Xm>, LSL #1], <Pg>/Z, { <Zt>.H }
+		{
+			goOp:      AZLDNT1H,
+			fixedBits: 0xa480c000,
+			args:      XnSP__Xm__LSL_c1___PgZ___Zt_H_,
+		},
+		// ZLDNT1H [<Zn>.D{, <Xm>}], <Pg>/Z, { <Zt>.D }
+		{
+			goOp:      AZLDNT1H,
+			fixedBits: 0xc480c000,
+			args:      Zn_D__Xm___PgZ___Zt_D_,
+		},
+		// ZLDNT1H [<Zn>.S{, <Xm>}], <Pg>/Z, { <Zt>.S }
+		{
+			goOp:      AZLDNT1H,
+			fixedBits: 0x8480a000,
+			args:      Zn_S__Xm___PgZ___Zt_S_,
+		},
+	},
+	// ZLDNT1SB
+	{
+		// ZLDNT1SB [<Zn>.D{, <Xm>}], <Pg>/Z, { <Zt>.D }
+		{
+			goOp:      AZLDNT1SB,
+			fixedBits: 0xc4008000,
+			args:      Zn_D__Xm___PgZ___Zt_D_,
+		},
+		// ZLDNT1SB [<Zn>.S{, <Xm>}], <Pg>/Z, { <Zt>.S }
+		{
+			goOp:      AZLDNT1SB,
+			fixedBits: 0x84008000,
+			args:      Zn_S__Xm___PgZ___Zt_S_,
+		},
+	},
+	// ZLDNT1SH
+	{
+		// ZLDNT1SH [<Zn>.D{, <Xm>}], <Pg>/Z, { <Zt>.D }
+		{
+			goOp:      AZLDNT1SH,
+			fixedBits: 0xc4808000,
+			args:      Zn_D__Xm___PgZ___Zt_D_,
+		},
+		// ZLDNT1SH [<Zn>.S{, <Xm>}], <Pg>/Z, { <Zt>.S }
+		{
+			goOp:      AZLDNT1SH,
+			fixedBits: 0x84808000,
+			args:      Zn_S__Xm___PgZ___Zt_S_,
+		},
+	},
+	// ZLDNT1SW
+	{
+		// ZLDNT1SW [<Zn>.D{, <Xm>}], <Pg>/Z, { <Zt>.D }
+		{
+			goOp:      AZLDNT1SW,
+			fixedBits: 0xc5008000,
+			args:      Zn_D__Xm___PgZ___Zt_D_,
+		},
+	},
+	// ZLDNT1W
+	{
+		// ZLDNT1W [<Xn|SP>, <Xm>, LSL #2], <Pg>/Z, { <Zt>.S }
+		{
+			goOp:      AZLDNT1W,
+			fixedBits: 0xa500c000,
+			args:      XnSP__Xm__LSL_c2___PgZ___Zt_S_,
+		},
+		// ZLDNT1W [<Zn>.D{, <Xm>}], <Pg>/Z, { <Zt>.D }
+		{
+			goOp:      AZLDNT1W,
+			fixedBits: 0xc500c000,
+			args:      Zn_D__Xm___PgZ___Zt_D_,
+		},
+		// ZLDNT1W [<Zn>.S{, <Xm>}], <Pg>/Z, { <Zt>.S }
+		{
+			goOp:      AZLDNT1W,
+			fixedBits: 0x8500a000,
+			args:      Zn_S__Xm___PgZ___Zt_S_,
+		},
+	},
 	// ZLSL
 	{
 		// ZLSL <Zm>.D, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
@@ -5349,7 +6303,7 @@ var insts = [][]instEncoder{
 		{
 			goOp:      AZSPLICE,
 			fixedBits: 0x52d8000,
-			args:      _Zn1_T__Zn2_T___Pv__Zd_T,
+			args:      Zn1_T__Zn2_T___Pv__Zd_T,
 		},
 	},
 	// ZSQABS
@@ -6027,6 +6981,366 @@ var insts = [][]instEncoder{
 			args:      Zm_Tb__Zn_T__Zd_T,
 		},
 	},
+	// ZST1B
+	{
+		// ZST1B [<Xn|SP>, <Xm>], <Pg>, { <Zt>.<T> }
+		{
+			goOp:      AZST1B,
+			fixedBits: 0xe4004000,
+			args:      XnSP__Xm___Pg___Zt_T_,
+		},
+		// ZST1B [<Xn|SP>, <Zm>.D], <Pg>, { <Zt>.D }
+		{
+			goOp:      AZST1B,
+			fixedBits: 0xe400a000,
+			args:      XnSP__Zm_D___Pg___Zt_D_,
+		},
+		// ZST1B [<Xn|SP>, <Zm>.D, <mod>], <Pg>, { <Zt>.D }
+		{
+			goOp:      AZST1B,
+			fixedBits: 0xe4008000,
+			args:      XnSP__Zm_D__mod___Pg___Zt_D_,
+		},
+		// ZST1B [<Xn|SP>, <Zm>.S, <mod>], <Pg>, { <Zt>.S }
+		{
+			goOp:      AZST1B,
+			fixedBits: 0xe4408000,
+			args:      XnSP__Zm_S__mod___Pg___Zt_S_,
+		},
+	},
+	// ZST1D
+	{
+		// ZST1D [<Xn|SP>, <Zm>.D, LSL #3], <Pg>, { <Zt>.D }
+		{
+			goOp:      AZST1D,
+			fixedBits: 0xe5a0a000,
+			args:      XnSP__Zm_D__LSL_c3___Pg___Zt_D_,
+		},
+		// ZST1D [<Xn|SP>, <Zm>.D], <Pg>, { <Zt>.D }
+		{
+			goOp:      AZST1D,
+			fixedBits: 0xe580a000,
+			args:      XnSP__Zm_D___Pg___Zt_D_,
+		},
+		// ZST1D [<Xn|SP>, <Zm>.D, <mod>], <Pg>, { <Zt>.D }
+		{
+			goOp:      AZST1D,
+			fixedBits: 0xe5808000,
+			args:      XnSP__Zm_D__mod___Pg___Zt_D_,
+		},
+		// ZST1D [<Xn|SP>, <Zm>.D, <mod> #3], <Pg>, { <Zt>.D }
+		{
+			goOp:      AZST1D,
+			fixedBits: 0xe5a08000,
+			args:      XnSP__Zm_D__mod_c3___Pg___Zt_D_,
+		},
+	},
+	// ZST1H
+	{
+		// ZST1H [<Xn|SP>, <Xm>, LSL #1], <Pg>, { <Zt>.<T> }
+		{
+			goOp:      AZST1H,
+			fixedBits: 0xe4804000,
+			args:      XnSP__Xm__LSL_c1___Pg___Zt_T_,
+		},
+		// ZST1H [<Xn|SP>, <Zm>.D, LSL #1], <Pg>, { <Zt>.D }
+		{
+			goOp:      AZST1H,
+			fixedBits: 0xe4a0a000,
+			args:      XnSP__Zm_D__LSL_c1___Pg___Zt_D_,
+		},
+		// ZST1H [<Xn|SP>, <Zm>.D], <Pg>, { <Zt>.D }
+		{
+			goOp:      AZST1H,
+			fixedBits: 0xe480a000,
+			args:      XnSP__Zm_D___Pg___Zt_D_,
+		},
+		// ZST1H [<Xn|SP>, <Zm>.D, <mod>], <Pg>, { <Zt>.D }
+		{
+			goOp:      AZST1H,
+			fixedBits: 0xe4808000,
+			args:      XnSP__Zm_D__mod___Pg___Zt_D_,
+		},
+		// ZST1H [<Xn|SP>, <Zm>.D, <mod> #1], <Pg>, { <Zt>.D }
+		{
+			goOp:      AZST1H,
+			fixedBits: 0xe4a08000,
+			args:      XnSP__Zm_D__mod_c1___Pg___Zt_D_,
+		},
+		// ZST1H [<Xn|SP>, <Zm>.S, <mod>], <Pg>, { <Zt>.S }
+		{
+			goOp:      AZST1H,
+			fixedBits: 0xe4c08000,
+			args:      XnSP__Zm_S__mod___Pg___Zt_S_,
+		},
+		// ZST1H [<Xn|SP>, <Zm>.S, <mod> #1], <Pg>, { <Zt>.S }
+		{
+			goOp:      AZST1H,
+			fixedBits: 0xe4e08000,
+			args:      XnSP__Zm_S__mod_c1___Pg___Zt_S_,
+		},
+	},
+	// ZST1Q
+	{
+		// ZST1Q [<Zn>.D{, <Xm>}], <Pg>, { <Zt>.Q }
+		{
+			goOp:      AZST1Q,
+			fixedBits: 0xe4202000,
+			args:      Zn_D__Xm___Pg___Zt_Q_,
+		},
+	},
+	// ZST1W
+	{
+		// ZST1W [<Xn|SP>, <Zm>.D, LSL #2], <Pg>, { <Zt>.D }
+		{
+			goOp:      AZST1W,
+			fixedBits: 0xe520a000,
+			args:      XnSP__Zm_D__LSL_c2___Pg___Zt_D_,
+		},
+		// ZST1W [<Xn|SP>, <Zm>.D], <Pg>, { <Zt>.D }
+		{
+			goOp:      AZST1W,
+			fixedBits: 0xe500a000,
+			args:      XnSP__Zm_D___Pg___Zt_D_,
+		},
+		// ZST1W [<Xn|SP>, <Zm>.D, <mod>], <Pg>, { <Zt>.D }
+		{
+			goOp:      AZST1W,
+			fixedBits: 0xe5008000,
+			args:      XnSP__Zm_D__mod___Pg___Zt_D_,
+		},
+		// ZST1W [<Xn|SP>, <Zm>.D, <mod> #2], <Pg>, { <Zt>.D }
+		{
+			goOp:      AZST1W,
+			fixedBits: 0xe5208000,
+			args:      XnSP__Zm_D__mod_c2___Pg___Zt_D_,
+		},
+		// ZST1W [<Xn|SP>, <Zm>.S, <mod>], <Pg>, { <Zt>.S }
+		{
+			goOp:      AZST1W,
+			fixedBits: 0xe5408000,
+			args:      XnSP__Zm_S__mod___Pg___Zt_S_,
+		},
+		// ZST1W [<Xn|SP>, <Zm>.S, <mod> #2], <Pg>, { <Zt>.S }
+		{
+			goOp:      AZST1W,
+			fixedBits: 0xe5608000,
+			args:      XnSP__Zm_S__mod_c2___Pg___Zt_S_,
+		},
+	},
+	// ZST2B
+	{
+		// ZST2B [<Xn|SP>, <Xm>], <Pg>, { <Zt1>.B, <Zt2>.B }
+		{
+			goOp:      AZST2B,
+			fixedBits: 0xe4206000,
+			args:      XnSP__Xm___Pg___Zt1_B__Zt2_B_,
+		},
+	},
+	// ZST2D
+	{
+		// ZST2D [<Xn|SP>, <Xm>, LSL #3], <Pg>, { <Zt1>.D, <Zt2>.D }
+		{
+			goOp:      AZST2D,
+			fixedBits: 0xe5a06000,
+			args:      XnSP__Xm__LSL_c3___Pg___Zt1_D__Zt2_D_,
+		},
+	},
+	// ZST2H
+	{
+		// ZST2H [<Xn|SP>, <Xm>, LSL #1], <Pg>, { <Zt1>.H, <Zt2>.H }
+		{
+			goOp:      AZST2H,
+			fixedBits: 0xe4a06000,
+			args:      XnSP__Xm__LSL_c1___Pg___Zt1_H__Zt2_H_,
+		},
+	},
+	// ZST2Q
+	{
+		// ZST2Q [<Xn|SP>, <Xm>, LSL #4], <Pg>, { <Zt1>.Q, <Zt2>.Q }
+		{
+			goOp:      AZST2Q,
+			fixedBits: 0xe4600000,
+			args:      XnSP__Xm__LSL_c4___Pg___Zt1_Q__Zt2_Q_,
+		},
+	},
+	// ZST2W
+	{
+		// ZST2W [<Xn|SP>, <Xm>, LSL #2], <Pg>, { <Zt1>.S, <Zt2>.S }
+		{
+			goOp:      AZST2W,
+			fixedBits: 0xe5206000,
+			args:      XnSP__Xm__LSL_c2___Pg___Zt1_S__Zt2_S_,
+		},
+	},
+	// ZST3B
+	{
+		// ZST3B [<Xn|SP>, <Xm>], <Pg>, { <Zt1>.B, <Zt2>.B, <Zt3>.B }
+		{
+			goOp:      AZST3B,
+			fixedBits: 0xe4406000,
+			args:      XnSP__Xm___Pg___Zt1_B__Zt2_B__Zt3_B_,
+		},
+	},
+	// ZST3D
+	{
+		// ZST3D [<Xn|SP>, <Xm>, LSL #3], <Pg>, { <Zt1>.D, <Zt2>.D, <Zt3>.D }
+		{
+			goOp:      AZST3D,
+			fixedBits: 0xe5c06000,
+			args:      XnSP__Xm__LSL_c3___Pg___Zt1_D__Zt2_D__Zt3_D_,
+		},
+	},
+	// ZST3H
+	{
+		// ZST3H [<Xn|SP>, <Xm>, LSL #1], <Pg>, { <Zt1>.H, <Zt2>.H, <Zt3>.H }
+		{
+			goOp:      AZST3H,
+			fixedBits: 0xe4c06000,
+			args:      XnSP__Xm__LSL_c1___Pg___Zt1_H__Zt2_H__Zt3_H_,
+		},
+	},
+	// ZST3Q
+	{
+		// ZST3Q [<Xn|SP>, <Xm>, LSL #4], <Pg>, { <Zt1>.Q, <Zt2>.Q, <Zt3>.Q }
+		{
+			goOp:      AZST3Q,
+			fixedBits: 0xe4a00000,
+			args:      XnSP__Xm__LSL_c4___Pg___Zt1_Q__Zt2_Q__Zt3_Q_,
+		},
+	},
+	// ZST3W
+	{
+		// ZST3W [<Xn|SP>, <Xm>, LSL #2], <Pg>, { <Zt1>.S, <Zt2>.S, <Zt3>.S }
+		{
+			goOp:      AZST3W,
+			fixedBits: 0xe5406000,
+			args:      XnSP__Xm__LSL_c2___Pg___Zt1_S__Zt2_S__Zt3_S_,
+		},
+	},
+	// ZST4B
+	{
+		// ZST4B [<Xn|SP>, <Xm>], <Pg>, { <Zt1>.B, <Zt2>.B, <Zt3>.B, <Zt4>.B }
+		{
+			goOp:      AZST4B,
+			fixedBits: 0xe4606000,
+			args:      XnSP__Xm___Pg___Zt1_B__Zt2_B__Zt3_B__Zt4_B_,
+		},
+	},
+	// ZST4D
+	{
+		// ZST4D [<Xn|SP>, <Xm>, LSL #3], <Pg>, { <Zt1>.D, <Zt2>.D, <Zt3>.D, <Zt4>.D }
+		{
+			goOp:      AZST4D,
+			fixedBits: 0xe5e06000,
+			args:      XnSP__Xm__LSL_c3___Pg___Zt1_D__Zt2_D__Zt3_D__Zt4_D_,
+		},
+	},
+	// ZST4H
+	{
+		// ZST4H [<Xn|SP>, <Xm>, LSL #1], <Pg>, { <Zt1>.H, <Zt2>.H, <Zt3>.H, <Zt4>.H }
+		{
+			goOp:      AZST4H,
+			fixedBits: 0xe4e06000,
+			args:      XnSP__Xm__LSL_c1___Pg___Zt1_H__Zt2_H__Zt3_H__Zt4_H_,
+		},
+	},
+	// ZST4Q
+	{
+		// ZST4Q [<Xn|SP>, <Xm>, LSL #4], <Pg>, { <Zt1>.Q, <Zt2>.Q, <Zt3>.Q, <Zt4>.Q }
+		{
+			goOp:      AZST4Q,
+			fixedBits: 0xe4e00000,
+			args:      XnSP__Xm__LSL_c4___Pg___Zt1_Q__Zt2_Q__Zt3_Q__Zt4_Q_,
+		},
+	},
+	// ZST4W
+	{
+		// ZST4W [<Xn|SP>, <Xm>, LSL #2], <Pg>, { <Zt1>.S, <Zt2>.S, <Zt3>.S, <Zt4>.S }
+		{
+			goOp:      AZST4W,
+			fixedBits: 0xe5606000,
+			args:      XnSP__Xm__LSL_c2___Pg___Zt1_S__Zt2_S__Zt3_S__Zt4_S_,
+		},
+	},
+	// ZSTNT1B
+	{
+		// ZSTNT1B [<Xn|SP>, <Xm>], <Pg>, { <Zt>.B }
+		{
+			goOp:      AZSTNT1B,
+			fixedBits: 0xe4006000,
+			args:      XnSP__Xm___Pg___Zt_B_,
+		},
+		// ZSTNT1B [<Zn>.D{, <Xm>}], <Pg>, { <Zt>.D }
+		{
+			goOp:      AZSTNT1B,
+			fixedBits: 0xe4002000,
+			args:      Zn_D__Xm___Pg___Zt_D_,
+		},
+		// ZSTNT1B [<Zn>.S{, <Xm>}], <Pg>, { <Zt>.S }
+		{
+			goOp:      AZSTNT1B,
+			fixedBits: 0xe4402000,
+			args:      Zn_S__Xm___Pg___Zt_S_,
+		},
+	},
+	// ZSTNT1D
+	{
+		// ZSTNT1D [<Xn|SP>, <Xm>, LSL #3], <Pg>, { <Zt>.D }
+		{
+			goOp:      AZSTNT1D,
+			fixedBits: 0xe5806000,
+			args:      XnSP__Xm__LSL_c3___Pg___Zt_D_,
+		},
+		// ZSTNT1D [<Zn>.D{, <Xm>}], <Pg>, { <Zt>.D }
+		{
+			goOp:      AZSTNT1D,
+			fixedBits: 0xe5802000,
+			args:      Zn_D__Xm___Pg___Zt_D_,
+		},
+	},
+	// ZSTNT1H
+	{
+		// ZSTNT1H [<Xn|SP>, <Xm>, LSL #1], <Pg>, { <Zt>.H }
+		{
+			goOp:      AZSTNT1H,
+			fixedBits: 0xe4806000,
+			args:      XnSP__Xm__LSL_c1___Pg___Zt_H_,
+		},
+		// ZSTNT1H [<Zn>.D{, <Xm>}], <Pg>, { <Zt>.D }
+		{
+			goOp:      AZSTNT1H,
+			fixedBits: 0xe4802000,
+			args:      Zn_D__Xm___Pg___Zt_D_,
+		},
+		// ZSTNT1H [<Zn>.S{, <Xm>}], <Pg>, { <Zt>.S }
+		{
+			goOp:      AZSTNT1H,
+			fixedBits: 0xe4c02000,
+			args:      Zn_S__Xm___Pg___Zt_S_,
+		},
+	},
+	// ZSTNT1W
+	{
+		// ZSTNT1W [<Xn|SP>, <Xm>, LSL #2], <Pg>, { <Zt>.S }
+		{
+			goOp:      AZSTNT1W,
+			fixedBits: 0xe5006000,
+			args:      XnSP__Xm__LSL_c2___Pg___Zt_S_,
+		},
+		// ZSTNT1W [<Zn>.D{, <Xm>}], <Pg>, { <Zt>.D }
+		{
+			goOp:      AZSTNT1W,
+			fixedBits: 0xe5002000,
+			args:      Zn_D__Xm___Pg___Zt_D_,
+		},
+		// ZSTNT1W [<Zn>.S{, <Xm>}], <Pg>, { <Zt>.S }
+		{
+			goOp:      AZSTNT1W,
+			fixedBits: 0xe5402000,
+			args:      Zn_S__Xm___Pg___Zt_S_,
+		},
+	},
 	// ZSUB
 	{
 		// ZSUB <Zm>.<T>, <Zdn>.<T>, <Pg>/M, <Zdn>.<T>
@@ -7904,6 +9218,13 @@ var a_ARNG_Zd_SzSD1718 = operand{
 	},
 }
 
+var a_ARNG_Zd_SzSD2223 = operand{
+	class: AC_ARNG, elemEncoders: []elemEncoder{
+		{encodeZd, enc_Zd},
+		{encodeSzSD2223, enc_sz},
+	},
+}
+
 var a_ARNG_Zd_SzWordDoubleword = operand{
 	class: AC_ARNG, elemEncoders: []elemEncoder{
 		{encodeZd, enc_Zd},
@@ -8457,121 +9778,121 @@ var a_ARNG_Zn510Src_TszhTszlTbHSD = operand{
 	},
 }
 
-var a_ARNG_Zn510_ArngBCheck = operand{
+var a_ARNG_Zn510V1_ArngBCheck = operand{
 	class: AC_ARNG, elemEncoders: []elemEncoder{
-		{encodeZn510, enc_Zn},
+		{encodeZn510V1, enc_Zn},
 		{encodeArngBCheck, enc_NIL},
 	},
 }
 
-var a_ARNG_Zn510_ArngDCheck = operand{
+var a_ARNG_Zn510V1_ArngDCheck = operand{
 	class: AC_ARNG, elemEncoders: []elemEncoder{
-		{encodeZn510, enc_Zn},
+		{encodeZn510V1, enc_Zn},
 		{encodeArngDCheck, enc_NIL},
 	},
 }
 
-var a_ARNG_Zn510_ArngHCheck = operand{
+var a_ARNG_Zn510V1_ArngHCheck = operand{
 	class: AC_ARNG, elemEncoders: []elemEncoder{
-		{encodeZn510, enc_Zn},
+		{encodeZn510V1, enc_Zn},
 		{encodeArngHCheck, enc_NIL},
 	},
 }
 
-var a_ARNG_Zn510_ArngQCheck = operand{
+var a_ARNG_Zn510V1_ArngQCheck = operand{
 	class: AC_ARNG, elemEncoders: []elemEncoder{
-		{encodeZn510, enc_Zn},
+		{encodeZn510V1, enc_Zn},
 		{encodeArngQCheck, enc_NIL},
 	},
 }
 
-var a_ARNG_Zn510_ArngSCheck = operand{
+var a_ARNG_Zn510V1_ArngSCheck = operand{
 	class: AC_ARNG, elemEncoders: []elemEncoder{
-		{encodeZn510, enc_Zn},
+		{encodeZn510V1, enc_Zn},
 		{encodeArngSCheck, enc_NIL},
 	},
 }
 
-var a_ARNG_Zn510_Size0BH2223 = operand{
+var a_ARNG_Zn510V1_Size0BH2223 = operand{
 	class: AC_ARNG, elemEncoders: []elemEncoder{
-		{encodeZn510, enc_Zn},
+		{encodeZn510V1, enc_Zn},
 		{encodeSize0BH2223, enc_size0},
 	},
 }
 
-var a_ARNG_Zn510_Size0SD2223 = operand{
+var a_ARNG_Zn510V1_Size0SD2223 = operand{
 	class: AC_ARNG, elemEncoders: []elemEncoder{
-		{encodeZn510, enc_Zn},
+		{encodeZn510V1, enc_Zn},
 		{encodeSize0SD2223, enc_size0},
 	},
 }
 
-var a_ARNG_Zn510_Size0TbBH2223 = operand{
+var a_ARNG_Zn510V1_Size0TbBH2223 = operand{
 	class: AC_ARNG, elemEncoders: []elemEncoder{
-		{encodeZn510, enc_Zn},
+		{encodeZn510V1, enc_Zn},
 		{encodeSize0TbBH2223, enc_size0},
 	},
 }
 
-var a_ARNG_Zn510_SizeBHS2224 = operand{
+var a_ARNG_Zn510V1_SizeBHS2224 = operand{
 	class: AC_ARNG, elemEncoders: []elemEncoder{
-		{encodeZn510, enc_Zn},
+		{encodeZn510V1, enc_Zn},
 		{encodeSizeBHS2224, enc_size},
 	},
 }
 
-var a_ARNG_Zn510_SizeBHSD2224 = operand{
+var a_ARNG_Zn510V1_SizeBHSD2224 = operand{
 	class: AC_ARNG, elemEncoders: []elemEncoder{
-		{encodeZn510, enc_Zn},
+		{encodeZn510V1, enc_Zn},
 		{encodeSizeBHSD2224, enc_size},
 	},
 }
 
-var a_ARNG_Zn510_SizeBhsdTsz1921 = operand{
+var a_ARNG_Zn510V1_SizeBhsdTsz1921 = operand{
 	class: AC_ARNG, elemEncoders: []elemEncoder{
-		{encodeZn510, enc_Zn},
+		{encodeZn510V1, enc_Zn},
 		{encodeSizeBhsdTsz1921, enc_tszh_tszl},
 	},
 }
 
-var a_ARNG_Zn510_SizeHSD2224 = operand{
+var a_ARNG_Zn510V1_SizeHSD2224 = operand{
 	class: AC_ARNG, elemEncoders: []elemEncoder{
-		{encodeZn510, enc_Zn},
+		{encodeZn510V1, enc_Zn},
 		{encodeSizeHSD2224, enc_size},
 	},
 }
 
-var a_ARNG_Zn510_SizeHSD2224No00 = operand{
+var a_ARNG_Zn510V1_SizeHSD2224No00 = operand{
 	class: AC_ARNG, elemEncoders: []elemEncoder{
-		{encodeZn510, enc_Zn},
+		{encodeZn510V1, enc_Zn},
 		{encodeSizeHSD2224No00, enc_size},
 	},
 }
 
-var a_ARNG_Zn510_SizeTbBHS2224 = operand{
+var a_ARNG_Zn510V1_SizeTbBHS2224 = operand{
 	class: AC_ARNG, elemEncoders: []elemEncoder{
-		{encodeZn510, enc_Zn},
+		{encodeZn510V1, enc_Zn},
 		{encodeSizeTbBHS2224, enc_size},
 	},
 }
 
-var a_ARNG_Zn510_SizeTbBS2224 = operand{
+var a_ARNG_Zn510V1_SizeTbBS2224 = operand{
 	class: AC_ARNG, elemEncoders: []elemEncoder{
-		{encodeZn510, enc_Zn},
+		{encodeZn510V1, enc_Zn},
 		{encodeSizeTbBS2224, enc_size},
 	},
 }
 
-var a_ARNG_Zn510_SizeTbHSD2224Offset1 = operand{
+var a_ARNG_Zn510V1_SizeTbHSD2224Offset1 = operand{
 	class: AC_ARNG, elemEncoders: []elemEncoder{
-		{encodeZn510, enc_Zn},
+		{encodeZn510V1, enc_Zn},
 		{encodeSizeTbHSD2224Offset1, enc_size},
 	},
 }
 
-var a_ARNG_Zn510_SzSD2223 = operand{
+var a_ARNG_Zn510V1_SzSD2223 = operand{
 	class: AC_ARNG, elemEncoders: []elemEncoder{
-		{encodeZn510, enc_Zn},
+		{encodeZn510V1, enc_Zn},
 		{encodeSzSD2223, enc_sz},
 	},
 }
@@ -8756,6 +10077,358 @@ var a_IMM_ShiftTsz58Range1 = operand{
 	},
 }
 
+var a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt1Check = operand{
+	class: AC_MEMEXT, elemEncoders: []elemEncoder{
+		{encodeRn510SPV2, enc_Rn},
+		{encodeNoop, enc_NIL},
+		{encodeRm1621V2, enc_Rm},
+		{encodeNoop, enc_NIL},
+		{encodeModLSLCheck, enc_NIL},
+		{encodeModAmt1Check, enc_NIL},
+	},
+}
+
+var a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt2Check = operand{
+	class: AC_MEMEXT, elemEncoders: []elemEncoder{
+		{encodeRn510SPV2, enc_Rn},
+		{encodeNoop, enc_NIL},
+		{encodeRm1621V2, enc_Rm},
+		{encodeNoop, enc_NIL},
+		{encodeModLSLCheck, enc_NIL},
+		{encodeModAmt2Check, enc_NIL},
+	},
+}
+
+var a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt3Check = operand{
+	class: AC_MEMEXT, elemEncoders: []elemEncoder{
+		{encodeRn510SPV2, enc_Rn},
+		{encodeNoop, enc_NIL},
+		{encodeRm1621V2, enc_Rm},
+		{encodeNoop, enc_NIL},
+		{encodeModLSLCheck, enc_NIL},
+		{encodeModAmt3Check, enc_NIL},
+	},
+}
+
+var a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt4Check = operand{
+	class: AC_MEMEXT, elemEncoders: []elemEncoder{
+		{encodeRn510SPV2, enc_Rn},
+		{encodeNoop, enc_NIL},
+		{encodeRm1621V2, enc_Rm},
+		{encodeNoop, enc_NIL},
+		{encodeModLSLCheck, enc_NIL},
+		{encodeModAmt4Check, enc_NIL},
+	},
+}
+
+var a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_NoModCheck_NoAmtCheck = operand{
+	class: AC_MEMEXT, elemEncoders: []elemEncoder{
+		{encodeRn510SPV2, enc_Rn},
+		{encodeNoop, enc_NIL},
+		{encodeRm1621V2, enc_Rm},
+		{encodeNoop, enc_NIL},
+		{encodeNoModCheck, enc_NIL},
+		{encodeNoAmtCheck, enc_NIL},
+	},
+}
+
+var a_MEMEXT_Rn510SPV2_Noop_Rm1621XZR_Noop_ModLSLCheck_ModAmt1Check = operand{
+	class: AC_MEMEXT, elemEncoders: []elemEncoder{
+		{encodeRn510SPV2, enc_Rn},
+		{encodeNoop, enc_NIL},
+		{encodeRm1621XZR, enc_Rm},
+		{encodeNoop, enc_NIL},
+		{encodeModLSLCheck, enc_NIL},
+		{encodeModAmt1Check, enc_NIL},
+	},
+}
+
+var a_MEMEXT_Rn510SPV2_Noop_Rm1621XZR_Noop_ModLSLCheck_ModAmt2Check = operand{
+	class: AC_MEMEXT, elemEncoders: []elemEncoder{
+		{encodeRn510SPV2, enc_Rn},
+		{encodeNoop, enc_NIL},
+		{encodeRm1621XZR, enc_Rm},
+		{encodeNoop, enc_NIL},
+		{encodeModLSLCheck, enc_NIL},
+		{encodeModAmt2Check, enc_NIL},
+	},
+}
+
+var a_MEMEXT_Rn510SPV2_Noop_Rm1621XZR_Noop_ModLSLCheck_ModAmt3Check = operand{
+	class: AC_MEMEXT, elemEncoders: []elemEncoder{
+		{encodeRn510SPV2, enc_Rn},
+		{encodeNoop, enc_NIL},
+		{encodeRm1621XZR, enc_Rm},
+		{encodeNoop, enc_NIL},
+		{encodeModLSLCheck, enc_NIL},
+		{encodeModAmt3Check, enc_NIL},
+	},
+}
+
+var a_MEMEXT_Rn510SPV2_Noop_Rm1621XZR_Noop_NoModCheck_NoAmtCheck = operand{
+	class: AC_MEMEXT, elemEncoders: []elemEncoder{
+		{encodeRn510SPV2, enc_Rn},
+		{encodeNoop, enc_NIL},
+		{encodeRm1621XZR, enc_Rm},
+		{encodeNoop, enc_NIL},
+		{encodeNoModCheck, enc_NIL},
+		{encodeNoAmtCheck, enc_NIL},
+	},
+}
+
+var a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_ModLSLCheck_ModAmt1Check = operand{
+	class: AC_MEMEXT, elemEncoders: []elemEncoder{
+		{encodeRn510SPV2, enc_Rn},
+		{encodeNoop, enc_NIL},
+		{encodeZm1621V3, enc_Zm},
+		{encodeArngDCheck, enc_NIL},
+		{encodeModLSLCheck, enc_NIL},
+		{encodeModAmt1Check, enc_NIL},
+	},
+}
+
+var a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_ModLSLCheck_ModAmt2Check = operand{
+	class: AC_MEMEXT, elemEncoders: []elemEncoder{
+		{encodeRn510SPV2, enc_Rn},
+		{encodeNoop, enc_NIL},
+		{encodeZm1621V3, enc_Zm},
+		{encodeArngDCheck, enc_NIL},
+		{encodeModLSLCheck, enc_NIL},
+		{encodeModAmt2Check, enc_NIL},
+	},
+}
+
+var a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_ModLSLCheck_ModAmt3Check = operand{
+	class: AC_MEMEXT, elemEncoders: []elemEncoder{
+		{encodeRn510SPV2, enc_Rn},
+		{encodeNoop, enc_NIL},
+		{encodeZm1621V3, enc_Zm},
+		{encodeArngDCheck, enc_NIL},
+		{encodeModLSLCheck, enc_NIL},
+		{encodeModAmt3Check, enc_NIL},
+	},
+}
+
+var a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_NoModCheck_NoAmtCheck = operand{
+	class: AC_MEMEXT, elemEncoders: []elemEncoder{
+		{encodeRn510SPV2, enc_Rn},
+		{encodeNoop, enc_NIL},
+		{encodeZm1621V3, enc_Zm},
+		{encodeArngDCheck, enc_NIL},
+		{encodeNoModCheck, enc_NIL},
+		{encodeNoAmtCheck, enc_NIL},
+	},
+}
+
+var a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_Xs1415_ModAmt1Check = operand{
+	class: AC_MEMEXT, elemEncoders: []elemEncoder{
+		{encodeRn510SPV2, enc_Rn},
+		{encodeNoop, enc_NIL},
+		{encodeZm1621V3, enc_Zm},
+		{encodeArngDCheck, enc_NIL},
+		{encodeXs1415, enc_xs},
+		{encodeModAmt1Check, enc_NIL},
+	},
+}
+
+var a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_Xs1415_ModAmt2Check = operand{
+	class: AC_MEMEXT, elemEncoders: []elemEncoder{
+		{encodeRn510SPV2, enc_Rn},
+		{encodeNoop, enc_NIL},
+		{encodeZm1621V3, enc_Zm},
+		{encodeArngDCheck, enc_NIL},
+		{encodeXs1415, enc_xs},
+		{encodeModAmt2Check, enc_NIL},
+	},
+}
+
+var a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_Xs1415_ModAmt3Check = operand{
+	class: AC_MEMEXT, elemEncoders: []elemEncoder{
+		{encodeRn510SPV2, enc_Rn},
+		{encodeNoop, enc_NIL},
+		{encodeZm1621V3, enc_Zm},
+		{encodeArngDCheck, enc_NIL},
+		{encodeXs1415, enc_xs},
+		{encodeModAmt3Check, enc_NIL},
+	},
+}
+
+var a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_Xs1415_NoAmtCheck = operand{
+	class: AC_MEMEXT, elemEncoders: []elemEncoder{
+		{encodeRn510SPV2, enc_Rn},
+		{encodeNoop, enc_NIL},
+		{encodeZm1621V3, enc_Zm},
+		{encodeArngDCheck, enc_NIL},
+		{encodeXs1415, enc_xs},
+		{encodeNoAmtCheck, enc_NIL},
+	},
+}
+
+var a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_Xs2223_ModAmt1Check = operand{
+	class: AC_MEMEXT, elemEncoders: []elemEncoder{
+		{encodeRn510SPV2, enc_Rn},
+		{encodeNoop, enc_NIL},
+		{encodeZm1621V3, enc_Zm},
+		{encodeArngDCheck, enc_NIL},
+		{encodeXs2223, enc_xs},
+		{encodeModAmt1Check, enc_NIL},
+	},
+}
+
+var a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_Xs2223_ModAmt2Check = operand{
+	class: AC_MEMEXT, elemEncoders: []elemEncoder{
+		{encodeRn510SPV2, enc_Rn},
+		{encodeNoop, enc_NIL},
+		{encodeZm1621V3, enc_Zm},
+		{encodeArngDCheck, enc_NIL},
+		{encodeXs2223, enc_xs},
+		{encodeModAmt2Check, enc_NIL},
+	},
+}
+
+var a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_Xs2223_ModAmt3Check = operand{
+	class: AC_MEMEXT, elemEncoders: []elemEncoder{
+		{encodeRn510SPV2, enc_Rn},
+		{encodeNoop, enc_NIL},
+		{encodeZm1621V3, enc_Zm},
+		{encodeArngDCheck, enc_NIL},
+		{encodeXs2223, enc_xs},
+		{encodeModAmt3Check, enc_NIL},
+	},
+}
+
+var a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_Xs2223_NoAmtCheck = operand{
+	class: AC_MEMEXT, elemEncoders: []elemEncoder{
+		{encodeRn510SPV2, enc_Rn},
+		{encodeNoop, enc_NIL},
+		{encodeZm1621V3, enc_Zm},
+		{encodeArngDCheck, enc_NIL},
+		{encodeXs2223, enc_xs},
+		{encodeNoAmtCheck, enc_NIL},
+	},
+}
+
+var a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngSCheck_Xs1415_ModAmt1Check = operand{
+	class: AC_MEMEXT, elemEncoders: []elemEncoder{
+		{encodeRn510SPV2, enc_Rn},
+		{encodeNoop, enc_NIL},
+		{encodeZm1621V3, enc_Zm},
+		{encodeArngSCheck, enc_NIL},
+		{encodeXs1415, enc_xs},
+		{encodeModAmt1Check, enc_NIL},
+	},
+}
+
+var a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngSCheck_Xs1415_ModAmt2Check = operand{
+	class: AC_MEMEXT, elemEncoders: []elemEncoder{
+		{encodeRn510SPV2, enc_Rn},
+		{encodeNoop, enc_NIL},
+		{encodeZm1621V3, enc_Zm},
+		{encodeArngSCheck, enc_NIL},
+		{encodeXs1415, enc_xs},
+		{encodeModAmt2Check, enc_NIL},
+	},
+}
+
+var a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngSCheck_Xs1415_NoAmtCheck = operand{
+	class: AC_MEMEXT, elemEncoders: []elemEncoder{
+		{encodeRn510SPV2, enc_Rn},
+		{encodeNoop, enc_NIL},
+		{encodeZm1621V3, enc_Zm},
+		{encodeArngSCheck, enc_NIL},
+		{encodeXs1415, enc_xs},
+		{encodeNoAmtCheck, enc_NIL},
+	},
+}
+
+var a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngSCheck_Xs2223_ModAmt1Check = operand{
+	class: AC_MEMEXT, elemEncoders: []elemEncoder{
+		{encodeRn510SPV2, enc_Rn},
+		{encodeNoop, enc_NIL},
+		{encodeZm1621V3, enc_Zm},
+		{encodeArngSCheck, enc_NIL},
+		{encodeXs2223, enc_xs},
+		{encodeModAmt1Check, enc_NIL},
+	},
+}
+
+var a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngSCheck_Xs2223_ModAmt2Check = operand{
+	class: AC_MEMEXT, elemEncoders: []elemEncoder{
+		{encodeRn510SPV2, enc_Rn},
+		{encodeNoop, enc_NIL},
+		{encodeZm1621V3, enc_Zm},
+		{encodeArngSCheck, enc_NIL},
+		{encodeXs2223, enc_xs},
+		{encodeModAmt2Check, enc_NIL},
+	},
+}
+
+var a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngSCheck_Xs2223_NoAmtCheck = operand{
+	class: AC_MEMEXT, elemEncoders: []elemEncoder{
+		{encodeRn510SPV2, enc_Rn},
+		{encodeNoop, enc_NIL},
+		{encodeZm1621V3, enc_Zm},
+		{encodeArngSCheck, enc_NIL},
+		{encodeXs2223, enc_xs},
+		{encodeNoAmtCheck, enc_NIL},
+	},
+}
+
+var a_MEMEXT_Zn510V2_ArngDCheck_Rm1621XZR_Noop_NoModCheck_NoAmtCheck = operand{
+	class: AC_MEMEXT, elemEncoders: []elemEncoder{
+		{encodeZn510V2, enc_Zn},
+		{encodeArngDCheck, enc_NIL},
+		{encodeRm1621XZR, enc_Rm},
+		{encodeNoop, enc_NIL},
+		{encodeNoModCheck, enc_NIL},
+		{encodeNoAmtCheck, enc_NIL},
+	},
+}
+
+var a_MEMEXT_Zn510V2_ArngDCheck_Zm1621V3_ArngDCheck_ModSXTWCheck_Msz1012Amount = operand{
+	class: AC_MEMEXT, elemEncoders: []elemEncoder{
+		{encodeZn510V2, enc_Zn},
+		{encodeArngDCheck, enc_NIL},
+		{encodeZm1621V3, enc_Zm},
+		{encodeArngDCheck, enc_NIL},
+		{encodeModSXTWCheck, enc_NIL},
+		{encodeMsz1012Amount, enc_msz},
+	},
+}
+
+var a_MEMEXT_Zn510V2_ArngDCheck_Zm1621V3_ArngDCheck_ModUXTWCheck_Msz1012Amount = operand{
+	class: AC_MEMEXT, elemEncoders: []elemEncoder{
+		{encodeZn510V2, enc_Zn},
+		{encodeArngDCheck, enc_NIL},
+		{encodeZm1621V3, enc_Zm},
+		{encodeArngDCheck, enc_NIL},
+		{encodeModUXTWCheck, enc_NIL},
+		{encodeMsz1012Amount, enc_msz},
+	},
+}
+
+var a_MEMEXT_Zn510V2_ArngSCheck_Rm1621XZR_Noop_NoModCheck_NoAmtCheck = operand{
+	class: AC_MEMEXT, elemEncoders: []elemEncoder{
+		{encodeZn510V2, enc_Zn},
+		{encodeArngSCheck, enc_NIL},
+		{encodeRm1621XZR, enc_Rm},
+		{encodeNoop, enc_NIL},
+		{encodeNoModCheck, enc_NIL},
+		{encodeNoAmtCheck, enc_NIL},
+	},
+}
+
+var a_MEMEXT_Zn510V2_SzSD2223_Zm1621V3_SzSD2223_Msz1012_Msz1012Amount = operand{
+	class: AC_MEMEXT, elemEncoders: []elemEncoder{
+		{encodeZn510V2, enc_Zn},
+		{encodeSzSD2223, enc_sz},
+		{encodeZm1621V3, enc_Zm},
+		{encodeSzSD2223, enc_sz},
+		{encodeMsz1012, enc_msz},
+		{encodeMsz1012Amount, enc_msz},
+	},
+}
+
 var a_PREGIDX_PnN_58_Noop_I189 = operand{
 	class: AC_PREGIDX, elemEncoders: []elemEncoder{
 		{encodePnN_58, enc_PNn},
@@ -8884,13 +10557,62 @@ var a_REGLIST1_Zn510Table3_ArngHCheck = operand{
 	},
 }
 
-var a_REGLIST1_Zn510_SizeBHSD2224 = operand{
+var a_REGLIST1_Zn510V1_SizeBHSD2224 = operand{
 	class: AC_REGLIST1, elemEncoders: []elemEncoder{
-		{encodeZn510, enc_Zn},
+		{encodeZn510V1, enc_Zn},
 		{encodeSizeBHSD2224, enc_size},
 	},
 }
 
+var a_REGLIST1_Zt05_ArngBCheck = operand{
+	class: AC_REGLIST1, elemEncoders: []elemEncoder{
+		{encodeZt05, enc_Zt},
+		{encodeArngBCheck, enc_NIL},
+	},
+}
+
+var a_REGLIST1_Zt05_ArngDCheck = operand{
+	class: AC_REGLIST1, elemEncoders: []elemEncoder{
+		{encodeZt05, enc_Zt},
+		{encodeArngDCheck, enc_NIL},
+	},
+}
+
+var a_REGLIST1_Zt05_ArngHCheck = operand{
+	class: AC_REGLIST1, elemEncoders: []elemEncoder{
+		{encodeZt05, enc_Zt},
+		{encodeArngHCheck, enc_NIL},
+	},
+}
+
+var a_REGLIST1_Zt05_ArngQCheck = operand{
+	class: AC_REGLIST1, elemEncoders: []elemEncoder{
+		{encodeZt05, enc_Zt},
+		{encodeArngQCheck, enc_NIL},
+	},
+}
+
+var a_REGLIST1_Zt05_ArngSCheck = operand{
+	class: AC_REGLIST1, elemEncoders: []elemEncoder{
+		{encodeZt05, enc_Zt},
+		{encodeArngSCheck, enc_NIL},
+	},
+}
+
+var a_REGLIST1_Zt05_Size2123V1 = operand{
+	class: AC_REGLIST1, elemEncoders: []elemEncoder{
+		{encodeZt05, enc_Zt},
+		{encodeSize2123V1, enc_size},
+	},
+}
+
+var a_REGLIST1_Zt05_Size2123V2 = operand{
+	class: AC_REGLIST1, elemEncoders: []elemEncoder{
+		{encodeZt05, enc_Zt},
+		{encodeSize2123V2, enc_size},
+	},
+}
+
 var a_REGLIST2_Pd04_SizeBHSD2224_Pd04Plus1_SizeBHSD2224 = operand{
 	class: AC_REGLIST2, elemEncoders: []elemEncoder{
 		{encodePd04, enc_Pd},
@@ -8945,6 +10667,171 @@ var a_REGLIST2_Zn510Table1_ArngHCheck_Zn510Table2_ArngHCheck = operand{
 	},
 }
 
+var a_REGLIST2_Zt051_ArngBCheck_Zt052_ArngBCheck = operand{
+	class: AC_REGLIST2, elemEncoders: []elemEncoder{
+		{encodeZt051, enc_Zt},
+		{encodeArngBCheck, enc_NIL},
+		{encodeZt052, enc_Zt},
+		{encodeArngBCheck, enc_NIL},
+	},
+}
+
+var a_REGLIST2_Zt051_ArngDCheck_Zt052_ArngDCheck = operand{
+	class: AC_REGLIST2, elemEncoders: []elemEncoder{
+		{encodeZt051, enc_Zt},
+		{encodeArngDCheck, enc_NIL},
+		{encodeZt052, enc_Zt},
+		{encodeArngDCheck, enc_NIL},
+	},
+}
+
+var a_REGLIST2_Zt051_ArngHCheck_Zt052_ArngHCheck = operand{
+	class: AC_REGLIST2, elemEncoders: []elemEncoder{
+		{encodeZt051, enc_Zt},
+		{encodeArngHCheck, enc_NIL},
+		{encodeZt052, enc_Zt},
+		{encodeArngHCheck, enc_NIL},
+	},
+}
+
+var a_REGLIST2_Zt051_ArngQCheck_Zt052_ArngQCheck = operand{
+	class: AC_REGLIST2, elemEncoders: []elemEncoder{
+		{encodeZt051, enc_Zt},
+		{encodeArngQCheck, enc_NIL},
+		{encodeZt052, enc_Zt},
+		{encodeArngQCheck, enc_NIL},
+	},
+}
+
+var a_REGLIST2_Zt051_ArngSCheck_Zt052_ArngSCheck = operand{
+	class: AC_REGLIST2, elemEncoders: []elemEncoder{
+		{encodeZt051, enc_Zt},
+		{encodeArngSCheck, enc_NIL},
+		{encodeZt052, enc_Zt},
+		{encodeArngSCheck, enc_NIL},
+	},
+}
+
+var a_REGLIST3_Zt051_ArngBCheck_Zt052_ArngBCheck_Zt053_ArngBCheck = operand{
+	class: AC_REGLIST3, elemEncoders: []elemEncoder{
+		{encodeZt051, enc_Zt},
+		{encodeArngBCheck, enc_NIL},
+		{encodeZt052, enc_Zt},
+		{encodeArngBCheck, enc_NIL},
+		{encodeZt053, enc_Zt},
+		{encodeArngBCheck, enc_NIL},
+	},
+}
+
+var a_REGLIST3_Zt051_ArngDCheck_Zt052_ArngDCheck_Zt053_ArngDCheck = operand{
+	class: AC_REGLIST3, elemEncoders: []elemEncoder{
+		{encodeZt051, enc_Zt},
+		{encodeArngDCheck, enc_NIL},
+		{encodeZt052, enc_Zt},
+		{encodeArngDCheck, enc_NIL},
+		{encodeZt053, enc_Zt},
+		{encodeArngDCheck, enc_NIL},
+	},
+}
+
+var a_REGLIST3_Zt051_ArngHCheck_Zt052_ArngHCheck_Zt053_ArngHCheck = operand{
+	class: AC_REGLIST3, elemEncoders: []elemEncoder{
+		{encodeZt051, enc_Zt},
+		{encodeArngHCheck, enc_NIL},
+		{encodeZt052, enc_Zt},
+		{encodeArngHCheck, enc_NIL},
+		{encodeZt053, enc_Zt},
+		{encodeArngHCheck, enc_NIL},
+	},
+}
+
+var a_REGLIST3_Zt051_ArngQCheck_Zt052_ArngQCheck_Zt053_ArngQCheck = operand{
+	class: AC_REGLIST3, elemEncoders: []elemEncoder{
+		{encodeZt051, enc_Zt},
+		{encodeArngQCheck, enc_NIL},
+		{encodeZt052, enc_Zt},
+		{encodeArngQCheck, enc_NIL},
+		{encodeZt053, enc_Zt},
+		{encodeArngQCheck, enc_NIL},
+	},
+}
+
+var a_REGLIST3_Zt051_ArngSCheck_Zt052_ArngSCheck_Zt053_ArngSCheck = operand{
+	class: AC_REGLIST3, elemEncoders: []elemEncoder{
+		{encodeZt051, enc_Zt},
+		{encodeArngSCheck, enc_NIL},
+		{encodeZt052, enc_Zt},
+		{encodeArngSCheck, enc_NIL},
+		{encodeZt053, enc_Zt},
+		{encodeArngSCheck, enc_NIL},
+	},
+}
+
+var a_REGLIST4_Zt051_ArngBCheck_Zt052_ArngBCheck_Zt053_ArngBCheck_Zt054_ArngBCheck = operand{
+	class: AC_REGLIST4, elemEncoders: []elemEncoder{
+		{encodeZt051, enc_Zt},
+		{encodeArngBCheck, enc_NIL},
+		{encodeZt052, enc_Zt},
+		{encodeArngBCheck, enc_NIL},
+		{encodeZt053, enc_Zt},
+		{encodeArngBCheck, enc_NIL},
+		{encodeZt054, enc_Zt},
+		{encodeArngBCheck, enc_NIL},
+	},
+}
+
+var a_REGLIST4_Zt051_ArngDCheck_Zt052_ArngDCheck_Zt053_ArngDCheck_Zt054_ArngDCheck = operand{
+	class: AC_REGLIST4, elemEncoders: []elemEncoder{
+		{encodeZt051, enc_Zt},
+		{encodeArngDCheck, enc_NIL},
+		{encodeZt052, enc_Zt},
+		{encodeArngDCheck, enc_NIL},
+		{encodeZt053, enc_Zt},
+		{encodeArngDCheck, enc_NIL},
+		{encodeZt054, enc_Zt},
+		{encodeArngDCheck, enc_NIL},
+	},
+}
+
+var a_REGLIST4_Zt051_ArngHCheck_Zt052_ArngHCheck_Zt053_ArngHCheck_Zt054_ArngHCheck = operand{
+	class: AC_REGLIST4, elemEncoders: []elemEncoder{
+		{encodeZt051, enc_Zt},
+		{encodeArngHCheck, enc_NIL},
+		{encodeZt052, enc_Zt},
+		{encodeArngHCheck, enc_NIL},
+		{encodeZt053, enc_Zt},
+		{encodeArngHCheck, enc_NIL},
+		{encodeZt054, enc_Zt},
+		{encodeArngHCheck, enc_NIL},
+	},
+}
+
+var a_REGLIST4_Zt051_ArngQCheck_Zt052_ArngQCheck_Zt053_ArngQCheck_Zt054_ArngQCheck = operand{
+	class: AC_REGLIST4, elemEncoders: []elemEncoder{
+		{encodeZt051, enc_Zt},
+		{encodeArngQCheck, enc_NIL},
+		{encodeZt052, enc_Zt},
+		{encodeArngQCheck, enc_NIL},
+		{encodeZt053, enc_Zt},
+		{encodeArngQCheck, enc_NIL},
+		{encodeZt054, enc_Zt},
+		{encodeArngQCheck, enc_NIL},
+	},
+}
+
+var a_REGLIST4_Zt051_ArngSCheck_Zt052_ArngSCheck_Zt053_ArngSCheck_Zt054_ArngSCheck = operand{
+	class: AC_REGLIST4, elemEncoders: []elemEncoder{
+		{encodeZt051, enc_Zt},
+		{encodeArngSCheck, enc_NIL},
+		{encodeZt052, enc_Zt},
+		{encodeArngSCheck, enc_NIL},
+		{encodeZt053, enc_Zt},
+		{encodeArngSCheck, enc_NIL},
+		{encodeZt054, enc_Zt},
+		{encodeArngSCheck, enc_NIL},
+	},
+}
+
 var a_SPZGREG_Noop_Rd05 = operand{
 	class: AC_SPZGREG, elemEncoders: []elemEncoder{
 		{encodeNoop, enc_NIL},
@@ -8966,10 +10853,10 @@ var a_SPZGREG_Noop_Rdn05ZR = operand{
 	},
 }
 
-var a_SPZGREG_Noop_Rm1621 = operand{
+var a_SPZGREG_Noop_Rm1621V1 = operand{
 	class: AC_SPZGREG, elemEncoders: []elemEncoder{
 		{encodeNoop, enc_NIL},
-		{encodeRm1621, enc_Rm},
+		{encodeRm1621V1, enc_Rm},
 	},
 }
 
@@ -8994,10 +10881,10 @@ var a_SPZGREG_Noop_Rn510 = operand{
 	},
 }
 
-var a_SPZGREG_Noop_Rn510SP = operand{
+var a_SPZGREG_Noop_Rn510SPV1 = operand{
 	class: AC_SPZGREG, elemEncoders: []elemEncoder{
 		{encodeNoop, enc_NIL},
-		{encodeRn510SP, enc_Rn},
+		{encodeRn510SPV1, enc_Rn},
 	},
 }
 
@@ -9343,13 +11230,13 @@ var Rm__cimm__Zd_T = []operand{
 }
 
 var RnSP__PgM__Zd_T = []operand{
-	a_SPZGREG_Noop_Rn510SP,
+	a_SPZGREG_Noop_Rn510SPV1,
 	a_PREGZM_Pg1013_MergePredCheck,
 	a_ARNG_Zd_SizeBHSD2224,
 }
 
 var RnSP__Zd_T = []operand{
-	a_SPZGREG_Noop_Rn510SP,
+	a_SPZGREG_Noop_Rn510SPV1,
 	a_ARNG_Zd_SizeBHSD2224,
 }
 
@@ -9371,17 +11258,485 @@ var Wdn__Pm_T__Xdn = []operand{
 }
 
 var Xm__Xn__Pd_T = []operand{
-	a_SPZGREG_Noop_Rm1621,
+	a_SPZGREG_Noop_Rm1621V1,
 	a_SPZGREG_Noop_Rn510,
 	a_ARNG_Pd_SizeBHSD2224,
 }
 
 var Xm__Xn___Pd1_T__Pd2_T_ = []operand{
-	a_SPZGREG_Noop_Rm1621,
+	a_SPZGREG_Noop_Rm1621V1,
 	a_SPZGREG_Noop_Rn510,
 	a_REGLIST2_Pd14_SizeBHSD2224_Pd14Plus1_SizeBHSD2224,
 }
 
+var XnSP__Xm__LSL_c1___PgZ___Zt1_H__Zt2_H_ = []operand{
+	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt1Check,
+	a_PREGZM_Pg1013_ZeroPredCheck,
+	a_REGLIST2_Zt051_ArngHCheck_Zt052_ArngHCheck,
+}
+
+var XnSP__Xm__LSL_c1___PgZ___Zt1_H__Zt2_H__Zt3_H_ = []operand{
+	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt1Check,
+	a_PREGZM_Pg1013_ZeroPredCheck,
+	a_REGLIST3_Zt051_ArngHCheck_Zt052_ArngHCheck_Zt053_ArngHCheck,
+}
+
+var XnSP__Xm__LSL_c1___PgZ___Zt1_H__Zt2_H__Zt3_H__Zt4_H_ = []operand{
+	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt1Check,
+	a_PREGZM_Pg1013_ZeroPredCheck,
+	a_REGLIST4_Zt051_ArngHCheck_Zt052_ArngHCheck_Zt053_ArngHCheck_Zt054_ArngHCheck,
+}
+
+var XnSP__Xm__LSL_c1___PgZ___Zt_D_ = []operand{
+	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt1Check,
+	a_PREGZM_Pg1013_ZeroPredCheck,
+	a_REGLIST1_Zt05_ArngDCheck,
+}
+
+var XnSP__Xm__LSL_c1___PgZ___Zt_D__V2 = []operand{
+	a_MEMEXT_Rn510SPV2_Noop_Rm1621XZR_Noop_ModLSLCheck_ModAmt1Check,
+	a_PREGZM_Pg1013_ZeroPredCheck,
+	a_REGLIST1_Zt05_ArngDCheck,
+}
+
+var XnSP__Xm__LSL_c1___PgZ___Zt_H_ = []operand{
+	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt1Check,
+	a_PREGZM_Pg1013_ZeroPredCheck,
+	a_REGLIST1_Zt05_ArngHCheck,
+}
+
+var XnSP__Xm__LSL_c1___PgZ___Zt_H__V2 = []operand{
+	a_MEMEXT_Rn510SPV2_Noop_Rm1621XZR_Noop_ModLSLCheck_ModAmt1Check,
+	a_PREGZM_Pg1013_ZeroPredCheck,
+	a_REGLIST1_Zt05_ArngHCheck,
+}
+
+var XnSP__Xm__LSL_c1___PgZ___Zt_S_ = []operand{
+	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt1Check,
+	a_PREGZM_Pg1013_ZeroPredCheck,
+	a_REGLIST1_Zt05_ArngSCheck,
+}
+
+var XnSP__Xm__LSL_c1___PgZ___Zt_S__V2 = []operand{
+	a_MEMEXT_Rn510SPV2_Noop_Rm1621XZR_Noop_ModLSLCheck_ModAmt1Check,
+	a_PREGZM_Pg1013_ZeroPredCheck,
+	a_REGLIST1_Zt05_ArngSCheck,
+}
+
+var XnSP__Xm__LSL_c1___Pg___Zt1_H__Zt2_H_ = []operand{
+	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt1Check,
+	a_PREG_Pg1013_Noop,
+	a_REGLIST2_Zt051_ArngHCheck_Zt052_ArngHCheck,
+}
+
+var XnSP__Xm__LSL_c1___Pg___Zt1_H__Zt2_H__Zt3_H_ = []operand{
+	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt1Check,
+	a_PREG_Pg1013_Noop,
+	a_REGLIST3_Zt051_ArngHCheck_Zt052_ArngHCheck_Zt053_ArngHCheck,
+}
+
+var XnSP__Xm__LSL_c1___Pg___Zt1_H__Zt2_H__Zt3_H__Zt4_H_ = []operand{
+	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt1Check,
+	a_PREG_Pg1013_Noop,
+	a_REGLIST4_Zt051_ArngHCheck_Zt052_ArngHCheck_Zt053_ArngHCheck_Zt054_ArngHCheck,
+}
+
+var XnSP__Xm__LSL_c1___Pg___Zt_H_ = []operand{
+	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt1Check,
+	a_PREG_Pg1013_Noop,
+	a_REGLIST1_Zt05_ArngHCheck,
+}
+
+var XnSP__Xm__LSL_c1___Pg___Zt_T_ = []operand{
+	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt1Check,
+	a_PREG_Pg1013_Noop,
+	a_REGLIST1_Zt05_Size2123V2,
+}
+
+var XnSP__Xm__LSL_c2___PgZ___Zt1_S__Zt2_S_ = []operand{
+	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt2Check,
+	a_PREGZM_Pg1013_ZeroPredCheck,
+	a_REGLIST2_Zt051_ArngSCheck_Zt052_ArngSCheck,
+}
+
+var XnSP__Xm__LSL_c2___PgZ___Zt1_S__Zt2_S__Zt3_S_ = []operand{
+	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt2Check,
+	a_PREGZM_Pg1013_ZeroPredCheck,
+	a_REGLIST3_Zt051_ArngSCheck_Zt052_ArngSCheck_Zt053_ArngSCheck,
+}
+
+var XnSP__Xm__LSL_c2___PgZ___Zt1_S__Zt2_S__Zt3_S__Zt4_S_ = []operand{
+	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt2Check,
+	a_PREGZM_Pg1013_ZeroPredCheck,
+	a_REGLIST4_Zt051_ArngSCheck_Zt052_ArngSCheck_Zt053_ArngSCheck_Zt054_ArngSCheck,
+}
+
+var XnSP__Xm__LSL_c2___PgZ___Zt_D_ = []operand{
+	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt2Check,
+	a_PREGZM_Pg1013_ZeroPredCheck,
+	a_REGLIST1_Zt05_ArngDCheck,
+}
+
+var XnSP__Xm__LSL_c2___PgZ___Zt_D__V2 = []operand{
+	a_MEMEXT_Rn510SPV2_Noop_Rm1621XZR_Noop_ModLSLCheck_ModAmt2Check,
+	a_PREGZM_Pg1013_ZeroPredCheck,
+	a_REGLIST1_Zt05_ArngDCheck,
+}
+
+var XnSP__Xm__LSL_c2___PgZ___Zt_S_ = []operand{
+	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt2Check,
+	a_PREGZM_Pg1013_ZeroPredCheck,
+	a_REGLIST1_Zt05_ArngSCheck,
+}
+
+var XnSP__Xm__LSL_c2___PgZ___Zt_S__V2 = []operand{
+	a_MEMEXT_Rn510SPV2_Noop_Rm1621XZR_Noop_ModLSLCheck_ModAmt2Check,
+	a_PREGZM_Pg1013_ZeroPredCheck,
+	a_REGLIST1_Zt05_ArngSCheck,
+}
+
+var XnSP__Xm__LSL_c2___Pg___Zt1_S__Zt2_S_ = []operand{
+	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt2Check,
+	a_PREG_Pg1013_Noop,
+	a_REGLIST2_Zt051_ArngSCheck_Zt052_ArngSCheck,
+}
+
+var XnSP__Xm__LSL_c2___Pg___Zt1_S__Zt2_S__Zt3_S_ = []operand{
+	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt2Check,
+	a_PREG_Pg1013_Noop,
+	a_REGLIST3_Zt051_ArngSCheck_Zt052_ArngSCheck_Zt053_ArngSCheck,
+}
+
+var XnSP__Xm__LSL_c2___Pg___Zt1_S__Zt2_S__Zt3_S__Zt4_S_ = []operand{
+	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt2Check,
+	a_PREG_Pg1013_Noop,
+	a_REGLIST4_Zt051_ArngSCheck_Zt052_ArngSCheck_Zt053_ArngSCheck_Zt054_ArngSCheck,
+}
+
+var XnSP__Xm__LSL_c2___Pg___Zt_S_ = []operand{
+	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt2Check,
+	a_PREG_Pg1013_Noop,
+	a_REGLIST1_Zt05_ArngSCheck,
+}
+
+var XnSP__Xm__LSL_c3___PgZ___Zt1_D__Zt2_D_ = []operand{
+	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt3Check,
+	a_PREGZM_Pg1013_ZeroPredCheck,
+	a_REGLIST2_Zt051_ArngDCheck_Zt052_ArngDCheck,
+}
+
+var XnSP__Xm__LSL_c3___PgZ___Zt1_D__Zt2_D__Zt3_D_ = []operand{
+	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt3Check,
+	a_PREGZM_Pg1013_ZeroPredCheck,
+	a_REGLIST3_Zt051_ArngDCheck_Zt052_ArngDCheck_Zt053_ArngDCheck,
+}
+
+var XnSP__Xm__LSL_c3___PgZ___Zt1_D__Zt2_D__Zt3_D__Zt4_D_ = []operand{
+	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt3Check,
+	a_PREGZM_Pg1013_ZeroPredCheck,
+	a_REGLIST4_Zt051_ArngDCheck_Zt052_ArngDCheck_Zt053_ArngDCheck_Zt054_ArngDCheck,
+}
+
+var XnSP__Xm__LSL_c3___PgZ___Zt_D_ = []operand{
+	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt3Check,
+	a_PREGZM_Pg1013_ZeroPredCheck,
+	a_REGLIST1_Zt05_ArngDCheck,
+}
+
+var XnSP__Xm__LSL_c3___PgZ___Zt_D__V2 = []operand{
+	a_MEMEXT_Rn510SPV2_Noop_Rm1621XZR_Noop_ModLSLCheck_ModAmt3Check,
+	a_PREGZM_Pg1013_ZeroPredCheck,
+	a_REGLIST1_Zt05_ArngDCheck,
+}
+
+var XnSP__Xm__LSL_c3___Pg___Zt1_D__Zt2_D_ = []operand{
+	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt3Check,
+	a_PREG_Pg1013_Noop,
+	a_REGLIST2_Zt051_ArngDCheck_Zt052_ArngDCheck,
+}
+
+var XnSP__Xm__LSL_c3___Pg___Zt1_D__Zt2_D__Zt3_D_ = []operand{
+	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt3Check,
+	a_PREG_Pg1013_Noop,
+	a_REGLIST3_Zt051_ArngDCheck_Zt052_ArngDCheck_Zt053_ArngDCheck,
+}
+
+var XnSP__Xm__LSL_c3___Pg___Zt1_D__Zt2_D__Zt3_D__Zt4_D_ = []operand{
+	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt3Check,
+	a_PREG_Pg1013_Noop,
+	a_REGLIST4_Zt051_ArngDCheck_Zt052_ArngDCheck_Zt053_ArngDCheck_Zt054_ArngDCheck,
+}
+
+var XnSP__Xm__LSL_c3___Pg___Zt_D_ = []operand{
+	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt3Check,
+	a_PREG_Pg1013_Noop,
+	a_REGLIST1_Zt05_ArngDCheck,
+}
+
+var XnSP__Xm__LSL_c4___PgZ___Zt1_Q__Zt2_Q_ = []operand{
+	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt4Check,
+	a_PREGZM_Pg1013_ZeroPredCheck,
+	a_REGLIST2_Zt051_ArngQCheck_Zt052_ArngQCheck,
+}
+
+var XnSP__Xm__LSL_c4___PgZ___Zt1_Q__Zt2_Q__Zt3_Q_ = []operand{
+	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt4Check,
+	a_PREGZM_Pg1013_ZeroPredCheck,
+	a_REGLIST3_Zt051_ArngQCheck_Zt052_ArngQCheck_Zt053_ArngQCheck,
+}
+
+var XnSP__Xm__LSL_c4___PgZ___Zt1_Q__Zt2_Q__Zt3_Q__Zt4_Q_ = []operand{
+	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt4Check,
+	a_PREGZM_Pg1013_ZeroPredCheck,
+	a_REGLIST4_Zt051_ArngQCheck_Zt052_ArngQCheck_Zt053_ArngQCheck_Zt054_ArngQCheck,
+}
+
+var XnSP__Xm__LSL_c4___Pg___Zt1_Q__Zt2_Q_ = []operand{
+	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt4Check,
+	a_PREG_Pg1013_Noop,
+	a_REGLIST2_Zt051_ArngQCheck_Zt052_ArngQCheck,
+}
+
+var XnSP__Xm__LSL_c4___Pg___Zt1_Q__Zt2_Q__Zt3_Q_ = []operand{
+	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt4Check,
+	a_PREG_Pg1013_Noop,
+	a_REGLIST3_Zt051_ArngQCheck_Zt052_ArngQCheck_Zt053_ArngQCheck,
+}
+
+var XnSP__Xm__LSL_c4___Pg___Zt1_Q__Zt2_Q__Zt3_Q__Zt4_Q_ = []operand{
+	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt4Check,
+	a_PREG_Pg1013_Noop,
+	a_REGLIST4_Zt051_ArngQCheck_Zt052_ArngQCheck_Zt053_ArngQCheck_Zt054_ArngQCheck,
+}
+
+var XnSP__Xm___PgZ___Zt1_B__Zt2_B_ = []operand{
+	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_NoModCheck_NoAmtCheck,
+	a_PREGZM_Pg1013_ZeroPredCheck,
+	a_REGLIST2_Zt051_ArngBCheck_Zt052_ArngBCheck,
+}
+
+var XnSP__Xm___PgZ___Zt1_B__Zt2_B__Zt3_B_ = []operand{
+	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_NoModCheck_NoAmtCheck,
+	a_PREGZM_Pg1013_ZeroPredCheck,
+	a_REGLIST3_Zt051_ArngBCheck_Zt052_ArngBCheck_Zt053_ArngBCheck,
+}
+
+var XnSP__Xm___PgZ___Zt1_B__Zt2_B__Zt3_B__Zt4_B_ = []operand{
+	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_NoModCheck_NoAmtCheck,
+	a_PREGZM_Pg1013_ZeroPredCheck,
+	a_REGLIST4_Zt051_ArngBCheck_Zt052_ArngBCheck_Zt053_ArngBCheck_Zt054_ArngBCheck,
+}
+
+var XnSP__Xm___PgZ___Zt_B_ = []operand{
+	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_NoModCheck_NoAmtCheck,
+	a_PREGZM_Pg1013_ZeroPredCheck,
+	a_REGLIST1_Zt05_ArngBCheck,
+}
+
+var XnSP__Xm___PgZ___Zt_B__V2 = []operand{
+	a_MEMEXT_Rn510SPV2_Noop_Rm1621XZR_Noop_NoModCheck_NoAmtCheck,
+	a_PREGZM_Pg1013_ZeroPredCheck,
+	a_REGLIST1_Zt05_ArngBCheck,
+}
+
+var XnSP__Xm___PgZ___Zt_D_ = []operand{
+	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_NoModCheck_NoAmtCheck,
+	a_PREGZM_Pg1013_ZeroPredCheck,
+	a_REGLIST1_Zt05_ArngDCheck,
+}
+
+var XnSP__Xm___PgZ___Zt_D__V2 = []operand{
+	a_MEMEXT_Rn510SPV2_Noop_Rm1621XZR_Noop_NoModCheck_NoAmtCheck,
+	a_PREGZM_Pg1013_ZeroPredCheck,
+	a_REGLIST1_Zt05_ArngDCheck,
+}
+
+var XnSP__Xm___PgZ___Zt_H_ = []operand{
+	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_NoModCheck_NoAmtCheck,
+	a_PREGZM_Pg1013_ZeroPredCheck,
+	a_REGLIST1_Zt05_ArngHCheck,
+}
+
+var XnSP__Xm___PgZ___Zt_H__V2 = []operand{
+	a_MEMEXT_Rn510SPV2_Noop_Rm1621XZR_Noop_NoModCheck_NoAmtCheck,
+	a_PREGZM_Pg1013_ZeroPredCheck,
+	a_REGLIST1_Zt05_ArngHCheck,
+}
+
+var XnSP__Xm___PgZ___Zt_S_ = []operand{
+	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_NoModCheck_NoAmtCheck,
+	a_PREGZM_Pg1013_ZeroPredCheck,
+	a_REGLIST1_Zt05_ArngSCheck,
+}
+
+var XnSP__Xm___PgZ___Zt_S__V2 = []operand{
+	a_MEMEXT_Rn510SPV2_Noop_Rm1621XZR_Noop_NoModCheck_NoAmtCheck,
+	a_PREGZM_Pg1013_ZeroPredCheck,
+	a_REGLIST1_Zt05_ArngSCheck,
+}
+
+var XnSP__Xm___Pg___Zt1_B__Zt2_B_ = []operand{
+	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_NoModCheck_NoAmtCheck,
+	a_PREG_Pg1013_Noop,
+	a_REGLIST2_Zt051_ArngBCheck_Zt052_ArngBCheck,
+}
+
+var XnSP__Xm___Pg___Zt1_B__Zt2_B__Zt3_B_ = []operand{
+	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_NoModCheck_NoAmtCheck,
+	a_PREG_Pg1013_Noop,
+	a_REGLIST3_Zt051_ArngBCheck_Zt052_ArngBCheck_Zt053_ArngBCheck,
+}
+
+var XnSP__Xm___Pg___Zt1_B__Zt2_B__Zt3_B__Zt4_B_ = []operand{
+	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_NoModCheck_NoAmtCheck,
+	a_PREG_Pg1013_Noop,
+	a_REGLIST4_Zt051_ArngBCheck_Zt052_ArngBCheck_Zt053_ArngBCheck_Zt054_ArngBCheck,
+}
+
+var XnSP__Xm___Pg___Zt_B_ = []operand{
+	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_NoModCheck_NoAmtCheck,
+	a_PREG_Pg1013_Noop,
+	a_REGLIST1_Zt05_ArngBCheck,
+}
+
+var XnSP__Xm___Pg___Zt_T_ = []operand{
+	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_NoModCheck_NoAmtCheck,
+	a_PREG_Pg1013_Noop,
+	a_REGLIST1_Zt05_Size2123V1,
+}
+
+var XnSP__Zm_D__LSL_c1___PgZ___Zt_D_ = []operand{
+	a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_ModLSLCheck_ModAmt1Check,
+	a_PREGZM_Pg1013_ZeroPredCheck,
+	a_REGLIST1_Zt05_ArngDCheck,
+}
+
+var XnSP__Zm_D__LSL_c1___Pg___Zt_D_ = []operand{
+	a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_ModLSLCheck_ModAmt1Check,
+	a_PREG_Pg1013_Noop,
+	a_REGLIST1_Zt05_ArngDCheck,
+}
+
+var XnSP__Zm_D__LSL_c2___PgZ___Zt_D_ = []operand{
+	a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_ModLSLCheck_ModAmt2Check,
+	a_PREGZM_Pg1013_ZeroPredCheck,
+	a_REGLIST1_Zt05_ArngDCheck,
+}
+
+var XnSP__Zm_D__LSL_c2___Pg___Zt_D_ = []operand{
+	a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_ModLSLCheck_ModAmt2Check,
+	a_PREG_Pg1013_Noop,
+	a_REGLIST1_Zt05_ArngDCheck,
+}
+
+var XnSP__Zm_D__LSL_c3___PgZ___Zt_D_ = []operand{
+	a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_ModLSLCheck_ModAmt3Check,
+	a_PREGZM_Pg1013_ZeroPredCheck,
+	a_REGLIST1_Zt05_ArngDCheck,
+}
+
+var XnSP__Zm_D__LSL_c3___Pg___Zt_D_ = []operand{
+	a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_ModLSLCheck_ModAmt3Check,
+	a_PREG_Pg1013_Noop,
+	a_REGLIST1_Zt05_ArngDCheck,
+}
+
+var XnSP__Zm_D___PgZ___Zt_D_ = []operand{
+	a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_NoModCheck_NoAmtCheck,
+	a_PREGZM_Pg1013_ZeroPredCheck,
+	a_REGLIST1_Zt05_ArngDCheck,
+}
+
+var XnSP__Zm_D___Pg___Zt_D_ = []operand{
+	a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_NoModCheck_NoAmtCheck,
+	a_PREG_Pg1013_Noop,
+	a_REGLIST1_Zt05_ArngDCheck,
+}
+
+var XnSP__Zm_D__mod___PgZ___Zt_D_ = []operand{
+	a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_Xs2223_NoAmtCheck,
+	a_PREGZM_Pg1013_ZeroPredCheck,
+	a_REGLIST1_Zt05_ArngDCheck,
+}
+
+var XnSP__Zm_D__mod___Pg___Zt_D_ = []operand{
+	a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_Xs1415_NoAmtCheck,
+	a_PREG_Pg1013_Noop,
+	a_REGLIST1_Zt05_ArngDCheck,
+}
+
+var XnSP__Zm_D__mod_c1___PgZ___Zt_D_ = []operand{
+	a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_Xs2223_ModAmt1Check,
+	a_PREGZM_Pg1013_ZeroPredCheck,
+	a_REGLIST1_Zt05_ArngDCheck,
+}
+
+var XnSP__Zm_D__mod_c1___Pg___Zt_D_ = []operand{
+	a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_Xs1415_ModAmt1Check,
+	a_PREG_Pg1013_Noop,
+	a_REGLIST1_Zt05_ArngDCheck,
+}
+
+var XnSP__Zm_D__mod_c2___PgZ___Zt_D_ = []operand{
+	a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_Xs2223_ModAmt2Check,
+	a_PREGZM_Pg1013_ZeroPredCheck,
+	a_REGLIST1_Zt05_ArngDCheck,
+}
+
+var XnSP__Zm_D__mod_c2___Pg___Zt_D_ = []operand{
+	a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_Xs1415_ModAmt2Check,
+	a_PREG_Pg1013_Noop,
+	a_REGLIST1_Zt05_ArngDCheck,
+}
+
+var XnSP__Zm_D__mod_c3___PgZ___Zt_D_ = []operand{
+	a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_Xs2223_ModAmt3Check,
+	a_PREGZM_Pg1013_ZeroPredCheck,
+	a_REGLIST1_Zt05_ArngDCheck,
+}
+
+var XnSP__Zm_D__mod_c3___Pg___Zt_D_ = []operand{
+	a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_Xs1415_ModAmt3Check,
+	a_PREG_Pg1013_Noop,
+	a_REGLIST1_Zt05_ArngDCheck,
+}
+
+var XnSP__Zm_S__mod___PgZ___Zt_S_ = []operand{
+	a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngSCheck_Xs2223_NoAmtCheck,
+	a_PREGZM_Pg1013_ZeroPredCheck,
+	a_REGLIST1_Zt05_ArngSCheck,
+}
+
+var XnSP__Zm_S__mod___Pg___Zt_S_ = []operand{
+	a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngSCheck_Xs1415_NoAmtCheck,
+	a_PREG_Pg1013_Noop,
+	a_REGLIST1_Zt05_ArngSCheck,
+}
+
+var XnSP__Zm_S__mod_c1___PgZ___Zt_S_ = []operand{
+	a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngSCheck_Xs2223_ModAmt1Check,
+	a_PREGZM_Pg1013_ZeroPredCheck,
+	a_REGLIST1_Zt05_ArngSCheck,
+}
+
+var XnSP__Zm_S__mod_c1___Pg___Zt_S_ = []operand{
+	a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngSCheck_Xs1415_ModAmt1Check,
+	a_PREG_Pg1013_Noop,
+	a_REGLIST1_Zt05_ArngSCheck,
+}
+
+var XnSP__Zm_S__mod_c2___PgZ___Zt_S_ = []operand{
+	a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngSCheck_Xs2223_ModAmt2Check,
+	a_PREGZM_Pg1013_ZeroPredCheck,
+	a_REGLIST1_Zt05_ArngSCheck,
+}
+
+var XnSP__Zm_S__mod_c2___Pg___Zt_S_ = []operand{
+	a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngSCheck_Xs1415_ModAmt2Check,
+	a_PREG_Pg1013_Noop,
+	a_REGLIST1_Zt05_ArngSCheck,
+}
+
 var Za_D__Zm_D__Zdn_D = []operand{
 	a_ARNG_Za5103Rd_ArngDCheck,
 	a_ARNG_Zm1621V2_ArngDCheck,
@@ -9422,55 +11777,55 @@ var Zm_B__Zdn_B__Zdn_B = []operand{
 
 var Zm_B__Zn_B__Zd_B = []operand{
 	a_ARNG_Zm1621V2_ArngBCheck,
-	a_ARNG_Zn510_ArngBCheck,
+	a_ARNG_Zn510V1_ArngBCheck,
 	a_ARNG_Zd_ArngBCheck,
 }
 
 var Zm_B__Zn_B__Zda_H = []operand{
 	a_ARNG_Zm1621V2_ArngBCheck,
-	a_ARNG_Zn510_ArngBCheck,
+	a_ARNG_Zn510V1_ArngBCheck,
 	a_ARNG_Zda3RdSrcDst_ArngHCheck,
 }
 
 var Zm_B__Zn_B__Zda_S = []operand{
 	a_ARNG_Zm1621V2_ArngBCheck,
-	a_ARNG_Zn510_ArngBCheck,
+	a_ARNG_Zn510V1_ArngBCheck,
 	a_ARNG_Zda3RdSrcDst_ArngSCheck,
 }
 
 var Zm_B_imm___Zn_B__Zda_H__1 = []operand{
 	a_ARNGIDX_Zm_1619_Range0_7V2_ArngBCheck_I4hI4l_1019,
-	a_ARNG_Zn510_ArngBCheck,
+	a_ARNG_Zn510V1_ArngBCheck,
 	a_ARNG_Zda3RdSrcDst_ArngHCheck,
 }
 
 var Zm_B_imm___Zn_B__Zda_H__2 = []operand{
 	a_ARNGIDX_Zm_1619_Range0_7V2_ArngBCheck_I3hI3l_1923_8To16Bit,
-	a_ARNG_Zn510_ArngBCheck,
+	a_ARNG_Zn510V1_ArngBCheck,
 	a_ARNG_Zda3RdSrcDst_ArngHCheck,
 }
 
 var Zm_B_imm___Zn_B__Zda_H__3 = []operand{
 	a_ARNGIDX_Zm_1619_Range0_7V2_ArngBCheck_I3hI3l_1119_Pair8Bit,
-	a_ARNG_Zn510_ArngBCheck,
+	a_ARNG_Zn510V1_ArngBCheck,
 	a_ARNG_Zda3RdSrcDst_ArngHCheck,
 }
 
 var Zm_B_imm___Zn_B__Zda_S__1 = []operand{
 	a_ARNGIDX_Zm_1619_Range0_7V2_ArngBCheck_I4hI4l_1019,
-	a_ARNG_Zn510_ArngBCheck,
+	a_ARNG_Zn510V1_ArngBCheck,
 	a_ARNG_Zda3RdSrcDst_ArngSCheck,
 }
 
 var Zm_B_imm___Zn_B__Zda_S__2 = []operand{
 	a_ARNGIDX_Zm_1619_Range0_7V2_ArngBCheck_I2_1921_8BitGroup,
-	a_ARNG_Zn510_ArngBCheck,
+	a_ARNG_Zn510V1_ArngBCheck,
 	a_ARNG_Zda3RdSrcDst_ArngSCheck,
 }
 
 var Zm_B_imm___Zn_B__Zda_S__3 = []operand{
 	a_ARNGIDX_Zm1619_8To32Bit_ArngBCheck_I2_1921_8To32Bit,
-	a_ARNG_Zn510_ArngBCheck,
+	a_ARNG_Zn510V1_ArngBCheck,
 	a_ARNG_Zda3RdSrcDst_ArngSCheck,
 }
 
@@ -9490,56 +11845,56 @@ var Zm_D__Zdn_T__PgM__Zdn_T = []operand{
 
 var Zm_D__Zn_D__Zd_D = []operand{
 	a_ARNG_Zm1621V2_ArngDCheck,
-	a_ARNG_Zn510_ArngDCheck,
+	a_ARNG_Zn510V1_ArngDCheck,
 	a_ARNG_Zd_ArngDCheck,
 }
 
 var Zm_D__Zn_D__Zd_Q = []operand{
 	a_ARNG_Zm1621V2_ArngDCheck,
-	a_ARNG_Zn510_ArngDCheck,
+	a_ARNG_Zn510V1_ArngDCheck,
 	a_ARNG_Zd_ArngQCheck,
 }
 
 var Zm_D__Zn_D__Zda_D = []operand{
 	a_ARNG_Zm1621V2_ArngDCheck,
-	a_ARNG_Zn510_ArngDCheck,
+	a_ARNG_Zn510V1_ArngDCheck,
 	a_ARNG_Zda3RdSrcDst_ArngDCheck,
 }
 
 var Zm_D__Zn_T__PgZ__Pd_T = []operand{
 	a_ARNG_Zm1621V2_ArngDCheck,
-	a_ARNG_Zn510_SizeBHS2224,
+	a_ARNG_Zn510V1_SizeBHS2224,
 	a_PREGZM_Pg1013_ZeroPredCheck,
 	a_ARNG_Pd_SizeBHS2224,
 }
 
 var Zm_D__Zn_T__Zd_T = []operand{
 	a_ARNG_Zm1621V2_ArngDCheck,
-	a_ARNG_Zn510_SizeBHS2224,
+	a_ARNG_Zn510V1_SizeBHS2224,
 	a_ARNG_Zd_SizeBHS2224,
 }
 
 var Zm_D_imm___Zn_D__Zd_D__1 = []operand{
 	a_ARNGIDX_Zm1620_64Bit_ArngDCheck_I1_2021_64Bit,
-	a_ARNG_Zn510_ArngDCheck,
+	a_ARNG_Zn510V1_ArngDCheck,
 	a_ARNG_Zd_ArngDCheck,
 }
 
 var Zm_D_imm___Zn_D__Zd_D__2 = []operand{
 	a_ARNGIDX_Zm1620_DoublePrecision_ArngDCheck_I1_2021_DoublePrecision,
-	a_ARNG_Zn510_ArngDCheck,
+	a_ARNG_Zn510V1_ArngDCheck,
 	a_ARNG_Zd_ArngDCheck,
 }
 
 var Zm_D_imm___Zn_D__Zda_D__1 = []operand{
 	a_ARNGIDX_Zm1620_64Bit_ArngDCheck_I1_2021_64Bit,
-	a_ARNG_Zn510_ArngDCheck,
+	a_ARNG_Zn510V1_ArngDCheck,
 	a_ARNG_Zda3RdSrcDst_ArngDCheck,
 }
 
 var Zm_D_imm___Zn_D__Zda_D__2 = []operand{
 	a_ARNGIDX_Zm1620_DoublePrecision_ArngDCheck_I1_2021_DoublePrecision,
-	a_ARNG_Zn510_ArngDCheck,
+	a_ARNG_Zn510V1_ArngDCheck,
 	a_ARNG_Zda3RdSrcDst_ArngDCheck,
 }
 
@@ -9552,104 +11907,104 @@ var Zm_H__Zdn_H__PgM__Zdn_H = []operand{
 
 var Zm_H__Zn_H__PgM__Zda_H = []operand{
 	a_ARNG_Zm1621V2_ArngHCheck,
-	a_ARNG_Zn510_ArngHCheck,
+	a_ARNG_Zn510V1_ArngHCheck,
 	a_PREGZM_Pg1013_MergePredCheck,
 	a_ARNG_Zda3RdSrcDst_ArngHCheck,
 }
 
 var Zm_H__Zn_H__Zd_H = []operand{
 	a_ARNG_Zm1621V2_ArngHCheck,
-	a_ARNG_Zn510_ArngHCheck,
+	a_ARNG_Zn510V1_ArngHCheck,
 	a_ARNG_Zd_ArngHCheck,
 }
 
 var Zm_H__Zn_H__Zda_H = []operand{
 	a_ARNG_Zm1621V2_ArngHCheck,
-	a_ARNG_Zn510_ArngHCheck,
+	a_ARNG_Zn510V1_ArngHCheck,
 	a_ARNG_Zda3RdSrcDst_ArngHCheck,
 }
 
 var Zm_H__Zn_H__Zda_S = []operand{
 	a_ARNG_Zm1621V2_ArngHCheck,
-	a_ARNG_Zn510_ArngHCheck,
+	a_ARNG_Zn510V1_ArngHCheck,
 	a_ARNG_Zda3RdSrcDst_ArngSCheck,
 }
 
 var Zm_H_imm___Zn_H__Zd_H__1 = []operand{
 	a_ARNGIDX_Zm1619_16Bit32Bit_ArngHCheck_I3hI3l_1923_16Bit,
-	a_ARNG_Zn510_ArngHCheck,
+	a_ARNG_Zn510V1_ArngHCheck,
 	a_ARNG_Zd_ArngHCheck,
 }
 
 var Zm_H_imm___Zn_H__Zd_H__2 = []operand{
 	a_ARNGIDX_Zm_1619_Range0_7V2_ArngHCheck_I3hI3l_1922,
-	a_ARNG_Zn510_ArngHCheck,
+	a_ARNG_Zn510V1_ArngHCheck,
 	a_ARNG_Zd_ArngHCheck,
 }
 
 var Zm_H_imm___Zn_H__Zd_H__3 = []operand{
 	a_ARNGIDX_Zm1619_HalfSinglePrecision_ArngHCheck_I3hI3l_1923_HalfPrecision,
-	a_ARNG_Zn510_ArngHCheck,
+	a_ARNG_Zn510V1_ArngHCheck,
 	a_ARNG_Zd_ArngHCheck,
 }
 
 var Zm_H_imm___Zn_H__Zd_S = []operand{
 	a_ARNGIDX_Zm1619_32Bit_ArngHCheck_I3hI3l_1119_32Bit,
-	a_ARNG_Zn510_ArngHCheck,
+	a_ARNG_Zn510V1_ArngHCheck,
 	a_ARNG_Zd_ArngSCheck,
 }
 
 var Zm_H_imm___Zn_H__Zda_D = []operand{
 	a_ARNGIDX_Zm1620_16To64Bit_ArngHCheck_I1_2021_16To64Bit,
-	a_ARNG_Zn510_ArngHCheck,
+	a_ARNG_Zn510V1_ArngHCheck,
 	a_ARNG_Zda3RdSrcDst_ArngDCheck,
 }
 
 var Zm_H_imm___Zn_H__Zda_H__1 = []operand{
 	a_ARNGIDX_Zm1619_16Bit32Bit_ArngHCheck_I3hI3l_1923_16Bit,
-	a_ARNG_Zn510_ArngHCheck,
+	a_ARNG_Zn510V1_ArngHCheck,
 	a_ARNG_Zda3RdSrcDst_ArngHCheck,
 }
 
 var Zm_H_imm___Zn_H__Zda_H__2 = []operand{
 	a_ARNGIDX_Zm_1619_Range0_7V2_ArngHCheck_I3hI3l_1922,
-	a_ARNG_Zn510_ArngHCheck,
+	a_ARNG_Zn510V1_ArngHCheck,
 	a_ARNG_Zda3RdSrcDst_ArngHCheck,
 }
 
 var Zm_H_imm___Zn_H__Zda_H__3 = []operand{
 	a_ARNGIDX_Zm1619_HalfSinglePrecision_ArngHCheck_I3hI3l_1923_HalfPrecision,
-	a_ARNG_Zn510_ArngHCheck,
+	a_ARNG_Zn510V1_ArngHCheck,
 	a_ARNG_Zda3RdSrcDst_ArngHCheck,
 }
 
 var Zm_H_imm___Zn_H__Zda_S__1 = []operand{
 	a_ARNGIDX_Zm1619_32Bit_ArngHCheck_I3hI3l_1119_32Bit,
-	a_ARNG_Zn510_ArngHCheck,
+	a_ARNG_Zn510V1_ArngHCheck,
 	a_ARNG_Zda3RdSrcDst_ArngSCheck,
 }
 
 var Zm_H_imm___Zn_H__Zda_S__2 = []operand{
 	a_ARNGIDX_Zm_1619_Range0_7V2_ArngHCheck_I3hI3l_1119,
-	a_ARNG_Zn510_ArngHCheck,
+	a_ARNG_Zn510V1_ArngHCheck,
 	a_ARNG_Zda3RdSrcDst_ArngSCheck,
 }
 
 var Zm_H_imm___Zn_H__Zda_S__3 = []operand{
 	a_ARNGIDX_Zm_1619_Range0_7V2_ArngHCheck_I2_1921_Pair16Bit,
-	a_ARNG_Zn510_ArngHCheck,
+	a_ARNG_Zn510V1_ArngHCheck,
 	a_ARNG_Zda3RdSrcDst_ArngSCheck,
 }
 
 var Zm_H_imm___Zn_H__Zda_S__4 = []operand{
 	a_ARNGIDX_Zm_1619_Range0_7V2_ArngHCheck_I2_1921_16To32Bit,
-	a_ARNG_Zn510_ArngHCheck,
+	a_ARNG_Zn510V1_ArngHCheck,
 	a_ARNG_Zda3RdSrcDst_ArngSCheck,
 }
 
 var Zm_Q__Zn_Q__Zd_Q = []operand{
 	a_ARNG_Zm1621V2_ArngQCheck,
-	a_ARNG_Zn510_ArngQCheck,
+	a_ARNG_Zn510V1_ArngQCheck,
 	a_ARNG_Zd_ArngQCheck,
 }
 
@@ -9661,49 +12016,49 @@ var Zm_S__Zdn_S__Zdn_S = []operand{
 
 var Zm_S__Zn_S__Zd_S = []operand{
 	a_ARNG_Zm1621V2_ArngSCheck,
-	a_ARNG_Zn510_ArngSCheck,
+	a_ARNG_Zn510V1_ArngSCheck,
 	a_ARNG_Zd_ArngSCheck,
 }
 
 var Zm_S__Zn_S__Zda_S = []operand{
 	a_ARNG_Zm1621V2_ArngSCheck,
-	a_ARNG_Zn510_ArngSCheck,
+	a_ARNG_Zn510V1_ArngSCheck,
 	a_ARNG_Zda3RdSrcDst_ArngSCheck,
 }
 
 var Zm_S_imm___Zn_S__Zd_D = []operand{
 	a_ARNGIDX_Zm1620_64Bit_ArngSCheck_I2hI2l_1120_64Bit,
-	a_ARNG_Zn510_ArngSCheck,
+	a_ARNG_Zn510V1_ArngSCheck,
 	a_ARNG_Zd_ArngDCheck,
 }
 
 var Zm_S_imm___Zn_S__Zd_S__1 = []operand{
 	a_ARNGIDX_Zm1619_16Bit32Bit_ArngSCheck_I2_1921_32Bit,
-	a_ARNG_Zn510_ArngSCheck,
+	a_ARNG_Zn510V1_ArngSCheck,
 	a_ARNG_Zd_ArngSCheck,
 }
 
 var Zm_S_imm___Zn_S__Zd_S__2 = []operand{
 	a_ARNGIDX_Zm1619_HalfSinglePrecision_ArngSCheck_I2_1921_SinglePrecision,
-	a_ARNG_Zn510_ArngSCheck,
+	a_ARNG_Zn510V1_ArngSCheck,
 	a_ARNG_Zd_ArngSCheck,
 }
 
 var Zm_S_imm___Zn_S__Zda_D = []operand{
 	a_ARNGIDX_Zm1620_64Bit_ArngSCheck_I2hI2l_1120_64Bit,
-	a_ARNG_Zn510_ArngSCheck,
+	a_ARNG_Zn510V1_ArngSCheck,
 	a_ARNG_Zda3RdSrcDst_ArngDCheck,
 }
 
 var Zm_S_imm___Zn_S__Zda_S__1 = []operand{
 	a_ARNGIDX_Zm1619_16Bit32Bit_ArngSCheck_I2_1921_32Bit,
-	a_ARNG_Zn510_ArngSCheck,
+	a_ARNG_Zn510V1_ArngSCheck,
 	a_ARNG_Zda3RdSrcDst_ArngSCheck,
 }
 
 var Zm_S_imm___Zn_S__Zda_S__2 = []operand{
 	a_ARNGIDX_Zm1619_HalfSinglePrecision_ArngSCheck_I2_1921_SinglePrecision,
-	a_ARNG_Zn510_ArngSCheck,
+	a_ARNG_Zn510V1_ArngSCheck,
 	a_ARNG_Zda3RdSrcDst_ArngSCheck,
 }
 
@@ -9772,122 +12127,122 @@ var Zm_T__Zdn_T__Pv__Zdn_T = []operand{
 
 var Zm_T__Zn_T__PgM__Zda_T__1 = []operand{
 	a_ARNG_Zm1621V2_SizeHSD2224No00,
-	a_ARNG_Zn510_SizeHSD2224No00,
+	a_ARNG_Zn510V1_SizeHSD2224No00,
 	a_PREGZM_Pg1013_MergePredCheck,
 	a_ARNG_Zda3RdSrcDst_SizeHSD2224No00,
 }
 
 var Zm_T__Zn_T__PgM__Zda_T__2 = []operand{
 	a_ARNG_Zm1621V2_SizeBHSD2224,
-	a_ARNG_Zn510_SizeBHSD2224,
+	a_ARNG_Zn510V1_SizeBHSD2224,
 	a_PREGZM_Pg1013_MergePredCheck,
 	a_ARNG_Zda3RdSrcDst_SizeBHSD2224,
 }
 
 var Zm_T__Zn_T__PgZ__Pd_T__1 = []operand{
 	a_ARNG_Zm1621V2_SizeHSD2224,
-	a_ARNG_Zn510_SizeHSD2224,
+	a_ARNG_Zn510V1_SizeHSD2224,
 	a_PREGZM_Pg1013_ZeroPredCheck,
 	a_ARNG_Pd_SizeHSD2224,
 }
 
 var Zm_T__Zn_T__PgZ__Pd_T__2 = []operand{
 	a_ARNG_Zm1621V2_SizeBHSD2224,
-	a_ARNG_Zn510_SizeBHSD2224,
+	a_ARNG_Zn510V1_SizeBHSD2224,
 	a_PREGZM_Pg1013_ZeroPredCheck,
 	a_ARNG_Pd_SizeBHSD2224,
 }
 
 var Zm_T__Zn_T__PgZ__Pd_T__3 = []operand{
 	a_ARNG_Zm1621V2_Size0BH2223,
-	a_ARNG_Zn510_Size0BH2223,
+	a_ARNG_Zn510V1_Size0BH2223,
 	a_PREGZM_Pg1013_ZeroPredCheck,
 	a_ARNG_Pd_Size0BH2223,
 }
 
 var Zm_T__Zn_T__PgZ__Zd_T = []operand{
 	a_ARNG_Zm1621V2_Size0SD2223,
-	a_ARNG_Zn510_Size0SD2223,
+	a_ARNG_Zn510V1_Size0SD2223,
 	a_PREGZM_Pg1013_ZeroPredCheck,
 	a_ARNG_Zd_Size0SD2223,
 }
 
 var Zm_T__Zn_T__Pv__Zd_T = []operand{
 	a_ARNG_Zm1621V2_SizeBHSD2224,
-	a_ARNG_Zn510_SizeBHSD2224,
+	a_ARNG_Zn510V1_SizeBHSD2224,
 	a_PREG_Pv1014_Noop,
 	a_ARNG_Zd_SizeBHSD2224,
 }
 
 var Zm_T__Zn_T__Zd_T__1 = []operand{
 	a_ARNG_Zm1621V2_SizeBHSD2224,
-	a_ARNG_Zn510_SizeBHSD2224,
+	a_ARNG_Zn510V1_SizeBHSD2224,
 	a_ARNG_Zd_SizeBHSD2224,
 }
 
 var Zm_T__Zn_T__Zd_T__2 = []operand{
 	a_ARNG_Zm1621V2_SizeHSD2224No00,
-	a_ARNG_Zn510_SizeHSD2224No00,
+	a_ARNG_Zn510V1_SizeHSD2224No00,
 	a_ARNG_Zd_SizeHSD2224No00,
 }
 
 var Zm_T__Zn_T__Zd_T__3 = []operand{
 	a_ARNG_Zm1621V2_SizeHSD2224,
-	a_ARNG_Zn510_SizeHSD2224,
+	a_ARNG_Zn510V1_SizeHSD2224,
 	a_ARNG_Zd_SizeHSD2224,
 }
 
 var Zm_T__Zn_T__Zda_T__1 = []operand{
 	a_ARNG_Zm1621V2_SzSD2223,
-	a_ARNG_Zn510_SzSD2223,
+	a_ARNG_Zn510V1_SzSD2223,
 	a_ARNG_Zda3RdSrcDst_SzSD2223,
 }
 
 var Zm_T__Zn_T__Zda_T__2 = []operand{
 	a_ARNG_Zm1621V2_SizeBHSD2224,
-	a_ARNG_Zn510_SizeBHSD2224,
+	a_ARNG_Zn510V1_SizeBHSD2224,
 	a_ARNG_Zda3RdSrcDst_SizeBHSD2224,
 }
 
 var Zm_T___Zn_T___Zd_T = []operand{
 	a_ARNG_Zm1621V2_SizeBHSD2224,
-	a_REGLIST1_Zn510_SizeBHSD2224,
+	a_REGLIST1_Zn510V1_SizeBHSD2224,
 	a_ARNG_Zd_SizeBHSD2224,
 }
 
 var Zm_Tb__Zn_T__Zd_T = []operand{
 	a_ARNG_Zm1621V2_SizeTbBHS2224,
-	a_ARNG_Zn510_SizeHSD2224,
+	a_ARNG_Zn510V1_SizeHSD2224,
 	a_ARNG_Zd_SizeHSD2224,
 }
 
 var Zm_Tb__Zn_Tb__Zd_T__1 = []operand{
 	a_ARNG_Zm1621V2_SizeTbBHS2224,
-	a_ARNG_Zn510_SizeTbBHS2224,
+	a_ARNG_Zn510V1_SizeTbBHS2224,
 	a_ARNG_Zd_SizeHSD2224,
 }
 
 var Zm_Tb__Zn_Tb__Zd_T__2 = []operand{
 	a_ARNG_Zm1621V2_SizeTbHSD2224Offset1,
-	a_ARNG_Zn510_SizeTbHSD2224Offset1,
+	a_ARNG_Zn510V1_SizeTbHSD2224Offset1,
 	a_ARNG_Zd_SizeBHS2224Offset1,
 }
 
 var Zm_Tb__Zn_Tb__Zd_T__3 = []operand{
 	a_ARNG_Zm1621V2_SizeTbBS2224,
-	a_ARNG_Zn510_SizeTbBS2224,
+	a_ARNG_Zn510V1_SizeTbBS2224,
 	a_ARNG_Zd_SizeHD2224,
 }
 
 var Zm_Tb__Zn_Tb__Zda_T__1 = []operand{
 	a_ARNG_Zm1621V2_SizeTbBHS2224,
-	a_ARNG_Zn510_SizeTbBHS2224,
+	a_ARNG_Zn510V1_SizeTbBHS2224,
 	a_ARNG_Zda3RdSrcDst_SizeHSD2224,
 }
 
 var Zm_Tb__Zn_Tb__Zda_T__2 = []operand{
 	a_ARNG_Zm1621V2_Size0TbBH2223,
-	a_ARNG_Zn510_Size0TbBH2223,
+	a_ARNG_Zn510V1_Size0TbBH2223,
 	a_ARNG_Zda3RdSrcDst_Size0SD2223,
 }
 
@@ -9933,6 +12288,12 @@ var Zm_index____Zn_H___Zd_H__2 = []operand{
 	a_ARNG_Zd_ArngHCheck,
 }
 
+var Zn1_T__Zn2_T___Pv__Zd_T = []operand{
+	a_REGLIST2_Zn510MultiSrc1_SizeBHSD2224_Zn510MultiSrc2_SizeBHSD2224,
+	a_PREG_Pv1013_Noop,
+	a_ARNG_Zd_SizeBHSD2224,
+}
+
 var Zn_B__Zd_H = []operand{
 	a_ARNG_Zn510Src_ArngBCheck,
 	a_ARNG_Zd_ArngHCheck,
@@ -9974,6 +12335,40 @@ var Zn_D__PgZ__Zd_S = []operand{
 	a_ARNG_Zd_ArngSCheck,
 }
 
+var Zn_D__Xm___PgZ___Zt_D_ = []operand{
+	a_MEMEXT_Zn510V2_ArngDCheck_Rm1621XZR_Noop_NoModCheck_NoAmtCheck,
+	a_PREGZM_Pg1013_ZeroPredCheck,
+	a_REGLIST1_Zt05_ArngDCheck,
+}
+
+var Zn_D__Xm___PgZ___Zt_Q_ = []operand{
+	a_MEMEXT_Zn510V2_ArngDCheck_Rm1621XZR_Noop_NoModCheck_NoAmtCheck,
+	a_PREGZM_Pg1013_ZeroPredCheck,
+	a_REGLIST1_Zt05_ArngQCheck,
+}
+
+var Zn_D__Xm___Pg___Zt_D_ = []operand{
+	a_MEMEXT_Zn510V2_ArngDCheck_Rm1621XZR_Noop_NoModCheck_NoAmtCheck,
+	a_PREG_Pg1013_Noop,
+	a_REGLIST1_Zt05_ArngDCheck,
+}
+
+var Zn_D__Xm___Pg___Zt_Q_ = []operand{
+	a_MEMEXT_Zn510V2_ArngDCheck_Rm1621XZR_Noop_NoModCheck_NoAmtCheck,
+	a_PREG_Pg1013_Noop,
+	a_REGLIST1_Zt05_ArngQCheck,
+}
+
+var Zn_D__Zm_D__SXTWamount___Zd_D = []operand{
+	a_MEMEXT_Zn510V2_ArngDCheck_Zm1621V3_ArngDCheck_ModSXTWCheck_Msz1012Amount,
+	a_ARNG_Zd_ArngDCheck,
+}
+
+var Zn_D__Zm_D__UXTWamount___Zd_D = []operand{
+	a_MEMEXT_Zn510V2_ArngDCheck_Zm1621V3_ArngDCheck_ModUXTWCheck_Msz1012Amount,
+	a_ARNG_Zd_ArngDCheck,
+}
+
 var Zn_H__PgM__Zd_D = []operand{
 	a_ARNG_Zn510Src_ArngHCheck,
 	a_PREGZM_Pg1013_MergePredCheck,
@@ -10058,6 +12453,18 @@ var Zn_S__PgZ__Zd_S = []operand{
 	a_ARNG_Zd_ArngSCheck,
 }
 
+var Zn_S__Xm___PgZ___Zt_S_ = []operand{
+	a_MEMEXT_Zn510V2_ArngSCheck_Rm1621XZR_Noop_NoModCheck_NoAmtCheck,
+	a_PREGZM_Pg1013_ZeroPredCheck,
+	a_REGLIST1_Zt05_ArngSCheck,
+}
+
+var Zn_S__Xm___Pg___Zt_S_ = []operand{
+	a_MEMEXT_Zn510V2_ArngSCheck_Rm1621XZR_Noop_NoModCheck_NoAmtCheck,
+	a_PREG_Pg1013_Noop,
+	a_REGLIST1_Zt05_ArngSCheck,
+}
+
 var Zn_T__PgM__Zd_T__1 = []operand{
 	a_ARNG_Zn510Src_SizeHSD2224,
 	a_PREGZM_Pg1013_MergePredCheck,
@@ -10194,6 +12601,11 @@ var Zn_T__Zd_T__2 = []operand{
 	a_ARNG_Zd_SizeBHSD2224,
 }
 
+var Zn_T__Zm_T__mod_amount___Zd_T = []operand{
+	a_MEMEXT_Zn510V2_SzSD2223_Zm1621V3_SzSD2223_Msz1012_Msz1012Amount,
+	a_ARNG_Zd_SzSD2223,
+}
+
 var Zn_T_imm___Zd_T__1 = []operand{
 	a_ARNGIDX_Zn510Src_Tsz_1621_SizeSpecifier5_Imm2Tsz_Delegate,
 	a_ARNG_Zd_Tsz_1621_SizeSpecifier5,
@@ -10205,7 +12617,7 @@ var Zn_T_imm___Zd_T__2 = []operand{
 }
 
 var Zn_Tb__PgM__Zda_T = []operand{
-	a_ARNG_Zn510_SizeTbBHS2224,
+	a_ARNG_Zn510V1_SizeTbBHS2224,
 	a_PREGZM_Pg1013_MergePredCheck,
 	a_ARNG_ZdaDest_SizeHSD2224,
 }
@@ -10257,12 +12669,6 @@ var Zn_imm___Pd_S = []operand{
 	a_ARNG_Pd_ArngSCheck,
 }
 
-var _Zn1_T__Zn2_T___Pv__Zd_T = []operand{
-	a_REGLIST2_Zn510MultiSrc1_SizeBHSD2224_Zn510MultiSrc2_SizeBHSD2224,
-	a_PREG_Pv1013_Noop,
-	a_ARNG_Zd_SizeBHSD2224,
-}
-
 var c0_0__Zn_T__PgZ__Pd_T = []operand{
 	a_IMM_Fimm0_0_56,
 	a_ARNG_Zn510Src_SizeHSD2224,
@@ -10327,7 +12733,7 @@ var cconst__Zn_T__Zd_T__2 = []operand{
 
 var cconst__Zn_T__Zda_T = []operand{
 	a_IMM_ShiftTsz1619Range1V2,
-	a_ARNG_Zn510_SizeBhsdTsz1921,
+	a_ARNG_Zn510V1_SizeBhsdTsz1921,
 	a_ARNG_Zda3RdSrcDst_SizeBhsdTsz1921,
 }
 
@@ -10466,42 +12872,42 @@ var const__Zdn_T__PgM__Zdn_T__3 = []operand{
 var const__Zm_B_imm___Zn_B__Zda_S = []operand{
 	a_IMM_Rot0_90_180_270_1012,
 	a_ARNGIDX_Zm1619_8To32Bit_ArngBCheck_I2_1921_8To32Bit,
-	a_ARNG_Zn510_ArngBCheck,
+	a_ARNG_Zn510V1_ArngBCheck,
 	a_ARNG_Zda3RdSrcDst_ArngSCheck,
 }
 
 var const__Zm_H_imm___Zn_H__Zda_D = []operand{
 	a_IMM_Rot0_90_180_270_1012,
 	a_ARNGIDX_Zm1620_16To64Bit_ArngHCheck_I1_2021_16To64Bit,
-	a_ARNG_Zn510_ArngHCheck,
+	a_ARNG_Zn510V1_ArngHCheck,
 	a_ARNG_Zda3RdSrcDst_ArngDCheck,
 }
 
 var const__Zm_H_imm___Zn_H__Zda_H__1 = []operand{
 	a_IMM_Rot0_90_180_270_1012,
 	a_ARNGIDX_Zm_1619_Range0_7V1_ArngHCheck_I2_1921_16bit,
-	a_ARNG_Zn510_ArngHCheck,
+	a_ARNG_Zn510V1_ArngHCheck,
 	a_ARNG_Zda3RdSrcDst_ArngHCheck,
 }
 
 var const__Zm_H_imm___Zn_H__Zda_H__2 = []operand{
 	a_IMM_Rot0_90_180_270_1012,
 	a_ARNGIDX_Zm_1619_Half_ArngHCheck_I2_1921_Half,
-	a_ARNG_Zn510_ArngHCheck,
+	a_ARNG_Zn510V1_ArngHCheck,
 	a_ARNG_Zda3RdSrcDst_ArngHCheck,
 }
 
 var const__Zm_S_imm___Zn_S__Zda_S__1 = []operand{
 	a_IMM_Rot0_90_180_270_1012,
 	a_ARNGIDX_Zm_1620_Range0_15_ArngSCheck_I1_2021_32bit,
-	a_ARNG_Zn510_ArngSCheck,
+	a_ARNG_Zn510V1_ArngSCheck,
 	a_ARNG_Zda3RdSrcDst_ArngSCheck,
 }
 
 var const__Zm_S_imm___Zn_S__Zda_S__2 = []operand{
 	a_IMM_Rot0_90_180_270_1012,
 	a_ARNGIDX_Zm_1620_Single_ArngSCheck_I1_2021_Single,
-	a_ARNG_Zn510_ArngSCheck,
+	a_ARNG_Zn510V1_ArngSCheck,
 	a_ARNG_Zda3RdSrcDst_ArngSCheck,
 }
 
@@ -10523,7 +12929,7 @@ var const__Zm_T__Zdn_T__Zdn_T = []operand{
 var const__Zm_T__Zn_T__PgM__Zda_T = []operand{
 	a_IMM_Rot0_90_180_270_1315,
 	a_ARNG_Zm1621V2_SizeHSD2224,
-	a_ARNG_Zn510_SizeHSD2224,
+	a_ARNG_Zn510V1_SizeHSD2224,
 	a_PREGZM_Pg1013_MergePredCheck,
 	a_ARNG_Zda3RdSrcDst_SizeHSD2224,
 }
@@ -10531,14 +12937,14 @@ var const__Zm_T__Zn_T__PgM__Zda_T = []operand{
 var const__Zm_T__Zn_T__Zda_T = []operand{
 	a_IMM_Rot0_90_180_270_1012,
 	a_ARNG_Zm1621V2_SizeBHSD2224,
-	a_ARNG_Zn510_SizeBHSD2224,
+	a_ARNG_Zn510V1_SizeBHSD2224,
 	a_ARNG_Zda3RdSrcDst_SizeBHSD2224,
 }
 
 var const__Zm_Tb__Zn_Tb__Zda_T = []operand{
 	a_IMM_Rot0_90_180_270_1012,
 	a_ARNG_Zm1621V2_Size0TbBH2223,
-	a_ARNG_Zn510_Size0TbBH2223,
+	a_ARNG_Zn510V1_Size0TbBH2223,
 	a_ARNG_Zda3RdSrcDst_Size0SD2223,
 }