diff options
| author | Junyang Shao <shaojunyang@google.com> | 2026-03-26 20:25:57 +0000 |
|---|---|---|
| committer | Junyang Shao <shaojunyang@google.com> | 2026-04-10 07:25:07 -0700 |
| commit | ce4459cf0ee339b3bcf0ed10427079a234aade36 (patch) | |
| tree | 8a4798fdf60384f34fffedd15c877f1122dc041a /src/cmd/internal/obj/arm64/a.out.go | |
| parent | 926a1bef08ae6b93b50a96eedb15210e1d8c4733 (diff) | |
| download | go-ce4459cf0ee339b3bcf0ed10427079a234aade36.tar.xz | |
cmd/asm, cmd/internal/obj/arm64: support register with index in SVE
This CL is generated by CL 759800.
The new register patterns are (examples):
Z1.B[5]
Z2[6]
P1[7]
PN1[8]
Change-Id: I5bccc4f1c0474dbd4cd4878bd488f36a7026c7ca
Reviewed-on: https://go-review.googlesource.com/c/go/+/759780
Reviewed-by: David Chase <drchase@google.com>
LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
Diffstat (limited to 'src/cmd/internal/obj/arm64/a.out.go')
| -rw-r--r-- | src/cmd/internal/obj/arm64/a.out.go | 23 |
1 files changed, 16 insertions, 7 deletions
diff --git a/src/cmd/internal/obj/arm64/a.out.go b/src/cmd/internal/obj/arm64/a.out.go index 72e0d519d7..d259a651d5 100644 --- a/src/cmd/internal/obj/arm64/a.out.go +++ b/src/cmd/internal/obj/arm64/a.out.go @@ -218,12 +218,21 @@ const ( // bits 0-4 indicates register: Vn // bits 5-8 indicates arrangement: <T> +// TODO: consider putting the register and arrangement in different fields of an +// [obj.Prog] to make the bit pattern less confusing. const ( - REG_ARNG = obj.RBaseARM64 + 1<<10 + iota<<9 // Vn.<T> - REG_ELEM // Vn.<T>[index] - REG_ELEM_END - REG_ZARNG // Zn.<T> + REG_ARNG = obj.RBaseARM64 + 1<<10 + iota<<9 // Vn.<T> + REG_ELEM // Vn.<T>[index] + REG_ZARNG // Zn.<T> + REG_ZARNGELEM // Zn.<T>[index] + // PZELEM is taking a portion of the P or Z register. + // Since it does not have an arrangement, it interpret bit 5 differently: + // bit 5 = 0: Z register + // bit 5 = 1: P register + REG_PZELEM // Zn[index] or Pn[index] or PNd[index] REG_PARNGZM // Pn.<T> or Pn/M, Pn/Z + // This currently overlaps with REG_EXT, if more arrangements are to be added, + // move REG_EXT to a higher range and update RBase.*. REG_PARNGZM_END ) @@ -621,9 +630,9 @@ const ( AC_ZREG // the scalable vector registers, such as Z1 AC_PREG // the scalable predicate registers, such as P1 AC_PREGZM // Pg.Z or Pg.M - AC_REGIDX // P8[1] - AC_ZREGIDX // Z1[1] - AC_PREGIDX // P0[R1, 1] + AC_PREGIDX // P8[1] or PN1[1] or Z1[1] + AC_ZREGIDX // P8[1] or PN1[1] or Z1[1] + AC_PREGSEL // P0[R1, 1], index is calculated as R1 + 1 AC_ARNG // vector register with arrangement, such as Z1.D AC_ARNGIDX // vector register with arrangement and index, such as Z1.D[1] |