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authorFangming.Fang <fangming.fang@arm.com>2018-03-16 03:19:01 +0000
committerCherry Zhang <cherryyz@google.com>2018-04-03 15:36:31 +0000
commitef9bdd11e8e5d93d268f13b54feedbed7e3fa595 (patch)
treebd6f3a03106ce352616c1d51d6c3b2787128c30b /src/cmd/asm
parentdcaf3fb134d5ca3b74a85b765c39aa5b632638cd (diff)
downloadgo-ef9bdd11e8e5d93d268f13b54feedbed7e3fa595.tar.xz
cmd/asm: add essential instructions for AES-GCM on ARM64
This change adds VLD1, VST1, VPMULL{2}, VEXT, VRBIT, VUSHR and VSHL instructions for supporting AES-GCM implementation later. Fixes #24400 Change-Id: I556feb88067f195cbe25629ec2b7a817acc58709 Reviewed-on: https://go-review.googlesource.com/101095 Reviewed-by: Cherry Zhang <cherryyz@google.com> Run-TryBot: Cherry Zhang <cherryyz@google.com> TryBot-Result: Gobot Gobot <gobot@golang.org>
Diffstat (limited to 'src/cmd/asm')
-rw-r--r--src/cmd/asm/internal/arch/arm64.go10
-rw-r--r--src/cmd/asm/internal/asm/testdata/arm64.s36
-rw-r--r--src/cmd/asm/internal/asm/testdata/arm64error.s14
3 files changed, 59 insertions, 1 deletions
diff --git a/src/cmd/asm/internal/arch/arm64.go b/src/cmd/asm/internal/arch/arm64.go
index 74b7d285df..0bbd7f98c7 100644
--- a/src/cmd/asm/internal/arch/arm64.go
+++ b/src/cmd/asm/internal/arch/arm64.go
@@ -208,11 +208,21 @@ func ARM64RegisterExtension(a *obj.Addr, ext string, reg, num int16, isAmount, i
return errors.New("invalid register extension")
}
a.Reg = arm64.REG_ARNG + (reg & 31) + ((arm64.ARNG_4S & 15) << 5)
+ case "D1":
+ if isIndex {
+ return errors.New("invalid register extension")
+ }
+ a.Reg = arm64.REG_ARNG + (reg & 31) + ((arm64.ARNG_1D & 15) << 5)
case "D2":
if isIndex {
return errors.New("invalid register extension")
}
a.Reg = arm64.REG_ARNG + (reg & 31) + ((arm64.ARNG_2D & 15) << 5)
+ case "Q1":
+ if isIndex {
+ return errors.New("invalid register extension")
+ }
+ a.Reg = arm64.REG_ARNG + (reg & 31) + ((arm64.ARNG_1Q & 15) << 5)
case "B":
if !isIndex {
return nil
diff --git a/src/cmd/asm/internal/asm/testdata/arm64.s b/src/cmd/asm/internal/asm/testdata/arm64.s
index 65ebdb9417..8ee2e01615 100644
--- a/src/cmd/asm/internal/asm/testdata/arm64.s
+++ b/src/cmd/asm/internal/asm/testdata/arm64.s
@@ -78,6 +78,28 @@ TEXT foo(SB), DUPOK|NOSPLIT, $-8
VFMLS V1.D2, V12.D2, V1.D2 // 81cde14e
VFMLS V1.S2, V12.S2, V1.S2 // 81cda10e
VFMLS V1.S4, V12.S4, V1.S4 // 81cda14e
+ VPMULL V2.D1, V1.D1, V3.Q1 // 23e0e20e
+ VPMULL2 V2.D2, V1.D2, V4.Q1 // 24e0e24e
+ VPMULL V2.B8, V1.B8, V3.H8 // 23e0220e
+ VPMULL2 V2.B16, V1.B16, V4.H8 // 24e0224e
+ VEXT $4, V2.B8, V1.B8, V3.B8 // 2320022e
+ VEXT $8, V2.B16, V1.B16, V3.B16 // 2340026e
+ VRBIT V24.B16, V24.B16 // 185b606e
+ VRBIT V24.B8, V24.B8 // 185b602e
+ VUSHR $56, V1.D2, V2.D2 // 2204486f
+ VUSHR $24, V1.S4, V2.S4 // 2204286f
+ VUSHR $24, V1.S2, V2.S2 // 2204282f
+ VUSHR $8, V1.H4, V2.H4 // 2204182f
+ VUSHR $8, V1.H8, V2.H8 // 2204186f
+ VUSHR $2, V1.B8, V2.B8 // 22040e2f
+ VUSHR $2, V1.B16, V2.B16 // 22040e6f
+ VSHL $56, V1.D2, V2.D2 // 2254784f
+ VSHL $24, V1.S4, V2.S4 // 2254384f
+ VSHL $24, V1.S2, V2.S2 // 2254380f
+ VSHL $8, V1.H4, V2.H4 // 2254180f
+ VSHL $8, V1.H8, V2.H8 // 2254184f
+ VSHL $2, V1.B8, V2.B8 // 22540a0f
+ VSHL $2, V1.B16, V2.B16 // 22540a4f
// LTYPE1 imsr ',' spreg ','
// {
@@ -144,6 +166,12 @@ TEXT foo(SB), DUPOK|NOSPLIT, $-8
VLD1.P (R3), [V31.H8, V0.H8] // 7fa4df4c
VLD1.P (R8)(R20), [V21.B16, V22.B16] // VLD1.P (R8)(R20*1), [V21.B16,V22.B16] // 15a1d44c
VLD1.P 64(R1), [V5.B16, V6.B16, V7.B16, V8.B16] // 2520df4c
+ VLD1.P 1(R0), V4.B[15] // 041cdf4d
+ VLD1.P 2(R0), V4.H[7] // 0458df4d
+ VLD1.P 4(R0), V4.S[3] // 0490df4d
+ VLD1.P 8(R0), V4.D[1] // 0484df4d
+ VLD1.P (R0)(R1), V4.D[1] // VLD1.P (R0)(R1*1), V4.D[1] // 0484c14d
+ VLD1 (R0), V4.D[1] // 0484404d
VST1.P [V4.S4, V5.S4], 32(R1) // 24a89f4c
VST1 [V0.S4, V1.S4], (R0) // 00a8004c
VLD1 (R30), [V15.S2, V16.S2] // cfab400c
@@ -151,6 +179,12 @@ TEXT foo(SB), DUPOK|NOSPLIT, $-8
VST1.P [V24.S2], 8(R2) // 58789f0c
VST1 [V29.S2, V30.S2], (R29) // bdab000c
VST1 [V14.H4, V15.H4, V16.H4], (R27) // 6e67000c
+ VST1.P V4.B[15], 1(R0) // 041c9f4d
+ VST1.P V4.H[7], 2(R0) // 04589f4d
+ VST1.P V4.S[3], 4(R0) // 04909f4d
+ VST1.P V4.D[1], 8(R0) // 04849f4d
+ VST1.P V4.D[1], (R0)(R1) // VST1.P V4.D[1], (R0)(R1*1) // 0484814d
+ VST1 V4.D[1], (R0) // 0484004d
VMOVS V20, (R0) // 140000bd
VMOVS.P V20, 4(R0) // 144400bc
VMOVS.W V20, 4(R0) // 144c00bc
@@ -233,7 +267,7 @@ TEXT foo(SB), DUPOK|NOSPLIT, $-8
VMOV R20, V1.S[1] // 811e0c4e
VMOV R1, V9.H4 // 290c020e
VMOV R22, V11.D2 // cb0e084e
- VMOV V2.B16, V4.B16 // 441ca24e
+ VMOV V2.B16, V4.B16 // 441ca24e
VMOV V20.S[0], V20 // 9406045e
VMOV V12.D[0], V12.D[1] // 8c05186e
VMOV V10.S[0], V12.S[1] // 4c050c6e
diff --git a/src/cmd/asm/internal/asm/testdata/arm64error.s b/src/cmd/asm/internal/asm/testdata/arm64error.s
index dcdb4fe175..37e9442eca 100644
--- a/src/cmd/asm/internal/asm/testdata/arm64error.s
+++ b/src/cmd/asm/internal/asm/testdata/arm64error.s
@@ -58,4 +58,18 @@ TEXT errors(SB),$0
VST1.P [V4.S4], 8(R1) // ERROR "invalid post-increment offset"
VLD1.P 32(R1), [V8.S4, V9.S4, V10.S4] // ERROR "invalid post-increment offset"
VLD1.P 48(R1), [V7.S4, V8.S4, V9.S4, V10.S4] // ERROR "invalid post-increment offset"
+ VPMULL V1.D1, V2.H4, V3.Q1 // ERROR "invalid arrangement"
+ VPMULL V1.H4, V2.H4, V3.Q1 // ERROR "invalid arrangement"
+ VPMULL V1.D2, V2.D2, V3.Q1 // ERROR "invalid arrangement"
+ VPMULL V1.B16, V2.B16, V3.H8 // ERROR "invalid arrangement"
+ VPMULL2 V1.D2, V2.H4, V3.Q1 // ERROR "invalid arrangement"
+ VPMULL2 V1.H4, V2.H4, V3.Q1 // ERROR "invalid arrangement"
+ VPMULL2 V1.D1, V2.D1, V3.Q1 // ERROR "invalid arrangement"
+ VPMULL2 V1.B8, V2.B8, V3.H8 // ERROR "invalid arrangement"
+ VEXT $8, V1.B16, V2.B8, V2.B16 // ERROR "invalid arrangement"
+ VEXT $8, V1.H8, V2.H8, V2.H8 // ERROR "invalid arrangement"
+ VRBIT V1.B16, V2.B8 // ERROR "invalid arrangement"
+ VRBIT V1.H4, V2.H4 // ERROR "invalid arrangement"
+ VUSHR $56, V1.D2, V2.H4 // ERROR "invalid arrangement"
+ VUSHR $127, V1.D2, V2.D2 // ERROR "shift out of range"
RET
generated by cgit v1.3-5-g9baa (git 2.53.0) at 2026-04-17 03:52:47 +0000