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| author | Balaram Makam <bmakam.qdt@qualcommdatacenter.com> | 2018-04-27 15:44:31 -0400 |
|---|---|---|
| committer | Cherry Zhang <cherryyz@google.com> | 2018-04-30 20:07:37 +0000 |
| commit | c789ce3f75d56b005750dee99321cba2cb9f4f14 (patch) | |
| tree | 4d3f8c00310edb3a9b7f2577911a58a85636edd4 /src/cmd/asm | |
| parent | e3c684777a05ca5a4f9bb59983e07c4e6a7a5e15 (diff) | |
| download | go-c789ce3f75d56b005750dee99321cba2cb9f4f14.tar.xz | |
cmd/asm: add vector instructions for ChaCha20Poly1305 on ARM64
This change provides VZIP1, VZIP2, VTBL instruction for supporting
ChaCha20Poly1305 implementation later.
Change-Id: Ife7c87b8ab1a6495a444478eeb9d906ae4c5ffa9
Reviewed-on: https://go-review.googlesource.com/110015
Reviewed-by: Cherry Zhang <cherryyz@google.com>
Run-TryBot: Cherry Zhang <cherryyz@google.com>
TryBot-Result: Gobot Gobot <gobot@golang.org>
Diffstat (limited to 'src/cmd/asm')
| -rw-r--r-- | src/cmd/asm/internal/arch/arm64.go | 7 | ||||
| -rw-r--r-- | src/cmd/asm/internal/asm/asm.go | 9 | ||||
| -rw-r--r-- | src/cmd/asm/internal/asm/testdata/arm64.s | 22 |
3 files changed, 38 insertions, 0 deletions
diff --git a/src/cmd/asm/internal/arch/arm64.go b/src/cmd/asm/internal/arch/arm64.go index 2aadda4b9b..4b30e40b55 100644 --- a/src/cmd/asm/internal/arch/arm64.go +++ b/src/cmd/asm/internal/arch/arm64.go @@ -132,6 +132,13 @@ func arm64RegisterNumber(name string, n int16) (int16, bool) { return 0, false } +// IsARM64TBL reports whether the op (as defined by an arm64.A* +// constant) is one of the table lookup instructions that require special +// handling. +func IsARM64TBL(op obj.As) bool { + return op == arm64.AVTBL +} + // ARM64RegisterExtension parses an ARM64 register with extension or arrangement. func ARM64RegisterExtension(a *obj.Addr, ext string, reg, num int16, isAmount, isIndex bool) error { Rnum := (reg & 31) + int16(num<<5) diff --git a/src/cmd/asm/internal/asm/asm.go b/src/cmd/asm/internal/asm/asm.go index b2d5a75ac4..21dcd06c5c 100644 --- a/src/cmd/asm/internal/asm/asm.go +++ b/src/cmd/asm/internal/asm/asm.go @@ -576,6 +576,15 @@ func (p *Parser) asmInstruction(op obj.As, cond string, a []obj.Addr) { prog.To = a[2] break } + if arch.IsARM64TBL(op) { + prog.From = a[0] + if a[1].Type != obj.TYPE_REGLIST { + p.errorf("%s: expected list; found %s", op, obj.Dconv(prog, &a[1])) + } + prog.SetFrom3(a[1]) + prog.To = a[2] + break + } prog.From = a[0] prog.Reg = p.getRegister(prog, op, &a[1]) prog.To = a[2] diff --git a/src/cmd/asm/internal/asm/testdata/arm64.s b/src/cmd/asm/internal/asm/testdata/arm64.s index 9a2e20acc0..7463689a3c 100644 --- a/src/cmd/asm/internal/asm/testdata/arm64.s +++ b/src/cmd/asm/internal/asm/testdata/arm64.s @@ -107,6 +107,28 @@ TEXT foo(SB), DUPOK|NOSPLIT, $-8 VSRI $8, V1.H8, V2.H8 // 2244186f VSRI $2, V1.B8, V2.B8 // 22440e2f VSRI $2, V1.B16, V2.B16 // 22440e6f + VTBL V22.B16, [V28.B16, V29.B16], V11.B16 // 8b23164e + VTBL V18.B8, [V17.B16, V18.B16, V19.B16], V22.B8 // 3642120e + VTBL V31.B8, [V14.B16, V15.B16, V16.B16, V17.B16], V15.B8 // cf611f0e + VTBL V14.B16, [V16.B16], V11.B16 // 0b020e4e + VTBL V28.B16, [V25.B16, V26.B16], V5.B16 // 25231c4e + VTBL V16.B8, [V4.B16, V5.B16, V6.B16], V12.B8 // 8c40100e + VTBL V4.B8, [V16.B16, V17.B16, V18.B16, V19.B16], V4.B8 // 0462040e + VTBL V15.B8, [V1.B16], V20.B8 // 34000f0e + VTBL V26.B16, [V2.B16, V3.B16], V26.B16 // 5a201a4e + VTBL V15.B8, [V6.B16, V7.B16, V8.B16], V2.B8 // c2400f0e + VTBL V2.B16, [V27.B16, V28.B16, V29.B16, V30.B16], V18.B16 // 7263024e + VTBL V11.B16, [V13.B16], V27.B16 // bb010b4e + VTBL V3.B8, [V7.B16, V8.B16], V25.B8 // f920030e + VTBL V14.B16, [V3.B16, V4.B16, V5.B16], V17.B16 // 71400e4e + VTBL V13.B16, [V29.B16, V30.B16, V31.B16, V0.B16], V28.B16 // bc630d4e + VTBL V3.B8, [V27.B16], V8.B8 // 6803030e + VZIP1 V16.H8, V3.H8, V19.H8 // 7338504e + VZIP2 V22.D2, V25.D2, V21.D2 // 357bd64e + VZIP1 V6.D2, V9.D2, V11.D2 // 2b39c64e + VZIP2 V10.D2, V13.D2, V3.D2 // a379ca4e + VZIP1 V17.S2, V4.S2, V26.S2 // 9a38910e + VZIP2 V25.S2, V14.S2, V25.S2 // d979990e MOVD (R2)(R6.SXTW), R4 // 44c866f8 MOVD (R3)(R6), R5 // MOVD (R3)(R6*1), R5 // 656866f8 MOVD (R2)(R6), R4 // MOVD (R2)(R6*1), R4 // 446866f8 |