diff options
| author | Cherry Zhang <cherryyz@google.com> | 2017-04-11 10:39:55 -0400 |
|---|---|---|
| committer | Cherry Zhang <cherryyz@google.com> | 2017-05-16 17:15:11 +0000 |
| commit | b53acd89db5847b9ddcba076df89bef8788dd348 (patch) | |
| tree | 493bcde661137e8aee2d73c96a3774f2c9bfd127 /src/cmd/asm | |
| parent | 84a51432a80686267e131f5d516559b3d82122b8 (diff) | |
| download | go-b53acd89db5847b9ddcba076df89bef8788dd348.tar.xz | |
cmd/internal/obj/mips: add support of LLV, SCV, NOOP instructions
LLV and SCV are 64-bit load-linked and store-conditional. They
were used in runtime as #define WORD. Change them to normal
instruction form.
NOOP is hardware no-op. It was written as WORD $0. Make a name
for it for better disassembly output.
Fixes #12561.
Fixes #18238.
Change-Id: I82c667ce756fa83ef37b034b641e8c4366335e83
Reviewed-on: https://go-review.googlesource.com/40297
Reviewed-by: Minux Ma <minux@golang.org>
Run-TryBot: Minux Ma <minux@golang.org>
TryBot-Result: Gobot Gobot <gobot@golang.org>
Diffstat (limited to 'src/cmd/asm')
| -rw-r--r-- | src/cmd/asm/internal/asm/testdata/mips64.s | 22 |
1 files changed, 15 insertions, 7 deletions
diff --git a/src/cmd/asm/internal/asm/testdata/mips64.s b/src/cmd/asm/internal/asm/testdata/mips64.s index e3d898af87..50a2694576 100644 --- a/src/cmd/asm/internal/asm/testdata/mips64.s +++ b/src/cmd/asm/internal/asm/testdata/mips64.s @@ -39,6 +39,9 @@ TEXT foo(SB),DUPOK|NOSPLIT,$0 MOVV 16(R1), R2 MOVV (R1), R2 + LL (R1), R2 // c0220000 + LLV (R1), R2 // d0220000 + // LMOVB rreg ',' rreg // { // outcode(int($1), &$2, 0, &$4); @@ -98,6 +101,9 @@ TEXT foo(SB),DUPOK|NOSPLIT,$0 MOVV R1, 16(R2) MOVV R1, (R2) + SC R1, (R2) // e0410000 + SCV R1, (R2) // f0410000 + // LMOVB rreg ',' addr // { // outcode(int($1), &$2, 0, &$4); @@ -238,11 +244,11 @@ TEXT foo(SB),DUPOK|NOSPLIT,$0 label0: JMP 1(PC) BEQ R1, 2(PC) - JMP label0+0 // JMP 64 + JMP label0+0 // JMP 68 BEQ R1, 2(PC) JAL 1(PC) // CALL 1(PC) BEQ R1, 2(PC) - JAL label0+0 // CALL 64 + JAL label0+0 // CALL 68 // LBRA addr // { @@ -266,7 +272,7 @@ label0: // } label1: BEQ R1, 1(PC) - BEQ R1, label1 // BEQ R1, 79 + BEQ R1, label1 // BEQ R1, 83 // LBRA rreg ',' sreg ',' rel // { @@ -274,7 +280,7 @@ label1: // } label2: BEQ R1, R2, 1(PC) - BEQ R1, R2, label2 // BEQ R1, R2, 81 + BEQ R1, R2, label2 // BEQ R1, R2, 85 // // other integer conditional branch @@ -285,7 +291,7 @@ label2: // } label3: BLTZ R1, 1(PC) - BLTZ R1, label3 // BLTZ R1, 83 + BLTZ R1, label3 // BLTZ R1, 87 // // floating point conditional branch @@ -293,7 +299,7 @@ label3: // LBRA rel label4: BFPT 1(PC) - BFPT label4 // BFPT 85 + BFPT label4 // BFPT 89 // @@ -327,7 +333,9 @@ label4: // // WORD // - WORD $1 + WORD $1 // 00000001 + NOOP // 00000000 + SYNC // 0000000f // // NOP |