diff options
| author | Paul E. Murphy <murp@ibm.com> | 2021-03-09 16:55:31 -0600 |
|---|---|---|
| committer | Lynn Boger <laboger@linux.vnet.ibm.com> | 2021-09-14 13:53:08 +0000 |
| commit | b3c6de9dcd9a7258615dea7ca0dcd00878f9027d (patch) | |
| tree | 32103df75b6c1ff78c066067ef5c2e336d1735c7 /src/cmd/asm | |
| parent | ee91bb83198f61aa8f26c3100ca7558d302c0a98 (diff) | |
| download | go-b3c6de9dcd9a7258615dea7ca0dcd00878f9027d.tar.xz | |
cmd/internal/obj/ppc64: allow VR register arguments to VS registers
Likewise, reorder register numbers such that extended mnemonics which
use FPR arguments can be transparently encoded as a VSR argument for
the move to/from VSR class of instructions. Specifically, ensure the
following holds for all FPx and VRx constants: FPRx & 63 == x, and
VRx & 63 == x + 32.
This simplifies encoding machine instructions, and likewise helps
ppc64 assembly writers to avoid hokey workarounds when switching from
vector to vector-scalar register notation. Notably, many VSX
instructions are limited to vector operands due to encoding
restrictions.
Secondly, this explicitly rejects dubious usages of the m[tf]vsr
family of instructions which had previously been accepted.
* Reject two GPR arguments for non-MTVSRDD opcodes. These
have no defined behavior today, and may set RFU bits. e.g
MTVSRD R1, R2, VS1
* Reject FPR destinations for MTVSRDD, and only accept with two GPR
arguments. This copies two GPR values into either half of a VSR. e.g
MTVSRDD R1, R2, F1
MTVSRDD R1, F1
Change-Id: If13dd88c3791d1892dbd18ef0e34675a5285fff9
Reviewed-on: https://go-review.googlesource.com/c/go/+/342929
Run-TryBot: Paul Murphy <murp@ibm.com>
TryBot-Result: Go Bot <gobot@golang.org>
Trust: Lynn Boger <laboger@linux.vnet.ibm.com>
Reviewed-by: Cherry Mui <cherryyz@google.com>
Diffstat (limited to 'src/cmd/asm')
| -rw-r--r-- | src/cmd/asm/internal/asm/testdata/ppc64.s | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/src/cmd/asm/internal/asm/testdata/ppc64.s b/src/cmd/asm/internal/asm/testdata/ppc64.s index b6c0aa5035..28ceb621cb 100644 --- a/src/cmd/asm/internal/asm/testdata/ppc64.s +++ b/src/cmd/asm/internal/asm/testdata/ppc64.s @@ -649,6 +649,8 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$0 LXVB16X (R3)(R4), VS1 // 7c241ed8 LXVW4X (R3)(R4), VS1 // 7c241e18 LXV 16(R3), VS1 // f4230011 + LXV 16(R3), VS33 // f4230019 + LXV 16(R3), V1 // f4230019 LXVL R3, R4, VS1 // 7c23221a LXVLL R3, R4, VS1 // 7c23225a LXVX R3, R4, VS1 // 7c232218 @@ -668,8 +670,13 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$0 MTFPRD R3, F0 // 7c030166 MFVRD V0, R3 // 7c030067 MFVSRLD VS63,R4 // 7fe40267 + MFVSRLD V31,R4 // 7fe40267 MFVSRWZ VS33,R4 // 7c2400e7 + MFVSRWZ V1,R4 // 7c2400e7 MTVSRD R3, VS1 // 7c230166 + MTVSRDD R3, R4, VS1 // 7c232366 + MTVSRDD R3, R4, VS33 // 7c232367 + MTVSRDD R3, R4, V1 // 7c232367 MTVRD R3, V13 // 7da30167 MTVSRWA R4, VS31 // 7fe401a6 MTVSRWS R4, VS32 // 7c040327 @@ -678,6 +685,8 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$0 XXBRW VS1, VS2 // f04f0f6c XXBRH VS2, VS3 // f067176c XXLAND VS1, VS2, VS3 // f0611410 + XXLAND V1, V2, V3 // f0611417 + XXLAND VS33, VS34, VS35 // f0611417 XXLANDC VS1, VS2, VS3 // f0611450 XXLEQV VS0, VS1, VS2 // f0400dd0 XXLNAND VS0, VS1, VS2 // f0400d90 @@ -687,11 +696,17 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$0 XXLORQ VS1, VS2, VS3 // f0611490 XXLXOR VS1, VS2, VS3 // f06114d0 XXSEL VS1, VS2, VS3, VS4 // f08110f0 + XXSEL VS33, VS34, VS35, VS36 // f08110ff + XXSEL V1, V2, V3, V4 // f08110ff XXMRGHW VS1, VS2, VS3 // f0611090 XXMRGLW VS1, VS2, VS3 // f0611190 XXSPLTW VS1, $1, VS2 // f0410a90 + XXSPLTW VS33, $1, VS34 // f0410a93 + XXSPLTW V1, $1, V2 // f0410a93 XXPERM VS1, VS2, VS3 // f06110d0 XXSLDWI VS1, VS2, $1, VS3 // f0611110 + XXSLDWI V1, V2, $1, V3 // f0611117 + XXSLDWI VS33, VS34, $1, VS35 // f0611117 XSCVDPSP VS1, VS2 // f0400c24 XVCVDPSP VS1, VS2 // f0400e24 XSCVSXDDP VS1, VS2 // f0400de0 |