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| author | Joel Sing <joel@sing.id.au> | 2024-02-08 13:54:10 +1100 |
|---|---|---|
| committer | Joel Sing <joel@sing.id.au> | 2024-03-07 14:57:07 +0000 |
| commit | 997636760e2d981bb2f5ba486e0702e60a07ba16 (patch) | |
| tree | f4272eb6f8f4bd67d8b8c73e857f09233419a412 /src/cmd/asm | |
| parent | 58052fe8e707cc0285cffb239bc7a5343243e316 (diff) | |
| download | go-997636760e2d981bb2f5ba486e0702e60a07ba16.tar.xz | |
cmd/compile,cmd/internal/obj: provide rotation pseudo-instructions for riscv64
Provide and use rotation pseudo-instructions for riscv64. The RISC-V bitmanip
extension adds support for hardware rotation instructions in the form of ROL,
ROLW, ROR, RORI, RORIW and RORW. These are easily implemented in the assembler
as pseudo-instructions for CPUs that do not support the bitmanip extension.
This approach provides a number of advantages, including reducing the rewrite
rules needed in the compiler, simplifying codegen tests and most importantly,
allowing these instructions to be used in assembly (for example, riscv64
optimised versions of SHA-256 and SHA-512). When bitmanip support is added,
these instruction sequences can simply be replaced with a single instruction
if permitted by the GORISCV64 profile.
Change-Id: Ia23402e1a82f211ac760690deb063386056ae1fa
Reviewed-on: https://go-review.googlesource.com/c/go/+/565015
TryBot-Result: Gopher Robot <gobot@golang.org>
Reviewed-by: Michael Knyszek <mknyszek@google.com>
Reviewed-by: M Zhuo <mengzhuo1203@gmail.com>
Reviewed-by: Carlos Amedee <carlos@golang.org>
LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
Run-TryBot: Joel Sing <joel@sing.id.au>
Diffstat (limited to 'src/cmd/asm')
| -rw-r--r-- | src/cmd/asm/internal/asm/testdata/riscv64.s | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/src/cmd/asm/internal/asm/testdata/riscv64.s b/src/cmd/asm/internal/asm/testdata/riscv64.s index a5ab254eaa..f944072c6e 100644 --- a/src/cmd/asm/internal/asm/testdata/riscv64.s +++ b/src/cmd/asm/internal/asm/testdata/riscv64.s @@ -417,6 +417,24 @@ start: NEGW X5 // bb025040 NEGW X5, X6 // 3b035040 + // Bitwise rotation pseudo-instructions + ROL X5, X6, X7 // b30f5040b35ff301b3135300b3e37f00 + ROL X5, X6 // b30f5040b35ff3013313530033e36f00 + ROLW X5, X6, X7 // b30f5040bb5ff301bb135300b3e37f00 + ROLW X5, X6 // b30f5040bb5ff3013b13530033e36f00 + ROR X5, X6, X7 // b30f5040b31ff301b3535300b3e37f00 + ROR X5, X6 // b30f5040b31ff3013353530033e36f00 + RORW X5, X6, X7 // b30f5040bb1ff301bb535300b3e37f00 + RORW X5, X6 // b30f5040bb1ff3013b53530033e36f00 + RORI $5, X6, X7 // 935f53009313b303b3e37f00 + RORI $5, X6 // 935f53001313b30333e36f00 + RORIW $5, X6, X7 // 9b5f53009b13b301b3e37f00 + RORIW $5, X6 // 9b5f53001b13b30133e36f00 + ROR $5, X6, X7 // 935f53009313b303b3e37f00 + ROR $5, X6 // 935f53001313b30333e36f00 + RORW $5, X6, X7 // 9b5f53009b13b301b3e37f00 + RORW $5, X6 // 9b5f53001b13b30133e36f00 + // This jumps to the second instruction in the function (the // first instruction is an invisible stack pointer adjustment). JMP start // JMP 2 |