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authorisharipo <iskander.sharipov@intel.com>2017-11-20 20:56:05 +0300
committerIlya Tocar <ilya.tocar@intel.com>2017-11-21 20:29:59 +0000
commit49322ca9ede175cbd62de601ddc1170edcaae1a7 (patch)
tree1932737f4ed66c5d33c5990baca5353e521af9d3 /src/cmd/asm
parent78615844f536c6664909e3269652f4938fd2b027 (diff)
downloadgo-49322ca9ede175cbd62de601ddc1170edcaae1a7.tar.xz
cmd/internal/obj/x86: fix /is4 encoding for VBLEND
Fixes VBLENDVP{D/S}, VPBLENDVB encoding for /is4 imm8[7:4] encoded register operand. Explanation: `reg[r]+regrex[r]+1` will yield correct values for 8..15 reg indexes, but for 0..7 it gives `index+1` results. There was no test that used lower 8 register with /is4 encoding, so the bug passed the tests. The proper solution is to get 4th bit from regrex with a proper shift: `reg[r]|(regrex[r]<<1)`. Instead of inlining `reg[r]|(regrex[r]<<1)` expr, using new `regIndex(r)` function. Test that reproduces this issue is added to amd64enc_extra.s test suite. Bug came from https://golang.org/cl/70650. Change-Id: I846a25e88d5e6df88df9d9c3f5fe94ec55416a33 Reviewed-on: https://go-review.googlesource.com/78815 Run-TryBot: Iskander Sharipov <iskander.sharipov@intel.com> TryBot-Result: Gobot Gobot <gobot@golang.org> Reviewed-by: Ilya Tocar <ilya.tocar@intel.com>
Diffstat (limited to 'src/cmd/asm')
-rw-r--r--src/cmd/asm/internal/asm/testdata/amd64enc_extra.s2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/cmd/asm/internal/asm/testdata/amd64enc_extra.s b/src/cmd/asm/internal/asm/testdata/amd64enc_extra.s
index 6b4d7c7356..a5bcb0f9bc 100644
--- a/src/cmd/asm/internal/asm/testdata/amd64enc_extra.s
+++ b/src/cmd/asm/internal/asm/testdata/amd64enc_extra.s
@@ -233,5 +233,7 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$0
VPGATHERQQ Y0, (R13)(Y1*1), Y2 // c4c2fd91540d00
VPGATHERQQ Y0, 16(R13)(Y1*1), Y2 // c4c2fd91540d10
VPGATHERQQ Y0, 512(R13)(Y1*1), Y2 // c4c2fd91940d00020000
+ // Test low-8 register for /is4 "hr" operand.
+ VPBLENDVB X0, (BX), X1, X2 // c4e3714c1300
// End of tests.
RET