diff options
| author | erifan01 <eric.fang@arm.com> | 2020-08-12 17:41:54 +0800 |
|---|---|---|
| committer | Eric Fang <eric.fang@arm.com> | 2022-04-01 06:36:16 +0000 |
| commit | 26ab2159694b19ef5feb56f4fe7a9cd18360dcdd (patch) | |
| tree | 616bff0a2fe2990a3c856fc31546c71a8aafd647 /src/cmd/asm | |
| parent | 029d2c4524e729dbd913475ca4a5138bb6c5e099 (diff) | |
| download | go-26ab2159694b19ef5feb56f4fe7a9cd18360dcdd.tar.xz | |
cmd/asm: add TLBI instruction on arm64
There was only a placeholder for TLBI instruction in the previous code.
gVisor needs this instruction. This CL completes its support.
This patch is a copy of CL 250758, contributed by Junchen Li(junchen.li@arm.com).
Co-authored-by: Junchen Li(junchen.li@arm.com)
Change-Id: I69e893d2c1f75e227475de9e677548e14870f3cd
Reviewed-on: https://go-review.googlesource.com/c/go/+/302850
Reviewed-by: Cherry Mui <cherryyz@google.com>
Trust: Eric Fang <eric.fang@arm.com>
Run-TryBot: Eric Fang <eric.fang@arm.com>
TryBot-Result: Gopher Robot <gobot@golang.org>
Diffstat (limited to 'src/cmd/asm')
| -rw-r--r-- | src/cmd/asm/internal/asm/testdata/arm64.s | 80 | ||||
| -rw-r--r-- | src/cmd/asm/internal/asm/testdata/arm64enc.s | 2 | ||||
| -rw-r--r-- | src/cmd/asm/internal/asm/testdata/arm64error.s | 5 |
3 files changed, 86 insertions, 1 deletions
diff --git a/src/cmd/asm/internal/asm/testdata/arm64.s b/src/cmd/asm/internal/asm/testdata/arm64.s index 1413bdf476..7866cf1db0 100644 --- a/src/cmd/asm/internal/asm/testdata/arm64.s +++ b/src/cmd/asm/internal/asm/testdata/arm64.s @@ -1630,4 +1630,84 @@ again: MSR R17, ZCR_EL1 // 111218d5 SYS $32768, R1 // 018008d5 SYS $32768 // 1f8008d5 + +// TLBI instruction + TLBI VMALLE1IS // 1f8308d5 + TLBI VMALLE1 // 1f8708d5 + TLBI ALLE2IS // 1f830cd5 + TLBI ALLE1IS // 9f830cd5 + TLBI VMALLS12E1IS // df830cd5 + TLBI ALLE2 // 1f870cd5 + TLBI ALLE1 // 9f870cd5 + TLBI VMALLS12E1 // df870cd5 + TLBI ALLE3IS // 1f830ed5 + TLBI ALLE3 // 1f870ed5 + TLBI VMALLE1OS // 1f8108d5 + TLBI ALLE2OS // 1f810cd5 + TLBI ALLE1OS // 9f810cd5 + TLBI VMALLS12E1OS // df810cd5 + TLBI ALLE3OS // 1f810ed5 + TLBI VAE1IS, R0 // 208308d5 + TLBI ASIDE1IS, R1 // 418308d5 + TLBI VAAE1IS, R2 // 628308d5 + TLBI VALE1IS, R3 // a38308d5 + TLBI VAALE1IS, R4 // e48308d5 + TLBI VAE1, R5 // 258708d5 + TLBI ASIDE1, R6 // 468708d5 + TLBI VAAE1, R7 // 678708d5 + TLBI VALE1, R8 // a88708d5 + TLBI VAALE1, R9 // e98708d5 + TLBI IPAS2E1IS, R10 // 2a800cd5 + TLBI IPAS2LE1IS, R11 // ab800cd5 + TLBI VAE2IS, R12 // 2c830cd5 + TLBI VALE2IS, R13 // ad830cd5 + TLBI IPAS2E1, R14 // 2e840cd5 + TLBI IPAS2LE1, R15 // af840cd5 + TLBI VAE2, R16 // 30870cd5 + TLBI VALE2, R17 // b1870cd5 + TLBI VAE3IS, ZR // 3f830ed5 + TLBI VALE3IS, R19 // b3830ed5 + TLBI VAE3, R20 // 34870ed5 + TLBI VALE3, R21 // b5870ed5 + TLBI VAE1OS, R22 // 368108d5 + TLBI ASIDE1OS, R23 // 578108d5 + TLBI VAAE1OS, R24 // 788108d5 + TLBI VALE1OS, R25 // b98108d5 + TLBI VAALE1OS, R26 // fa8108d5 + TLBI RVAE1IS, R27 // 3b8208d5 + TLBI RVAAE1IS, ZR // 7f8208d5 + TLBI RVALE1IS, R29 // bd8208d5 + TLBI RVAALE1IS, R30 // fe8208d5 + TLBI RVAE1OS, ZR // 3f8508d5 + TLBI RVAAE1OS, R0 // 608508d5 + TLBI RVALE1OS, R1 // a18508d5 + TLBI RVAALE1OS, R2 // e28508d5 + TLBI RVAE1, R3 // 238608d5 + TLBI RVAAE1, R4 // 648608d5 + TLBI RVALE1, R5 // a58608d5 + TLBI RVAALE1, R6 // e68608d5 + TLBI RIPAS2E1IS, R7 // 47800cd5 + TLBI RIPAS2LE1IS, R8 // c8800cd5 + TLBI VAE2OS, R9 // 29810cd5 + TLBI VALE2OS, R10 // aa810cd5 + TLBI RVAE2IS, R11 // 2b820cd5 + TLBI RVALE2IS, R12 // ac820cd5 + TLBI IPAS2E1OS, R13 // 0d840cd5 + TLBI RIPAS2E1, R14 // 4e840cd5 + TLBI RIPAS2E1OS, R15 // 6f840cd5 + TLBI IPAS2LE1OS, R16 // 90840cd5 + TLBI RIPAS2LE1, R17 // d1840cd5 + TLBI RIPAS2LE1OS, ZR // ff840cd5 + TLBI RVAE2OS, R19 // 33850cd5 + TLBI RVALE2OS, R20 // b4850cd5 + TLBI RVAE2, R21 // 35860cd5 + TLBI RVALE2, R22 // b6860cd5 + TLBI VAE3OS, R23 // 37810ed5 + TLBI VALE3OS, R24 // b8810ed5 + TLBI RVAE3IS, R25 // 39820ed5 + TLBI RVALE3IS, R26 // ba820ed5 + TLBI RVAE3OS, R27 // 3b850ed5 + TLBI RVALE3OS, ZR // bf850ed5 + TLBI RVAE3, R29 // 3d860ed5 + TLBI RVALE3, R30 // be860ed5 END diff --git a/src/cmd/asm/internal/asm/testdata/arm64enc.s b/src/cmd/asm/internal/asm/testdata/arm64enc.s index a29862822d..f08e953c98 100644 --- a/src/cmd/asm/internal/asm/testdata/arm64enc.s +++ b/src/cmd/asm/internal/asm/testdata/arm64enc.s @@ -397,7 +397,7 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$-8 SXTH R17, R25 // 393e4093 SXTW R0, R27 // 1b7c4093 SYSL $285440, R12 // 0c5b2cd5 - //TODO TLBI + TLBI VAE1IS, R1 // 218308d5 TSTW $0x80000007, R9 // TSTW $2147483655, R9 // 3f0d0172 TST $0xfffffff0, LR // TST $4294967280, R30 // df6f7cf2 TSTW R10@>21, R2 // 5f54ca6a diff --git a/src/cmd/asm/internal/asm/testdata/arm64error.s b/src/cmd/asm/internal/asm/testdata/arm64error.s index 033c4cda6c..a41f180bb6 100644 --- a/src/cmd/asm/internal/asm/testdata/arm64error.s +++ b/src/cmd/asm/internal/asm/testdata/arm64error.s @@ -432,4 +432,9 @@ TEXT errors(SB),$0 STP (R26, R27), 700(R2) // ERROR "cannot use REGTMP as source" MOVK $0, R10 // ERROR "zero shifts cannot be handled correctly" MOVK $(0<<32), R10 // ERROR "zero shifts cannot be handled correctly" + TLBI PLDL1KEEP // ERROR "illegal argument" + TLBI VMALLE1IS, R0 // ERROR "extraneous register at operand 2" + TLBI ALLE3OS, ZR // ERROR "extraneous register at operand 2" + TLBI VAE1IS // ERROR "missing register at operand 2" + TLBI RVALE3 // ERROR "missing register at operand 2" RET |