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| author | Joel Sing <joel@sing.id.au> | 2019-11-04 04:08:26 +1100 |
|---|---|---|
| committer | Joel Sing <joel@sing.id.au> | 2019-12-24 03:50:29 +0000 |
| commit | 24f08103d2dad591a77c2b716f9a13fc7bb234fc (patch) | |
| tree | a7759641cb43d23e2fbad7be58eadf8bf193cd60 /src/cmd/asm | |
| parent | 7cab55dfd38ca24c327a648907d6befbf828447e (diff) | |
| download | go-24f08103d2dad591a77c2b716f9a13fc7bb234fc.tar.xz | |
cmd/internal/obj/riscv: handle FEQ/FNEG/SEQZ/SNEZ
Based on riscv-go port.
Updates #27532
Change-Id: I5e7f45955e1dfdb9d09cc6a4e6f3ce81216d411d
Reviewed-on: https://go-review.googlesource.com/c/go/+/204628
Reviewed-by: Cherry Zhang <cherryyz@google.com>
Diffstat (limited to 'src/cmd/asm')
| -rw-r--r-- | src/cmd/asm/internal/asm/testdata/riscvenc.s | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/src/cmd/asm/internal/asm/testdata/riscvenc.s b/src/cmd/asm/internal/asm/testdata/riscvenc.s index 21d1c40d9d..3e9319954b 100644 --- a/src/cmd/asm/internal/asm/testdata/riscvenc.s +++ b/src/cmd/asm/internal/asm/testdata/riscvenc.s @@ -282,3 +282,25 @@ start: // real address and updates the immediates for both instructions. CALL asmtest(SB) // 970f0000 JMP asmtest(SB) // 970f0000 + + SEQZ X15, X15 // 93b71700 + SNEZ X15, X15 // b337f000 + + // F extension + FNEGS F0, F1 // d3100020 + + // TODO(jsing): FNES gets encoded as FEQS+XORI - this should + // be handled as a single *obj.Prog so that the full two + // instruction encoding is tested here. + FNES F0, F1, X7 // d3a300a0 + + // D extension + FNEGD F0, F1 // d3100022 + FEQD F0, F1, X5 // d3a200a2 + FLTD F0, F1, X5 // d39200a2 + FLED F0, F1, X5 // d38200a2 + + // TODO(jsing): FNED gets encoded as FEQD+XORI - this should + // be handled as a single *obj.Prog so that the full two + // instruction encoding is tested here. + FNED F0, F1, X5 // d3a200a2 |