cmd/internal/obj/arm64: add CASx/CASPx instructions

This patch adds support for CASx and CASPx atomic instructions.

  go syntax                 gnu syntax
CASD Rs, (Rn|RSP), Rt => cas Xs, Xt, (Xn|SP)
CASALW Rs, (Rn|RSP), Rt => casal Ws, Wt, (Xn|SP)
CASPD (Rs, Rs+1), (Rn|RSP), (Rt, Rt+1) => casp Xs, Xs+1, Xt, Xt+1, (Xn|SP)
CASPW (Rs, Rs+1), (Rn|RSP), (Rt, Rt+1) => casp Ws, Ws+1, Wt, Wt+1, (Xn|SP)

This patch changes the type of prog.RestArgs from "[]Addr" to
"[]struct{Addr, Pos}", Pos is a enum, indicating the position of
the operand.

This patch also adds test cases.

Change-Id: Ib971cfda7890b7aa895d17bab22dea326c7fcaa4
Reviewed-on: https://go-review.googlesource.com/c/go/+/233277
Trust: fannie zhang <Fannie.Zhang@arm.com>
Reviewed-by: Cherry Zhang <cherryyz@google.com>

4 files changed, 49 insertions, 4 deletions

diff --git a/src/cmd/asm/internal/arch/arm64.go b/src/cmd/asm/internal/arch/arm64.go
index e643889aef..e557630ca6 100644
--- a/src/cmd/asm/internal/arch/arm64.go
+++ b/src/cmd/asm/internal/arch/arm64.go
@@ -75,7 +75,7 @@ func IsARM64STLXR(op obj.As) bool {
 		arm64.ASTXP, arm64.ASTXPW, arm64.ASTLXP, arm64.ASTLXPW:
 		return true
 	}
-	// atomic instructions
+	// LDADDx/SWPx/CASx atomic instructions
 	if arm64.IsAtomicInstruction(op) {
 		return true
 	}
@@ -93,6 +93,17 @@ func IsARM64TBL(op obj.As) bool {
 	return false
 }
 
+// IsARM64CASP reports whether the op (as defined by an arm64.A*
+// constant) is one of the CASP-like instructions, and its 2nd
+// destination is a register pair that require special handling.
+func IsARM64CASP(op obj.As) bool {
+	switch op {
+	case arm64.ACASPD, arm64.ACASPW:
+		return true
+	}
+	return false
+}
+
 // ARM64Suffix handles the special suffix for the ARM64.
 // It returns a boolean to indicate success; failure means
 // cond was unrecognized.
diff --git a/src/cmd/asm/internal/asm/asm.go b/src/cmd/asm/internal/asm/asm.go
index b9efa454ed..c4032759bb 100644
--- a/src/cmd/asm/internal/asm/asm.go
+++ b/src/cmd/asm/internal/asm/asm.go
@@ -637,6 +637,18 @@ func (p *Parser) asmInstruction(op obj.As, cond string, a []obj.Addr) {
 				prog.From = a[0]
 				prog.SetFrom3(a[1])
 				prog.To = a[2]
+			case arch.IsARM64CASP(op):
+				prog.From = a[0]
+				prog.To = a[1]
+				// both 1st operand and 3rd operand are (Rs, Rs+1) register pair.
+				// And the register pair must be contiguous.
+				if (a[0].Type != obj.TYPE_REGREG) || (a[2].Type != obj.TYPE_REGREG) {
+					p.errorf("invalid addressing modes for 1st or 3rd operand to %s instruction, must be register pair", op)
+					return
+				}
+				// For ARM64 CASP-like instructions, its 2nd destination operand is register pair(Rt, Rt+1) that can
+				// not fit into prog.RegTo2, so save it to the prog.RestArgs.
+				prog.SetTo2(a[2])
 			default:
 				prog.From = a[0]
 				prog.Reg = p.getRegister(prog, op, &a[1])
@@ -725,7 +737,7 @@ func (p *Parser) asmInstruction(op obj.As, cond string, a []obj.Addr) {
 		}
 		if p.arch.Family == sys.AMD64 {
 			prog.From = a[0]
-			prog.RestArgs = []obj.Addr{a[1], a[2]}
+			prog.SetRestArgs([]obj.Addr{a[1], a[2]})
 			prog.To = a[3]
 			break
 		}
@@ -808,13 +820,13 @@ func (p *Parser) asmInstruction(op obj.As, cond string, a []obj.Addr) {
 		}
 		if p.arch.Family == sys.AMD64 {
 			prog.From = a[0]
-			prog.RestArgs = []obj.Addr{a[1], a[2], a[3]}
+			prog.SetRestArgs([]obj.Addr{a[1], a[2], a[3]})
 			prog.To = a[4]
 			break
 		}
 		if p.arch.Family == sys.S390X {
 			prog.From = a[0]
-			prog.RestArgs = []obj.Addr{a[1], a[2], a[3]}
+			prog.SetRestArgs([]obj.Addr{a[1], a[2], a[3]})
 			prog.To = a[4]
 			break
 		}
diff --git a/src/cmd/asm/internal/asm/testdata/arm64.s b/src/cmd/asm/internal/asm/testdata/arm64.s
index 7943990e16..5547cf634c 100644
--- a/src/cmd/asm/internal/asm/testdata/arm64.s
+++ b/src/cmd/asm/internal/asm/testdata/arm64.s
@@ -777,6 +777,24 @@ again:
 	LDORLH	R5, (RSP), R7                        // e7336578
 	LDORLB	R5, (R6), R7                         // c7306538
 	LDORLB	R5, (RSP), R7                        // e7336538
+	CASD	R1, (R2), ZR                         // 5f7ca1c8
+	CASW	R1, (RSP), ZR                        // ff7fa188
+	CASB	ZR, (R5), R3                         // a37cbf08
+	CASH	R3, (RSP), ZR                        // ff7fa348
+	CASW	R5, (R7), R6                         // e67ca588
+	CASLD	ZR, (RSP), R8                        // e8ffbfc8
+	CASLW	R9, (R10), ZR                        // 5ffda988
+	CASAD	R7, (R11), R15                       // 6f7de7c8
+	CASAW	R10, (RSP), R19                      // f37fea88
+	CASALD	R5, (R6), R7                         // c7fce5c8
+	CASALD	R5, (RSP), R7                        // e7ffe5c8
+	CASALW	R5, (R6), R7                         // c7fce588
+	CASALW	R5, (RSP), R7                        // e7ffe588
+	CASALH	ZR, (R5), R8                         // a8fcff48
+	CASALB	R8, (R9), ZR                         // 3ffde808
+	CASPD	(R30, ZR), (RSP), (R8, R9)           // e87f3e48
+	CASPW	(R6, R7), (R8), (R4, R5)             // 047d2608
+	CASPD	(R2, R3), (R2), (R8, R9)             // 487c2248
 
 // RET
 	RET
diff --git a/src/cmd/asm/internal/asm/testdata/arm64error.s b/src/cmd/asm/internal/asm/testdata/arm64error.s
index c3a617066a..99e4d62d25 100644
--- a/src/cmd/asm/internal/asm/testdata/arm64error.s
+++ b/src/cmd/asm/internal/asm/testdata/arm64error.s
@@ -357,4 +357,8 @@ TEXT errors(SB),$0
 	VUADDW2	V9.B8, V12.S4, V14.S4                            // ERROR "operand mismatch"
 	VSLI	$64, V7.D2, V8.D2                                // ERROR "shift out of range"
 	VUSRA   $0, V7.D2, V8.D2                                 // ERROR "shift out of range"
+	CASPD	(R3, R4), (R2), (R8, R9)                         // ERROR "source register pair must start from even register"
+	CASPD	(R2, R3), (R2), (R9, R10)                        // ERROR "destination register pair must start from even register"
+	CASPD	(R2, R4), (R2), (R8, R9)                         // ERROR "source register pair must be contiguous"
+	CASPD	(R2, R3), (R2), (R8, R10)                        // ERROR "destination register pair must be contiguous"
 	RET