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| author | Paul E. Murphy <murp@ibm.com> | 2024-05-14 08:21:14 -0500 |
|---|---|---|
| committer | Paul Murphy <murp@ibm.com> | 2024-05-17 21:53:50 +0000 |
| commit | 105ac94486f243fc478c3a146d836302a95cdbbc (patch) | |
| tree | d4de8fc3290bb7e47f96186a2fda75a263bf80db /src/cmd/asm | |
| parent | b4376b8513bd0d0ace2102048c18371651ea6ae0 (diff) | |
| download | go-105ac94486f243fc478c3a146d836302a95cdbbc.tar.xz | |
cmd/asm: on PPC64, fix assembling of FCMPO opcode
The assembler should pack 3 argument usage of FCMPO similar
to other CMP-like opcodes.
Fixes #67359
Change-Id: Icfb42a67d741431a70dd880806857b4c38f42d62
Reviewed-on: https://go-review.googlesource.com/c/go/+/585640
Reviewed-by: Cherry Mui <cherryyz@google.com>
LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
Reviewed-by: Lynn Boger <laboger@linux.vnet.ibm.com>
Reviewed-by: Dmitri Shuralyov <dmitshur@google.com>
Diffstat (limited to 'src/cmd/asm')
| -rw-r--r-- | src/cmd/asm/internal/arch/ppc64.go | 2 | ||||
| -rw-r--r-- | src/cmd/asm/internal/asm/testdata/ppc64.s | 3 |
2 files changed, 4 insertions, 1 deletions
diff --git a/src/cmd/asm/internal/arch/ppc64.go b/src/cmd/asm/internal/arch/ppc64.go index 98a2bfedfd..c13652e960 100644 --- a/src/cmd/asm/internal/arch/ppc64.go +++ b/src/cmd/asm/internal/arch/ppc64.go @@ -25,7 +25,7 @@ func jumpPPC64(word string) bool { // one of the CMP instructions that require special handling. func IsPPC64CMP(op obj.As) bool { switch op { - case ppc64.ACMP, ppc64.ACMPU, ppc64.ACMPW, ppc64.ACMPWU, ppc64.AFCMPU: + case ppc64.ACMP, ppc64.ACMPU, ppc64.ACMPW, ppc64.ACMPWU, ppc64.AFCMPO, ppc64.AFCMPU: return true } return false diff --git a/src/cmd/asm/internal/asm/testdata/ppc64.s b/src/cmd/asm/internal/asm/testdata/ppc64.s index 7e8c6f9cf2..918c2e1681 100644 --- a/src/cmd/asm/internal/asm/testdata/ppc64.s +++ b/src/cmd/asm/internal/asm/testdata/ppc64.s @@ -763,7 +763,9 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$0 FCPSGN F1, F2 // fc420810 FCPSGNCC F1, F2 // fc420811 FCMPO F1, F2 // fc011040 + FCMPO F1, F2, CR0 // FCMPO F1,CR0,F2 // fc011040 FCMPU F1, F2 // fc011000 + FCMPU F1, F2, CR0 // FCMPU F1,CR0,F2 // fc011000 LVX (R3)(R4), V1 // 7c2418ce LVX (R3)(R0), V1 // 7c2018ce LVX (R3), V1 // 7c2018ce @@ -1153,6 +1155,7 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$0 MOVD XER, 4(R1) // 7fe102a6fbe10004 MOVD 4(R1), SPR(3) // ebe100047fe303a6 MOVD 4(R1), XER // ebe100047fe103a6 + OR $0, R0, R0 // 60000000 PNOP // 0700000000000000 SETB CR1,R3 // 7c640100 |