cmd/asm, cmd/internal/obj/ppc64: Add vector scalar (VSX) registers and instructions

The current implementation for Power architecture does not include the vector
scalar (VSX) registers.  This adds the 63 VSX registers and the most commonly
used instructions: load/store VSX vector/scalar, move to/from VSR, logical
operations, select, merge, splat, permute, shift, FP-FP conversion, FP-integer
conversion and integer-FP conversion.

Change-Id: I0f7572d2359fe7f3ea0124a1eb1b0bebab33649e
Reviewed-on: https://go-review.googlesource.com/30510
Reviewed-by: Lynn Boger <laboger@linux.vnet.ibm.com>
Reviewed-by: David Chase <drchase@google.com>
Run-TryBot: David Chase <drchase@google.com>
TryBot-Result: Gobot Gobot <gobot@golang.org>

4 files changed, 205 insertions, 1 deletions

diff --git a/src/cmd/asm/internal/arch/arch.go b/src/cmd/asm/internal/arch/arch.go
index 97117714f6..7766b020da 100644
--- a/src/cmd/asm/internal/arch/arch.go
+++ b/src/cmd/asm/internal/arch/arch.go
@@ -322,6 +322,9 @@ func archPPC64() *Arch {
 	for i := ppc64.REG_V0; i <= ppc64.REG_V31; i++ {
 		register[obj.Rconv(i)] = int16(i)
 	}
+	for i := ppc64.REG_VS0; i <= ppc64.REG_VS63; i++ {
+		register[obj.Rconv(i)] = int16(i)
+	}
 	for i := ppc64.REG_CR0; i <= ppc64.REG_CR7; i++ {
 		register[obj.Rconv(i)] = int16(i)
 	}
diff --git a/src/cmd/asm/internal/arch/ppc64.go b/src/cmd/asm/internal/arch/ppc64.go
index 8621bb623b..7e3d55b540 100644
--- a/src/cmd/asm/internal/arch/ppc64.go
+++ b/src/cmd/asm/internal/arch/ppc64.go
@@ -77,6 +77,10 @@ func ppc64RegisterNumber(name string, n int16) (int16, bool) {
 		if 0 <= n && n <= 7 {
 			return ppc64.REG_CR0 + n, true
 		}
+	case "VS":
+		if 0 <= n && n <= 63 {
+			return ppc64.REG_VS0 + n, true
+		}
 	case "V":
 		if 0 <= n && n <= 31 {
 			return ppc64.REG_V0 + n, true
diff --git a/src/cmd/asm/internal/asm/operand_test.go b/src/cmd/asm/internal/asm/operand_test.go
index e626589378..27d175ace6 100644
--- a/src/cmd/asm/internal/asm/operand_test.go
+++ b/src/cmd/asm/internal/asm/operand_test.go
@@ -340,6 +340,70 @@ var ppc64OperandTests = []operandTest{
 	{"6(PC)", "6(PC)"},
 	{"CR7", "CR7"},
 	{"CTR", "CTR"},
+	{"VS0", "VS0"},
+	{"VS1", "VS1"},
+	{"VS2", "VS2"},
+	{"VS3", "VS3"},
+	{"VS4", "VS4"},
+	{"VS5", "VS5"},
+	{"VS6", "VS6"},
+	{"VS7", "VS7"},
+	{"VS8", "VS8"},
+	{"VS9", "VS9"},
+	{"VS10", "VS10"},
+	{"VS11", "VS11"},
+	{"VS12", "VS12"},
+	{"VS13", "VS13"},
+	{"VS14", "VS14"},
+	{"VS15", "VS15"},
+	{"VS16", "VS16"},
+	{"VS17", "VS17"},
+	{"VS18", "VS18"},
+	{"VS19", "VS19"},
+	{"VS20", "VS20"},
+	{"VS21", "VS21"},
+	{"VS22", "VS22"},
+	{"VS23", "VS23"},
+	{"VS24", "VS24"},
+	{"VS25", "VS25"},
+	{"VS26", "VS26"},
+	{"VS27", "VS27"},
+	{"VS28", "VS28"},
+	{"VS29", "VS29"},
+	{"VS30", "VS30"},
+	{"VS31", "VS31"},
+	{"VS32", "VS32"},
+	{"VS33", "VS33"},
+	{"VS34", "VS34"},
+	{"VS35", "VS35"},
+	{"VS36", "VS36"},
+	{"VS37", "VS37"},
+	{"VS38", "VS38"},
+	{"VS39", "VS39"},
+	{"VS40", "VS40"},
+	{"VS41", "VS41"},
+	{"VS42", "VS42"},
+	{"VS43", "VS43"},
+	{"VS44", "VS44"},
+	{"VS45", "VS45"},
+	{"VS46", "VS46"},
+	{"VS47", "VS47"},
+	{"VS48", "VS48"},
+	{"VS49", "VS49"},
+	{"VS50", "VS50"},
+	{"VS51", "VS51"},
+	{"VS52", "VS52"},
+	{"VS53", "VS53"},
+	{"VS54", "VS54"},
+	{"VS55", "VS55"},
+	{"VS56", "VS56"},
+	{"VS57", "VS57"},
+	{"VS58", "VS58"},
+	{"VS59", "VS59"},
+	{"VS60", "VS60"},
+	{"VS61", "VS61"},
+	{"VS62", "VS62"},
+	{"VS63", "VS63"},
 	{"V0", "V0"},
 	{"V1", "V1"},
 	{"V2", "V2"},
diff --git a/src/cmd/asm/internal/asm/testdata/ppc64.s b/src/cmd/asm/internal/asm/testdata/ppc64.s
index a5e8bc0927..d1ebaa2962 100644
--- a/src/cmd/asm/internal/asm/testdata/ppc64.s
+++ b/src/cmd/asm/internal/asm/testdata/ppc64.s
@@ -677,7 +677,7 @@ label1:
 
 //	Described as:
 //	<instruction type>, <instruction format>
-//	<golang asm operand order> produces
+//	<go asm operand order> produces
 //	<Power ISA operand order>
 
 //	Vector load, VX-form
@@ -880,6 +880,139 @@ label1:
 	VSHASIGMAW    $15, V1, $1, V0
 	VSHASIGMAD    $15, V1, $1, V0
 
+//	VSX instructions
+//	Described as:
+//	<instruction type>, <instruction format>
+//	<go asm operand order> produces
+//	<Power ISA operand order>
+
+//	VSX load, XX1-form
+//	<MNEMONIC> (RB)(RA*1),XT produces
+//	<mnemonic> XT,RA,RB
+	LXVD2X	    (R1)(R2*1), VS0
+	LXVDSX	    (R1)(R2*1), VS0
+	LXVW4X	    (R1)(R2*1), VS0
+	LXSDX	    (R1)(R2*1), VS0
+	LXSIWAX	    (R1)(R2*1), VS0
+	LXSIWZX	    (R1)(R2*1), VS0
+
+//	VSX store, XX1-form
+//	<MNEMONIC> XS,(RB)(RA*1) produces
+//	<mnemonic> XS,RA,RB
+	STXVD2X	    VS63, (R1)(R2*1)
+	STXVW4X	    VS63, (R1)(R2*1)
+	STXSDX	    VS63, (R1)(R2*1)
+	STXSIWX	    VS63, (R1)(R2*1)
+
+//	VSX move from VSR, XX1-form
+//	<MNEMONIC> XS,RA produces
+//	<mnemonic> RA,XS
+	MFVSRD	    VS0, R1
+	MFVSRWZ	    VS33, R1
+
+//	VSX move to VSR, XX1-form
+//	<MNEMONIC> RA,XT produces
+//	<mnemonic> XT,RA
+	MTVSRD	    R1, VS0
+	MTVSRWA	    R1, VS31
+	MTVSRWZ	    R1, VS63
+
+//	VSX AND, XX3-form
+//	<MNEMONIC> XA,XB,XT produces
+//	<mnemonic> XT,XA,XB
+	XXLANDQ	    VS0,VS1,VS32
+	XXLANDC	    VS0,VS1,VS32
+	XXLEQV	    VS0,VS1,VS32
+	XXLNAND	    VS0,VS1,VS32
+
+//	VSX OR, XX3-form
+//	<MNEMONIC> XA,XB,XT produces
+//	<mnemonic> XT,XA,XB
+	XXLORC	    VS0,VS1,VS32
+	XXLNOR	    VS0,VS1,VS32
+	XXLORQ	    VS0,VS1,VS32
+	XXLXOR	    VS0,VS1,VS32
+
+//	VSX select, XX4-form
+//	<MNEMONIC> XA,XB,XC,XT produces
+//	<mnemonic> XT,XA,XB,XC
+	XXSEL	    VS0,VS1,VS3,VS32
+
+//	VSX merge, XX3-form
+//	<MNEMONIC> XA,XB,XT produces
+//	<mnemonic> XT,XA,XB
+	XXMRGHW	    VS0,VS1,VS32
+	XXMRGLW	    VS0,VS1,VS32
+
+//	VSX splat, XX2-form
+//	<MNEMONIC> XB,UIM,XT produces
+//	<mnemonic> XT,XB,UIM
+	XXSPLTW	    VS0,$3,VS32
+
+//	VSX permute, XX3-form
+//	<MNEMONIC> XA,XB,DM,XT produces
+//	<mnemonic> XT,XA,XB,DM
+	XXPERMDI    VS0,VS1,$3,VS32
+
+//	VSX shift, XX3-form
+//	<MNEMONIC> XA,XB,SHW,XT produces
+//	<mnemonic> XT,XA,XB,SHW
+	XXSLDWI	    VS0,VS1,$3,VS32
+
+//	VSX scalar FP-FP conversion, XX2-form
+//	<MNEMONIC> XB,XT produces
+//	<mnemonic> XT,XB
+	XSCVDPSP    VS0,VS32
+	XSCVSPDP    VS0,VS32
+	XSCVDPSPN   VS0,VS32
+	XSCVSPDPN   VS0,VS32
+
+//	VSX vector FP-FP conversion, XX2-form
+//	<MNEMONIC> XB,XT produces
+//	<mnemonic> XT,XB
+	XVCVDPSP    VS0,VS32
+	XVCVSPDP    VS0,VS32
+
+//	VSX scalar FP-integer conversion, XX2-form
+//	<MNEMONIC> XB,XT produces
+//	<mnemonic> XT,XB
+	XSCVDPSXDS  VS0,VS32
+	XSCVDPSXWS  VS0,VS32
+	XSCVDPUXDS  VS0,VS32
+	XSCVDPUXWS  VS0,VS32
+
+//	VSX scalar integer-FP conversion, XX2-form
+//	<MNEMONIC> XB,XT produces
+//	<mnemonic> XT,XB
+	XSCVSXDDP   VS0,VS32
+	XSCVUXDDP   VS0,VS32
+	XSCVSXDSP   VS0,VS32
+	XSCVUXDSP   VS0,VS32
+
+//	VSX vector FP-integer conversion, XX2-form
+//	<MNEMONIC> XB,XT produces
+//	<mnemonic> XT,XB
+	XVCVDPSXDS  VS0,VS32
+	XVCVDPSXWS  VS0,VS32
+	XVCVDPUXDS  VS0,VS32
+	XVCVDPUXWS  VS0,VS32
+	XVCVSPSXDS  VS0,VS32
+	XVCVSPSXWS  VS0,VS32
+	XVCVSPUXDS  VS0,VS32
+	XVCVSPUXWS  VS0,VS32
+
+//	VSX scalar integer-FP conversion, XX2-form
+//	<MNEMONIC> XB,XT produces
+//	<mnemonic> XT,XB
+	XVCVSXDDP   VS0,VS32
+	XVCVSXWDP   VS0,VS32
+	XVCVUXDDP   VS0,VS32
+	XVCVUXWDP   VS0,VS32
+	XVCVSXDSP   VS0,VS32
+	XVCVSXWSP   VS0,VS32
+	XVCVUXDSP   VS0,VS32
+	XVCVUXWSP   VS0,VS32
+
 //
 // NOP
 //