diff options
| author | Alexander Musman <alexander.musman@gmail.com> | 2025-11-10 19:26:35 +0300 |
|---|---|---|
| committer | David Chase <drchase@google.com> | 2026-04-08 03:50:26 -0700 |
| commit | f91403c2a0fd3fc4367d901bd6f238948c49c265 (patch) | |
| tree | 207939037bbd724183cb8528e62430c17340e979 /src/cmd/asm/internal | |
| parent | 497ec0d4e1763ffd167577cc2ac5fdb82b99ad82 (diff) | |
| download | go-f91403c2a0fd3fc4367d901bd6f238948c49c265.tar.xz | |
cmd/internal/obj: refactor arm64 ASIMD instruction encoding
Refactor arm64 ASIMD opcodes to use common helper routines named
after their instruction classes from the arm64 XML specification.
Add helper routines like ASIMDSAME for instructions with encoding
class "asimdsame" in arm64 encodingindex.xml. Helper arguments
follow the bitfield order in the speficication tables.
For example, the CMEQ instruction entry:
<tr class="instructiontable" encname="CMEQ_asimdsame_only"...>
<td bitwidth="1" class="bitfield">1</td>
<td bitwidth="2" class="bitfield"></td>
<td bitwidth="5" class="bitfield">10001</td>
<td class="iformname" iformid="CMEQ_advsimd_reg">CMEQ (register)</td>
<td class="enctags">Vector</td>
</tr>
Now corresponds to ASIMDSAME(1, 0, 0x11), where each argument
matches the correspoding bitfield value in the table.
Change-Id: I024f3eba552906a865841bc1a296f14e3fca73f5
Reviewed-on: https://go-review.googlesource.com/c/go/+/719280
Reviewed-by: Dmitri Shuralyov <dmitshur@google.com>
LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
Reviewed-by: Cherry Mui <cherryyz@google.com>
Diffstat (limited to 'src/cmd/asm/internal')
| -rw-r--r-- | src/cmd/asm/internal/asm/testdata/arm64.s | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/cmd/asm/internal/asm/testdata/arm64.s b/src/cmd/asm/internal/asm/testdata/arm64.s index edc6a8aafd..9c35b4b248 100644 --- a/src/cmd/asm/internal/asm/testdata/arm64.s +++ b/src/cmd/asm/internal/asm/testdata/arm64.s @@ -315,6 +315,8 @@ TEXT foo(SB), DUPOK|NOSPLIT, $-8 VREV32 V5.B16, V5.B16 // a508206e VREV64 V2.S2, V3.S2 // 4308a00e VREV64 V2.S4, V3.S4 // 4308a04e + VREV16 V7.B16, V5.B16 // e518204e + VREV16 V7.B8, V5.B8 // e518200e // logical ops // |