diff options
| author | Joel Sing <joel@sing.id.au> | 2019-09-08 04:11:07 +1000 |
|---|---|---|
| committer | Joel Sing <joel@sing.id.au> | 2019-09-17 04:37:46 +0000 |
| commit | c3c53661ba8823ea7a051110aebbdea2650c25d0 (patch) | |
| tree | 463647e8fd18a3149703c6835ae12d67275048f8 /src/cmd/asm/internal | |
| parent | 606fa2db7a7cd80292fca7aab6c1787fa274e52b (diff) | |
| download | go-c3c53661ba8823ea7a051110aebbdea2650c25d0.tar.xz | |
cmd/asm,cmd/internal/obj/riscv: implement integer computational instructions
Add support for assembling integer computational instructions.
Based on the riscv-go port.
Updates #27532
Change-Id: Ibf02649eebd65ce96002a9ca0624266d96def2cd
Reviewed-on: https://go-review.googlesource.com/c/go/+/195079
Run-TryBot: Joel Sing <joel@sing.id.au>
TryBot-Result: Gobot Gobot <gobot@golang.org>
Reviewed-by: Cherry Zhang <cherryyz@google.com>
Diffstat (limited to 'src/cmd/asm/internal')
| -rw-r--r-- | src/cmd/asm/internal/asm/asm.go | 4 | ||||
| -rw-r--r-- | src/cmd/asm/internal/asm/testdata/riscvenc.s | 68 |
2 files changed, 70 insertions, 2 deletions
diff --git a/src/cmd/asm/internal/asm/asm.go b/src/cmd/asm/internal/asm/asm.go index d83cfb2284..c6f07832a7 100644 --- a/src/cmd/asm/internal/asm/asm.go +++ b/src/cmd/asm/internal/asm/asm.go @@ -417,7 +417,7 @@ func (p *Parser) asmJump(op obj.As, cond string, a []obj.Addr) { prog.Reg = reg break } - if p.arch.Family == sys.MIPS || p.arch.Family == sys.MIPS64 { + if p.arch.Family == sys.MIPS || p.arch.Family == sys.MIPS64 || p.arch.Family == sys.RISCV64 { // 3-operand jumps. // First two must be registers target = &a[2] @@ -579,7 +579,7 @@ func (p *Parser) asmInstruction(op obj.As, cond string, a []obj.Addr) { prog.To = a[1] case 3: switch p.arch.Family { - case sys.MIPS, sys.MIPS64: + case sys.MIPS, sys.MIPS64, sys.RISCV64: prog.From = a[0] prog.Reg = p.getRegister(prog, op, &a[1]) prog.To = a[2] diff --git a/src/cmd/asm/internal/asm/testdata/riscvenc.s b/src/cmd/asm/internal/asm/testdata/riscvenc.s index eea5738f2c..c05a05ea33 100644 --- a/src/cmd/asm/internal/asm/testdata/riscvenc.s +++ b/src/cmd/asm/internal/asm/testdata/riscvenc.s @@ -9,3 +9,71 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$0 // Arbitrary bytes (entered in little-endian mode) WORD $0x12345678 // WORD $305419896 // 78563412 WORD $0x9abcdef0 // WORD $2596069104 // f0debc9a + + // Unprivileged ISA + + // 2.4: Integer Computational Instructions + + ADDI $2047, X5, X6 // 1383f27f + ADDI $-2048, X5, X6 // 13830280 + ADDI $2047, X5 // 9382f27f + ADDI $-2048, X5 // 93820280 + + SLTI $55, X5, X7 // 93a37203 + SLTIU $55, X5, X7 // 93b37203 + + ANDI $1, X5, X6 // 13f31200 + ANDI $1, X5 // 93f21200 + ORI $1, X5, X6 // 13e31200 + ORI $1, X5 // 93e21200 + XORI $1, X5, X6 // 13c31200 + XORI $1, X5 // 93c21200 + + SLLI $1, X5, X6 // 13931200 + SLLI $1, X5 // 93921200 + SRLI $1, X5, X6 // 13d31200 + SRLI $1, X5 // 93d21200 + SRAI $1, X5, X6 // 13d31240 + SRAI $1, X5 // 93d21240 + + ADD X6, X5, X7 // b3836200 + ADD X5, X6 // 33035300 + ADD $2047, X5, X6 // 1383f27f + ADD $-2048, X5, X6 // 13830280 + ADD $2047, X5 // 9382f27f + ADD $-2048, X5 // 93820280 + + SLT X6, X5, X7 // b3a36200 + SLT $55, X5, X7 // 93a37203 + SLTU X6, X5, X7 // b3b36200 + SLTU $55, X5, X7 // 93b37203 + + AND X6, X5, X7 // b3f36200 + AND X5, X6 // 33735300 + AND $1, X5, X6 // 13f31200 + AND $1, X5 // 93f21200 + OR X6, X5, X7 // b3e36200 + OR X5, X6 // 33635300 + OR $1, X5, X6 // 13e31200 + OR $1, X5 // 93e21200 + XOR X6, X5, X7 // b3c36200 + XOR X5, X6 // 33435300 + XOR $1, X5, X6 // 13c31200 + XOR $1, X5 // 93c21200 + + SLL X6, X5, X7 // b3936200 + SLL X5, X6 // 33135300 + SLL $1, X5, X6 // 13931200 + SLL $1, X5 // 93921200 + SRL X6, X5, X7 // b3d36200 + SRL X5, X6 // 33535300 + SRL $1, X5, X6 // 13d31200 + SRL $1, X5 // 93d21200 + + SUB X6, X5, X7 // b3836240 + SUB X5, X6 // 33035340 + + SRA X6, X5, X7 // b3d36240 + SRA X5, X6 // 33535340 + SRA $1, X5, X6 // 13d31240 + SRA $1, X5 // 93d21240 |