diff options
| author | eric fang <eric.fang@arm.com> | 2022-05-05 07:46:05 +0000 |
|---|---|---|
| committer | Eric Fang <eric.fang@arm.com> | 2022-08-23 06:11:32 +0000 |
| commit | 9f0f87c806b7a11b2cb3ebcd02eac57ee389c43a (patch) | |
| tree | 863f4ed6c3f96c332dc96bff0ccb23314b9451fe /src/cmd/asm/internal | |
| parent | 0a52d80666ddaa557cec17ad9166e2514b0bb6d4 (diff) | |
| download | go-9f0f87c806b7a11b2cb3ebcd02eac57ee389c43a.tar.xz | |
cmd/internal/obj/arm64: remove the transition from $0 to ZR
Previously we convert $0 to the ZR register for some reasons, which causes
two problems:
1. Confusion, the special case of the ZR register needs to be considered
when dealing with constants. For encoding, some places we encode ZR, and
some places we encode $0, although we have converted $0 to ZR.
2. Unexpected instruction format. All instructions that support ZR register
operands can be replaced by $0.
This patch removes this conversion. Note that this patch may cause previously
unintendedly supported instruction formats to no longer be supported.
Change-Id: I3d8d2c06711b7614a38191397da7776417f1861c
Reviewed-on: https://go-review.googlesource.com/c/go/+/404316
Reviewed-by: David Chase <drchase@google.com>
Run-TryBot: Eric Fang <eric.fang@arm.com>
Reviewed-by: Cherry Mui <cherryyz@google.com>
TryBot-Result: Gopher Robot <gobot@golang.org>
Diffstat (limited to 'src/cmd/asm/internal')
| -rw-r--r-- | src/cmd/asm/internal/asm/testdata/arm64.s | 19 | ||||
| -rw-r--r-- | src/cmd/asm/internal/asm/testdata/arm64enc.s | 2 |
2 files changed, 19 insertions, 2 deletions
diff --git a/src/cmd/asm/internal/asm/testdata/arm64.s b/src/cmd/asm/internal/asm/testdata/arm64.s index edd7a98279..4d04be52e4 100644 --- a/src/cmd/asm/internal/asm/testdata/arm64.s +++ b/src/cmd/asm/internal/asm/testdata/arm64.s @@ -95,6 +95,14 @@ TEXT foo(SB), DUPOK|NOSPLIT, $-8 // CLS CLSW R1, R2 CLS R1, R2 + SBC $0, R1 // 21001fda + SBCW $0, R1 // 21001f5a + SBCS $0, R1 // 21001ffa + SBCSW $0, R1 // 21001f7a + ADC $0, R1 // 21001f9a + ADCW $0, R1 // 21001f1a + ADCS $0, R1 // 21001fba + ADCSW $0, R1 // 21001f3a // fp/simd instructions. VADDP V1.B16, V2.B16, V3.B16 // 43bc214e @@ -386,7 +394,7 @@ TEXT foo(SB), DUPOK|NOSPLIT, $-8 MOVD $0x11110000, R1 // MOVD $286326784, R1 // 2122a2d2 MOVD $0xaaaa0000aaaa1111, R1 // MOVD $-6149102338357718767, R1 // 212282d24155b5f24155f5f2 MOVD $0x1111ffff1111aaaa, R1 // MOVD $1230045644216969898, R1 // a1aa8a922122a2f22122e2f2 - MOVD $0, R1 // 010080d2 + MOVD $0, R1 // e1031faa MOVD $-1, R1 // 01008092 MOVD $0x210000, R0 // MOVD $2162688, R0 // 2004a0d2 MOVD $0xffffffffffffaaaa, R1 // MOVD $-21846, R1 // a1aa8a92 @@ -496,6 +504,15 @@ TEXT foo(SB), DUPOK|NOSPLIT, $-8 FMOVQ.P 11(R10), F13 // 4db5c03c FMOVQ.W 11(R20), F15 // 8fbec03c +// storing $0 to memory, $0 will be replaced with ZR. + MOVD $0, (R1) // 3f0000f9 + MOVW $0, (R1) // 3f0000b9 + MOVWU $0, (R1) // 3f0000b9 + MOVH $0, (R1) // 3f000079 + MOVHU $0, (R1) // 3f000079 + MOVB $0, (R1) // 3f000039 + MOVBU $0, (R1) // 3f000039 + // small offset fits into instructions MOVB R1, 1(R2) // 41040039 MOVH R1, 1(R2) // 41100078 diff --git a/src/cmd/asm/internal/asm/testdata/arm64enc.s b/src/cmd/asm/internal/asm/testdata/arm64enc.s index eff48ae8e7..0ae00d2ac9 100644 --- a/src/cmd/asm/internal/asm/testdata/arm64enc.s +++ b/src/cmd/asm/internal/asm/testdata/arm64enc.s @@ -263,7 +263,7 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$-8 MOVKW $(3905<<0), R21 // MOVKW $3905, R21 // 35e88172 MOVKW $(3905<<16), R21 // MOVKW $255918080, R21 // 35e8a172 MOVK $(3905<<32), R21 // MOVK $16771847290880, R21 // 35e8c1f2 - MOVD $0, R5 // 050080d2 + MOVD $0, R5 // e5031faa MSR $1, SPSel // bf4100d5 MSR $9, DAIFSet // df4903d5 MSR $6, DAIFClr // ff4603d5 |