cmd/internal/obj/riscv: add support for vector mask instructions

Add support for vector mask instructions to the RISC-V assembler.
These allow manipulation of vector masks and include mask register
logical instructions, population count and find-first bit set
instructions.

Change-Id: I3ab3aa0f918338aee9b37ac5a2b2fdc407875072
Reviewed-on: https://go-review.googlesource.com/c/go/+/646779
Reviewed-by: Carlos Amedee <carlos@golang.org>
Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com>
LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
Reviewed-by: Mark Ryan <markdryan@rivosinc.com>
Reviewed-by: Junyang Shao <shaojunyang@google.com>

3 files changed, 53 insertions, 0 deletions

diff --git a/src/cmd/asm/internal/asm/testdata/riscv64.s b/src/cmd/asm/internal/asm/testdata/riscv64.s
index 687f98d072..c5eef10b7c 100644
--- a/src/cmd/asm/internal/asm/testdata/riscv64.s
+++ b/src/cmd/asm/internal/asm/testdata/riscv64.s
@@ -1201,6 +1201,34 @@ start:
 	VFWREDUSUMVS	V1, V2, V3			// d79120c6
 	VFWREDUSUMVS	V1, V2, V0, V3			// d79120c4
 
+	// 31.15: Vector Mask Instructions
+	VMANDMM		V1, V2, V3			// d7a12066
+	VMNANDMM	V1, V2, V3			// d7a12076
+	VMANDNMM	V1, V2, V3			// d7a12062
+	VMXORMM		V1, V2, V3			// d7a1206e
+	VMORMM		V1, V2, V3			// d7a1206a
+	VMNORMM		V1, V2, V3			// d7a1207a
+	VMORNMM		V1, V2, V3			// d7a12072
+	VMXNORMM	V1, V2, V3			// d7a1207e
+	VMMVM		V2, V3				// d7212166
+	VMCLRM		V3				// d7a1316e
+	VMSETM		V3				// d7a1317e
+	VMNOTM		V2, V3				// d7212176
+	VCPOPM		V2, X10				// 57252842
+	VCPOPM		V2, V0, X10			// 57252840
+	VFIRSTM		V2, X10				// 57a52842
+	VFIRSTM		V2, V0, X10			// 57a52840
+	VMSBFM		V2, V3				// d7a12052
+	VMSBFM		V2, V0, V3			// d7a12050
+	VMSIFM		V2, V3				// d7a12152
+	VMSIFM		V2, V0, V3			// d7a12150
+	VMSOFM		V2, V3				// d7212152
+	VMSOFM		V2, V0, V3			// d7212150
+	VIOTAM		V2, V3				// d7212852
+	VIOTAM		V2, V0, V3			// d7212850
+	VIDV		V3				// d7a10852
+	VIDV		V0, V3				// d7a10850
+
 	//
 	// Privileged ISA
 	//
diff --git a/src/cmd/asm/internal/asm/testdata/riscv64error.s b/src/cmd/asm/internal/asm/testdata/riscv64error.s
index 3a4bb1c761..b076cf50e0 100644
--- a/src/cmd/asm/internal/asm/testdata/riscv64error.s
+++ b/src/cmd/asm/internal/asm/testdata/riscv64error.s
@@ -362,5 +362,11 @@ TEXT errors(SB),$0
 	VFREDMAXVS	V1, V2, V4, V3			// ERROR "invalid vector mask register"
 	VFREDMINVS	V1, V2, V4, V3			// ERROR "invalid vector mask register"
 	VFWREDOSUMVS	V1, V2, V4, V3			// ERROR "invalid vector mask register"
+	VCPOPM		V2, V4, X10			// ERROR "invalid vector mask register"
+	VFIRSTM		V2, V4, X10			// ERROR "invalid vector mask register"
+	VMSBFM		V2, V4, V3			// ERROR "invalid vector mask register"
+	VMSIFM		V2, V4, V3			// ERROR "invalid vector mask register"
+	VMSOFM		V2, V4, V3			// ERROR "invalid vector mask register"
+	VIOTAM		V2, V4, V3			// ERROR "invalid vector mask register"
 
 	RET
diff --git a/src/cmd/asm/internal/asm/testdata/riscv64validation.s b/src/cmd/asm/internal/asm/testdata/riscv64validation.s
index adb10823d7..8b0349584f 100644
--- a/src/cmd/asm/internal/asm/testdata/riscv64validation.s
+++ b/src/cmd/asm/internal/asm/testdata/riscv64validation.s
@@ -380,5 +380,24 @@ TEXT validation(SB),$0
 	VFREDMINVS	X10, V2, V3			// ERROR "expected vector register in vs1 position"
 	VFWREDOSUMVS	X10, V2, V3			// ERROR "expected vector register in vs1 position"
 	VFWREDUSUMVS	X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VMANDMM		X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VMNANDMM	X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VMANDNMM	X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VMXORMM		X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VMORMM		X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VMNORMM		X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VMORNMM		X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VMXNORMM	X10, V2, V3			// ERROR "expected vector register in vs1 position"
+	VMMVM		V3, X10				// ERROR "expected vector register in vd position"
+	VMNOTM		V3, X10				// ERROR "expected vector register in vd position"
+	VCPOPM		V2, V1				// ERROR "expected integer register in rd position"
+	VCPOPM		X11, X10			// ERROR "expected vector register in vs2 position"
+	VFIRSTM		V2, V1				// ERROR "expected integer register in rd position"
+	VFIRSTM		X11, X10			// ERROR "expected vector register in vs2 position"
+	VMSBFM		X10, V3				// ERROR "expected vector register in vs2 position"
+	VMSIFM		X10, V3				// ERROR "expected vector register in vs2 position"
+	VMSOFM		X10, V3				// ERROR "expected vector register in vs2 position"
+	VIOTAM		X10, V3				// ERROR "expected vector register in vs2 position"
+	VIDV		X10				// ERROR "expected vector register in vd position"
 
 	RET