cmd/asm, cmd/internal/obj/arm64: support special operands in SVE

This CL is generated by CL 764980.

This CL supports these new special constants:
<prfop>, which Go already support (prefetch modifier)
<vl>, which include VLx2 and VLx4, which is the vector length specifier.

Change-Id: I831f306a816493c08f3c22786e5360f2a37acf6c
Reviewed-on: https://go-review.googlesource.com/c/go/+/765000
LUCI-TryBot-Result: golang-scoped@luci-project-accounts.iam.gserviceaccount.com <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
Reviewed-by: David Chase <drchase@google.com>

9 files changed, 639 insertions, 132 deletions

diff --git a/src/cmd/asm/internal/asm/testdata/arm64sveenc.s b/src/cmd/asm/internal/asm/testdata/arm64sveenc.s
index 53e0a26931..6a0dd9838a 100644
--- a/src/cmd/asm/internal/asm/testdata/arm64sveenc.s
+++ b/src/cmd/asm/internal/asm/testdata/arm64sveenc.s
@@ -1121,4 +1121,29 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$-8
 	ZSTNT1W (R6<<2)(R14), P4, [Z13.S]                 // cd7106e5
 	ZSTNT1W (R6)(Z7.S), P4, [Z13.S]                   // ed3046e5
 	ZSTNT1W (R6)(Z7.D), P4, [Z13.D]                   // ed3006e5
+	PCNTP VLx2, PN13.D, R5                            // a583e025
+	PPRFB (R8)(RSP), P3, PSTL3KEEP                    // eccf0884
+	PPRFD (R8<<3)(RSP), P3, PSTL3KEEP                 // eccf8885
+	PPRFH (R8<<1)(RSP), P3, PSTL3KEEP                 // eccf8884
+	PPRFW (R8<<2)(RSP), P3, PSTL3KEEP                 // eccf0885
+	PWHILEGE VLx4, R21, R9, PN12.H                    // 34617525
+	PWHILEGT VLx4, R21, R9, PN12.H                    // 3c617525
+	PWHILEHI VLx4, R21, R9, PN12.H                    // 3c697525
+	PWHILEHS VLx4, R21, R9, PN12.H                    // 34697525
+	PWHILELE VLx4, R21, R9, PN12.H                    // 3c657525
+	PWHILELO VLx4, R21, R9, PN12.H                    // 346d7525
+	PWHILELS VLx4, R21, R9, PN12.H                    // 3c6d7525
+	PWHILELT VLx4, R21, R9, PN12.H                    // 34657525
+	ZPRFB (Z6.S.SXTW)(R14), P2, PLDL1STRM             // c1096684
+	ZPRFB (Z6.D.SXTW)(R14), P2, PLDL1STRM             // c10966c4
+	ZPRFB (Z8.D)(RSP), P3, PSTL3KEEP                  // ec8f68c4
+	ZPRFD (Z6.S.SXTW<<3)(R14), P2, PLDL1STRM          // c1696684
+	ZPRFD (Z6.D.SXTW<<3)(R14), P2, PLDL1STRM          // c16966c4
+	ZPRFD (Z8.D<<3)(RSP), P3, PSTL3KEEP               // ecef68c4
+	ZPRFH (Z6.S.SXTW<<1)(R14), P2, PLDL1STRM          // c1296684
+	ZPRFH (Z6.D.SXTW<<1)(R14), P2, PLDL1STRM          // c12966c4
+	ZPRFH (Z8.D<<1)(RSP), P3, PSTL3KEEP               // ecaf68c4
+	ZPRFW (Z6.S.SXTW<<2)(R14), P2, PLDL1STRM          // c1496684
+	ZPRFW (Z6.D.SXTW<<2)(R14), P2, PLDL1STRM          // c14966c4
+	ZPRFW (Z8.D<<2)(RSP), P3, PSTL3KEEP               // eccf68c4
 	RET
diff --git a/src/cmd/asm/internal/asm/testdata/arm64sveerror.s b/src/cmd/asm/internal/asm/testdata/arm64sveerror.s
index 848cab0f59..7fb955dcb0 100644
--- a/src/cmd/asm/internal/asm/testdata/arm64sveerror.s
+++ b/src/cmd/asm/internal/asm/testdata/arm64sveerror.s
@@ -1120,4 +1120,29 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$-8
 	ZSTNT1W (R27<<2)(RSP), P13.Z, [Z11.B]             // ERROR "illegal combination from SVE"
 	ZSTNT1W (R27)(Z1.S), P13.Z, [Z11.B]               // ERROR "illegal combination from SVE"
 	ZSTNT1W (R27)(Z1.D), P13.Z, [Z11.B]               // ERROR "illegal combination from SVE"
+	PCNTP VLx4, PN7.Q, R25                            // ERROR "illegal combination from SVE"
+	PPRFB (R27)(RSP), P13.Z, PSTL3STRM                // ERROR "illegal combination from SVE"
+	PPRFD (R27<<3)(RSP), P13.Z, PSTL3STRM             // ERROR "illegal combination from SVE"
+	PPRFH (R27<<1)(RSP), P13.Z, PSTL3STRM             // ERROR "illegal combination from SVE"
+	PPRFW (R27<<2)(RSP), P13.Z, PSTL3STRM             // ERROR "illegal combination from SVE"
+	PWHILEGE VLx4, R27, ZR, PN7.Q                     // ERROR "illegal combination from SVE"
+	PWHILEGT VLx4, R27, ZR, PN7.Q                     // ERROR "illegal combination from SVE"
+	PWHILEHI VLx4, R27, ZR, PN7.Q                     // ERROR "illegal combination from SVE"
+	PWHILEHS VLx4, R27, ZR, PN7.Q                     // ERROR "illegal combination from SVE"
+	PWHILELE VLx4, R27, ZR, PN7.Q                     // ERROR "illegal combination from SVE"
+	PWHILELO VLx4, R27, ZR, PN7.Q                     // ERROR "illegal combination from SVE"
+	PWHILELS VLx4, R27, ZR, PN7.Q                     // ERROR "illegal combination from SVE"
+	PWHILELT VLx4, R27, ZR, PN7.Q                     // ERROR "illegal combination from SVE"
+	ZPRFB (Z27.S.UXTW)(RSP), P7.Z, PLDL1KEEP          // ERROR "illegal combination from SVE"
+	ZPRFB (Z27.D.UXTW)(RSP), P7.Z, PLDL1KEEP          // ERROR "illegal combination from SVE"
+	ZPRFB (Z27.D)(RSP), P13.Z, PSTL3STRM              // ERROR "illegal combination from SVE"
+	ZPRFD (Z27.S.UXTW<<3)(RSP), P7.Z, PLDL1KEEP       // ERROR "illegal combination from SVE"
+	ZPRFD (Z27.D.UXTW<<3)(RSP), P7.Z, PLDL1KEEP       // ERROR "illegal combination from SVE"
+	ZPRFD (Z27.D<<3)(RSP), P13.Z, PSTL3STRM           // ERROR "illegal combination from SVE"
+	ZPRFH (Z27.S.UXTW<<1)(RSP), P7.Z, PLDL1KEEP       // ERROR "illegal combination from SVE"
+	ZPRFH (Z27.D.UXTW<<1)(RSP), P7.Z, PLDL1KEEP       // ERROR "illegal combination from SVE"
+	ZPRFH (Z27.D<<1)(RSP), P13.Z, PSTL3STRM           // ERROR "illegal combination from SVE"
+	ZPRFW (Z27.S.UXTW<<2)(RSP), P7.Z, PLDL1KEEP       // ERROR "illegal combination from SVE"
+	ZPRFW (Z27.D.UXTW<<2)(RSP), P7.Z, PLDL1KEEP       // ERROR "illegal combination from SVE"
+	ZPRFW (Z27.D<<2)(RSP), P13.Z, PSTL3STRM           // ERROR "illegal combination from SVE"
 	RET
diff --git a/src/cmd/internal/obj/arm64/a.out.go b/src/cmd/internal/obj/arm64/a.out.go
index d259a651d5..db571507c9 100644
--- a/src/cmd/internal/obj/arm64/a.out.go
+++ b/src/cmd/internal/obj/arm64/a.out.go
@@ -1329,6 +1329,10 @@ const (
 	SPOP_PSTL3KEEP
 	SPOP_PSTL3STRM
 
+	// VL
+	SPOP_VLx2
+	SPOP_VLx4
+
 	// TLBI
 	SPOP_VMALLE1IS
 	SPOP_VAE1IS
diff --git a/src/cmd/internal/obj/arm64/anames_gen.go b/src/cmd/internal/obj/arm64/anames_gen.go
index 87620b1e10..28bc47c02d 100644
--- a/src/cmd/internal/obj/arm64/anames_gen.go
+++ b/src/cmd/internal/obj/arm64/anames_gen.go
@@ -43,6 +43,10 @@ var sveAnames = []string{
 	"PPFALSE",
 	"PPFIRST",
 	"PPNEXT",
+	"PPRFB",
+	"PPRFD",
+	"PPRFH",
+	"PPRFW",
 	"PPTEST",
 	"PPTRUE",
 	"PPUNPKHI",
@@ -403,6 +407,10 @@ var sveAnames = []string{
 	"ZPMUL",
 	"ZPMULLB",
 	"ZPMULLT",
+	"ZPRFB",
+	"ZPRFD",
+	"ZPRFH",
+	"ZPRFW",
 	"ZRADDHNB",
 	"ZRADDHNT",
 	"ZRAX1",
diff --git a/src/cmd/internal/obj/arm64/encoding_gen.go b/src/cmd/internal/obj/arm64/encoding_gen.go
index dbd4b67cf9..cb3fba2587 100644
--- a/src/cmd/internal/obj/arm64/encoding_gen.go
+++ b/src/cmd/internal/obj/arm64/encoding_gen.go
@@ -78,11 +78,13 @@ const (
 	enc_imm7
 	enc_imm8
 	enc_msz
+	enc_prfop
 	enc_rot
 	enc_size
 	enc_size0
 	enc_sz
 	enc_tsz
+	enc_vl
 	enc_xs
 )
 
@@ -1729,6 +1731,17 @@ func encodePn59v2(v uint32) (uint32, bool) {
 	return v << 5, true
 }
 
+// encodePNn59 is the implementation of the following encoding logic:
+// Is the name of the source scalable predicate register, with predicate-as-counter encoding, encoded in the "PNn" field.
+// bit range mappings:
+// PNn: [5:9)
+func encodePNn59(v uint32) (uint32, bool) {
+	if v > 15 {
+		return (v - 16) << 5, true
+	}
+	return 0, false
+}
+
 // encodeZm1621V1 is the implementation of the following encoding logic:
 // Is the name of the source scalable vector register, encoded in the "Zm" field.
 // bit range mappings:
@@ -2040,6 +2053,55 @@ func encodePredQualM45(v uint32) (uint32, bool) {
 	return 0, false
 }
 
+// encodePrfop04 is the implementation of the following encoding logic:
+// Is the prefetch operation specifier,
+// prfop	<prfop>
+// 0000	PLDL1KEEP
+// 0001	PLDL1STRM
+// 0010	PLDL2KEEP
+// 0011	PLDL2STRM
+// 0100	PLDL3KEEP
+// 0101	PLDL3STRM
+// x11x	#uimm4
+// 1000	PSTL1KEEP
+// 1001	PSTL1STRM
+// 1010	PSTL2KEEP
+// 1011	PSTL2STRM
+// 1100	PSTL3KEEP
+// 1101	PSTL3STRM
+// bit range mappings:
+// prfop: [0:4)
+func encodePrfop04(v uint32) (uint32, bool) {
+	switch SpecialOperand(v) {
+	case SPOP_PLDL1KEEP:
+		return 0, true
+	case SPOP_PLDL1STRM:
+		return 1, true
+	case SPOP_PLDL2KEEP:
+		return 2, true
+	case SPOP_PLDL2STRM:
+		return 3, true
+	case SPOP_PLDL3KEEP:
+		return 4, true
+	case SPOP_PLDL3STRM:
+		return 5, true
+	case SPOP_PSTL1KEEP:
+		return 8, true
+	case SPOP_PSTL1STRM:
+		return 9, true
+	case SPOP_PSTL2KEEP:
+		return 10, true
+	case SPOP_PSTL2STRM:
+		return 11, true
+	case SPOP_PSTL3KEEP:
+		return 12, true
+	case SPOP_PSTL3STRM:
+		return 13, true
+	default:
+		return 0, false
+	}
+}
+
 // encodeImm5bSigned_1621 is the implementation of the following encoding logic:
 // Is the second signed immediate operand, in the range -16 to 15, encoded in the "imm5b" field.
 // bit range mappings:
@@ -2802,6 +2864,42 @@ func encodeI12324(v uint32) (uint32, bool) {
 	return v << 23, true
 }
 
+// encodeVl1011 is the implementation of the following encoding logic:
+// Is the vl specifier,
+// vl	<vl>
+// 0	VLx2
+// 1	VLx4
+// bit range mappings:
+// vl: [10:11)
+func encodeVl1011(v uint32) (uint32, bool) {
+	switch SpecialOperand(v) {
+	case SPOP_VLx2:
+		return 0, true
+	case SPOP_VLx4:
+		return 1 << 10, true
+	default:
+		return 0, false
+	}
+}
+
+// encodeVl1314 is the implementation of the following encoding logic:
+// Is the vl specifier,
+// vl	<vl>
+// 0	VLx2
+// 1	VLx4
+// bit range mappings:
+// vl: [13:14)
+func encodeVl1314(v uint32) (uint32, bool) {
+	switch SpecialOperand(v) {
+	case SPOP_VLx2:
+		return 0, true
+	case SPOP_VLx4:
+		return 1 << 13, true
+	default:
+		return 0, false
+	}
+}
+
 // encodeNoop is the implementation of the following encoding logic:
 // No-op check, returns true
 func encodeNoop(v uint32) (uint32, bool) {
diff --git a/src/cmd/internal/obj/arm64/goops_gen.go b/src/cmd/internal/obj/arm64/goops_gen.go
index 53816d3ead..b7bf97b591 100644
--- a/src/cmd/internal/obj/arm64/goops_gen.go
+++ b/src/cmd/internal/obj/arm64/goops_gen.go
@@ -44,6 +44,10 @@ const (
 	APPFALSE
 	APPFIRST
 	APPNEXT
+	APPRFB
+	APPRFD
+	APPRFH
+	APPRFW
 	APPTEST
 	APPTRUE
 	APPUNPKHI
@@ -404,6 +408,10 @@ const (
 	AZPMUL
 	AZPMULLB
 	AZPMULLT
+	AZPRFB
+	AZPRFD
+	AZPRFH
+	AZPRFW
 	AZRADDHNB
 	AZRADDHNT
 	AZRAX1
diff --git a/src/cmd/internal/obj/arm64/inst.go b/src/cmd/internal/obj/arm64/inst.go
index 0bf4b9950d..ed415c3ee3 100644
--- a/src/cmd/internal/obj/arm64/inst.go
+++ b/src/cmd/internal/obj/arm64/inst.go
@@ -146,6 +146,9 @@ func aclass(a *obj.Addr) AClass {
 	if a.Type == obj.TYPE_MEM {
 		return AC_MEMEXT
 	}
+	if a.Type == obj.TYPE_SPECIAL {
+		return AC_SPECIAL
+	}
 	panic("unknown AClass")
 }
 
@@ -332,6 +335,20 @@ func addrComponent(a *obj.Addr, acl AClass, index int) uint32 {
 		default:
 			panic(fmt.Errorf("unknown elm index at %d in AClass %d", index, acl))
 		}
+	//	AClass: AC_SPECIAL
+	//	GNU mnemonic: <special>
+	//	Go mnemonic:
+	//		special
+	//	Encoding:
+	//		Type = TYPE_SPECIAL
+	//		Offset = SpecialOperand enum value
+	case AC_SPECIAL:
+		switch index {
+		case 0:
+			return uint32(a.Offset)
+		default:
+			panic(fmt.Errorf("unknown elm index at %d in AClass %d", index, acl))
+		}
 	//	AClass: AC_MEMEXT
 	//	GNU mnemonic: [<reg1>.<T1>, <reg2>.<T2>, <mod> <amount>]
 	//	Go mnemonic:
diff --git a/src/cmd/internal/obj/arm64/inst_gen.go b/src/cmd/internal/obj/arm64/inst_gen.go
index 6c68daa26b..ac36eea943 100644
--- a/src/cmd/internal/obj/arm64/inst_gen.go
+++ b/src/cmd/internal/obj/arm64/inst_gen.go
@@ -194,6 +194,12 @@ var insts = [][]instEncoder{
 			fixedBits: 0x25208000,
 			args:      Pn_T__Pg__Xd,
 		},
+		// PCNTP <vl>, <PNn>.<T>, <Xd>
+		{
+			goOp:      APCNTP,
+			fixedBits: 0x25208200,
+			args:      vl__PNn_T__Xd,
+		},
 	},
 	// PDECP
 	{
@@ -363,6 +369,42 @@ var insts = [][]instEncoder{
 			args:      Pdn_T__Pv__Pdn_T,
 		},
 	},
+	// PPRFB
+	{
+		// PPRFB [<Xn|SP>, <Xm>], <Pg>, <prfop>
+		{
+			goOp:      APPRFB,
+			fixedBits: 0x8400c000,
+			args:      XnSP__Xm___Pg__prfop,
+		},
+	},
+	// PPRFD
+	{
+		// PPRFD [<Xn|SP>, <Xm>, LSL #3], <Pg>, <prfop>
+		{
+			goOp:      APPRFD,
+			fixedBits: 0x8580c000,
+			args:      XnSP__Xm__LSL_c3___Pg__prfop,
+		},
+	},
+	// PPRFH
+	{
+		// PPRFH [<Xn|SP>, <Xm>, LSL #1], <Pg>, <prfop>
+		{
+			goOp:      APPRFH,
+			fixedBits: 0x8480c000,
+			args:      XnSP__Xm__LSL_c1___Pg__prfop,
+		},
+	},
+	// PPRFW
+	{
+		// PPRFW [<Xn|SP>, <Xm>, LSL #2], <Pg>, <prfop>
+		{
+			goOp:      APPRFW,
+			fixedBits: 0x8500c000,
+			args:      XnSP__Xm__LSL_c2___Pg__prfop,
+		},
+	},
 	// PPTEST
 	{
 		// PPTEST <Pn>.B, <Pg>
@@ -563,6 +605,12 @@ var insts = [][]instEncoder{
 			fixedBits: 0x25205010,
 			args:      Xm__Xn___Pd1_T__Pd2_T_,
 		},
+		// PWHILEGE <vl>, <Xm>, <Xn>, <PNd>.<T>
+		{
+			goOp:      APWHILEGE,
+			fixedBits: 0x25204010,
+			args:      vl__Xm__Xn__PNd_T,
+		},
 	},
 	// PWHILEGEW
 	{
@@ -587,6 +635,12 @@ var insts = [][]instEncoder{
 			fixedBits: 0x25205011,
 			args:      Xm__Xn___Pd1_T__Pd2_T_,
 		},
+		// PWHILEGT <vl>, <Xm>, <Xn>, <PNd>.<T>
+		{
+			goOp:      APWHILEGT,
+			fixedBits: 0x25204018,
+			args:      vl__Xm__Xn__PNd_T,
+		},
 	},
 	// PWHILEGTW
 	{
@@ -611,6 +665,12 @@ var insts = [][]instEncoder{
 			fixedBits: 0x25205811,
 			args:      Xm__Xn___Pd1_T__Pd2_T_,
 		},
+		// PWHILEHI <vl>, <Xm>, <Xn>, <PNd>.<T>
+		{
+			goOp:      APWHILEHI,
+			fixedBits: 0x25204818,
+			args:      vl__Xm__Xn__PNd_T,
+		},
 	},
 	// PWHILEHIW
 	{
@@ -635,6 +695,12 @@ var insts = [][]instEncoder{
 			fixedBits: 0x25205810,
 			args:      Xm__Xn___Pd1_T__Pd2_T_,
 		},
+		// PWHILEHS <vl>, <Xm>, <Xn>, <PNd>.<T>
+		{
+			goOp:      APWHILEHS,
+			fixedBits: 0x25204810,
+			args:      vl__Xm__Xn__PNd_T,
+		},
 	},
 	// PWHILEHSW
 	{
@@ -659,6 +725,12 @@ var insts = [][]instEncoder{
 			fixedBits: 0x25205411,
 			args:      Xm__Xn___Pd1_T__Pd2_T_,
 		},
+		// PWHILELE <vl>, <Xm>, <Xn>, <PNd>.<T>
+		{
+			goOp:      APWHILELE,
+			fixedBits: 0x25204418,
+			args:      vl__Xm__Xn__PNd_T,
+		},
 	},
 	// PWHILELEW
 	{
@@ -683,6 +755,12 @@ var insts = [][]instEncoder{
 			fixedBits: 0x25205c10,
 			args:      Xm__Xn___Pd1_T__Pd2_T_,
 		},
+		// PWHILELO <vl>, <Xm>, <Xn>, <PNd>.<T>
+		{
+			goOp:      APWHILELO,
+			fixedBits: 0x25204c10,
+			args:      vl__Xm__Xn__PNd_T,
+		},
 	},
 	// PWHILELOW
 	{
@@ -707,6 +785,12 @@ var insts = [][]instEncoder{
 			fixedBits: 0x25205c11,
 			args:      Xm__Xn___Pd1_T__Pd2_T_,
 		},
+		// PWHILELS <vl>, <Xm>, <Xn>, <PNd>.<T>
+		{
+			goOp:      APWHILELS,
+			fixedBits: 0x25204c18,
+			args:      vl__Xm__Xn__PNd_T,
+		},
 	},
 	// PWHILELSW
 	{
@@ -731,6 +815,12 @@ var insts = [][]instEncoder{
 			fixedBits: 0x25205410,
 			args:      Xm__Xn___Pd1_T__Pd2_T_,
 		},
+		// PWHILELT <vl>, <Xm>, <Xn>, <PNd>.<T>
+		{
+			goOp:      APWHILELT,
+			fixedBits: 0x25204410,
+			args:      vl__Xm__Xn__PNd_T,
+		},
 	},
 	// PWHILELTW
 	{
@@ -5457,6 +5547,90 @@ var insts = [][]instEncoder{
 			args:      Zm_Tb__Zn_Tb__Zd_T__3,
 		},
 	},
+	// ZPRFB
+	{
+		// ZPRFB [<Xn|SP>, <Zm>.D], <Pg>, <prfop>
+		{
+			goOp:      AZPRFB,
+			fixedBits: 0xc4608000,
+			args:      XnSP__Zm_D___Pg__prfop,
+		},
+		// ZPRFB [<Xn|SP>, <Zm>.D, <mod>], <Pg>, <prfop>
+		{
+			goOp:      AZPRFB,
+			fixedBits: 0xc4200000,
+			args:      XnSP__Zm_D__mod___Pg__prfop,
+		},
+		// ZPRFB [<Xn|SP>, <Zm>.S, <mod>], <Pg>, <prfop>
+		{
+			goOp:      AZPRFB,
+			fixedBits: 0x84200000,
+			args:      XnSP__Zm_S__mod___Pg__prfop,
+		},
+	},
+	// ZPRFD
+	{
+		// ZPRFD [<Xn|SP>, <Zm>.D, LSL #3], <Pg>, <prfop>
+		{
+			goOp:      AZPRFD,
+			fixedBits: 0xc460e000,
+			args:      XnSP__Zm_D__LSL_c3___Pg__prfop,
+		},
+		// ZPRFD [<Xn|SP>, <Zm>.D, <mod> #3], <Pg>, <prfop>
+		{
+			goOp:      AZPRFD,
+			fixedBits: 0xc4206000,
+			args:      XnSP__Zm_D__mod_c3___Pg__prfop,
+		},
+		// ZPRFD [<Xn|SP>, <Zm>.S, <mod> #3], <Pg>, <prfop>
+		{
+			goOp:      AZPRFD,
+			fixedBits: 0x84206000,
+			args:      XnSP__Zm_S__mod_c3___Pg__prfop,
+		},
+	},
+	// ZPRFH
+	{
+		// ZPRFH [<Xn|SP>, <Zm>.D, LSL #1], <Pg>, <prfop>
+		{
+			goOp:      AZPRFH,
+			fixedBits: 0xc460a000,
+			args:      XnSP__Zm_D__LSL_c1___Pg__prfop,
+		},
+		// ZPRFH [<Xn|SP>, <Zm>.D, <mod> #1], <Pg>, <prfop>
+		{
+			goOp:      AZPRFH,
+			fixedBits: 0xc4202000,
+			args:      XnSP__Zm_D__mod_c1___Pg__prfop,
+		},
+		// ZPRFH [<Xn|SP>, <Zm>.S, <mod> #1], <Pg>, <prfop>
+		{
+			goOp:      AZPRFH,
+			fixedBits: 0x84202000,
+			args:      XnSP__Zm_S__mod_c1___Pg__prfop,
+		},
+	},
+	// ZPRFW
+	{
+		// ZPRFW [<Xn|SP>, <Zm>.D, LSL #2], <Pg>, <prfop>
+		{
+			goOp:      AZPRFW,
+			fixedBits: 0xc460c000,
+			args:      XnSP__Zm_D__LSL_c2___Pg__prfop,
+		},
+		// ZPRFW [<Xn|SP>, <Zm>.D, <mod> #2], <Pg>, <prfop>
+		{
+			goOp:      AZPRFW,
+			fixedBits: 0xc4204000,
+			args:      XnSP__Zm_D__mod_c2___Pg__prfop,
+		},
+		// ZPRFW [<Xn|SP>, <Zm>.S, <mod> #2], <Pg>, <prfop>
+		{
+			goOp:      AZPRFW,
+			fixedBits: 0x84204000,
+			args:      XnSP__Zm_S__mod_c2___Pg__prfop,
+		},
+	},
 	// ZRADDHNB
 	{
 		// ZRADDHNB <Zm>.<Tb>, <Zn>.<Tb>, <Zd>.<T>
@@ -8868,6 +9042,13 @@ var a_ARNG_PNd_SizeBHSD2224 = operand{
 	},
 }
 
+var a_ARNG_PNn59_SizeBHSD2224 = operand{
+	class: AC_ARNG, elemEncoders: []elemEncoder{
+		{encodePNn59, enc_PNn},
+		{encodeSizeBHSD2224, enc_size},
+	},
+}
+
 var a_ARNG_Pd_ArngBCheck = operand{
 	class: AC_ARNG, elemEncoders: []elemEncoder{
 		{encodePd, enc_Pd},
@@ -10363,6 +10544,17 @@ var a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngSCheck_Xs2223_ModAmt2Check = operand{
 	},
 }
 
+var a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngSCheck_Xs2223_ModAmt3Check = operand{
+	class: AC_MEMEXT, elemEncoders: []elemEncoder{
+		{encodeRn510SPV2, enc_Rn},
+		{encodeNoop, enc_NIL},
+		{encodeZm1621V3, enc_Zm},
+		{encodeArngSCheck, enc_NIL},
+		{encodeXs2223, enc_xs},
+		{encodeModAmt3Check, enc_NIL},
+	},
+}
+
 var a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngSCheck_Xs2223_NoAmtCheck = operand{
 	class: AC_MEMEXT, elemEncoders: []elemEncoder{
 		{encodeRn510SPV2, enc_Rn},
@@ -10832,6 +11024,24 @@ var a_REGLIST4_Zt051_ArngSCheck_Zt052_ArngSCheck_Zt053_ArngSCheck_Zt054_ArngSChe
 	},
 }
 
+var a_SPECIAL_Prfop04 = operand{
+	class: AC_SPECIAL, elemEncoders: []elemEncoder{
+		{encodePrfop04, enc_prfop},
+	},
+}
+
+var a_SPECIAL_Vl1011 = operand{
+	class: AC_SPECIAL, elemEncoders: []elemEncoder{
+		{encodeVl1011, enc_vl},
+	},
+}
+
+var a_SPECIAL_Vl1314 = operand{
+	class: AC_SPECIAL, elemEncoders: []elemEncoder{
+		{encodeVl1314, enc_vl},
+	},
+}
+
 var a_SPZGREG_Noop_Rd05 = operand{
 	class: AC_SPZGREG, elemEncoders: []elemEncoder{
 		{encodeNoop, enc_NIL},
@@ -11353,6 +11563,12 @@ var XnSP__Xm__LSL_c1___Pg___Zt_T_ = []operand{
 	a_REGLIST1_Zt05_Size2123V2,
 }
 
+var XnSP__Xm__LSL_c1___Pg__prfop = []operand{
+	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt1Check,
+	a_PREG_Pg1013_Noop,
+	a_SPECIAL_Prfop04,
+}
+
 var XnSP__Xm__LSL_c2___PgZ___Zt1_S__Zt2_S_ = []operand{
 	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt2Check,
 	a_PREGZM_Pg1013_ZeroPredCheck,
@@ -11419,6 +11635,12 @@ var XnSP__Xm__LSL_c2___Pg___Zt_S_ = []operand{
 	a_REGLIST1_Zt05_ArngSCheck,
 }
 
+var XnSP__Xm__LSL_c2___Pg__prfop = []operand{
+	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt2Check,
+	a_PREG_Pg1013_Noop,
+	a_SPECIAL_Prfop04,
+}
+
 var XnSP__Xm__LSL_c3___PgZ___Zt1_D__Zt2_D_ = []operand{
 	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt3Check,
 	a_PREGZM_Pg1013_ZeroPredCheck,
@@ -11473,6 +11695,12 @@ var XnSP__Xm__LSL_c3___Pg___Zt_D_ = []operand{
 	a_REGLIST1_Zt05_ArngDCheck,
 }
 
+var XnSP__Xm__LSL_c3___Pg__prfop = []operand{
+	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt3Check,
+	a_PREG_Pg1013_Noop,
+	a_SPECIAL_Prfop04,
+}
+
 var XnSP__Xm__LSL_c4___PgZ___Zt1_Q__Zt2_Q_ = []operand{
 	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt4Check,
 	a_PREGZM_Pg1013_ZeroPredCheck,
@@ -11605,6 +11833,12 @@ var XnSP__Xm___Pg___Zt_T_ = []operand{
 	a_REGLIST1_Zt05_Size2123V1,
 }
 
+var XnSP__Xm___Pg__prfop = []operand{
+	a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_NoModCheck_NoAmtCheck,
+	a_PREG_Pg1013_Noop,
+	a_SPECIAL_Prfop04,
+}
+
 var XnSP__Zm_D__LSL_c1___PgZ___Zt_D_ = []operand{
 	a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_ModLSLCheck_ModAmt1Check,
 	a_PREGZM_Pg1013_ZeroPredCheck,
@@ -11617,6 +11851,12 @@ var XnSP__Zm_D__LSL_c1___Pg___Zt_D_ = []operand{
 	a_REGLIST1_Zt05_ArngDCheck,
 }
 
+var XnSP__Zm_D__LSL_c1___Pg__prfop = []operand{
+	a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_ModLSLCheck_ModAmt1Check,
+	a_PREG_Pg1013_Noop,
+	a_SPECIAL_Prfop04,
+}
+
 var XnSP__Zm_D__LSL_c2___PgZ___Zt_D_ = []operand{
 	a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_ModLSLCheck_ModAmt2Check,
 	a_PREGZM_Pg1013_ZeroPredCheck,
@@ -11629,6 +11869,12 @@ var XnSP__Zm_D__LSL_c2___Pg___Zt_D_ = []operand{
 	a_REGLIST1_Zt05_ArngDCheck,
 }
 
+var XnSP__Zm_D__LSL_c2___Pg__prfop = []operand{
+	a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_ModLSLCheck_ModAmt2Check,
+	a_PREG_Pg1013_Noop,
+	a_SPECIAL_Prfop04,
+}
+
 var XnSP__Zm_D__LSL_c3___PgZ___Zt_D_ = []operand{
 	a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_ModLSLCheck_ModAmt3Check,
 	a_PREGZM_Pg1013_ZeroPredCheck,
@@ -11641,6 +11887,12 @@ var XnSP__Zm_D__LSL_c3___Pg___Zt_D_ = []operand{
 	a_REGLIST1_Zt05_ArngDCheck,
 }
 
+var XnSP__Zm_D__LSL_c3___Pg__prfop = []operand{
+	a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_ModLSLCheck_ModAmt3Check,
+	a_PREG_Pg1013_Noop,
+	a_SPECIAL_Prfop04,
+}
+
 var XnSP__Zm_D___PgZ___Zt_D_ = []operand{
 	a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_NoModCheck_NoAmtCheck,
 	a_PREGZM_Pg1013_ZeroPredCheck,
@@ -11653,6 +11905,12 @@ var XnSP__Zm_D___Pg___Zt_D_ = []operand{
 	a_REGLIST1_Zt05_ArngDCheck,
 }
 
+var XnSP__Zm_D___Pg__prfop = []operand{
+	a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_NoModCheck_NoAmtCheck,
+	a_PREG_Pg1013_Noop,
+	a_SPECIAL_Prfop04,
+}
+
 var XnSP__Zm_D__mod___PgZ___Zt_D_ = []operand{
 	a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_Xs2223_NoAmtCheck,
 	a_PREGZM_Pg1013_ZeroPredCheck,
@@ -11665,6 +11923,12 @@ var XnSP__Zm_D__mod___Pg___Zt_D_ = []operand{
 	a_REGLIST1_Zt05_ArngDCheck,
 }
 
+var XnSP__Zm_D__mod___Pg__prfop = []operand{
+	a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_Xs2223_NoAmtCheck,
+	a_PREG_Pg1013_Noop,
+	a_SPECIAL_Prfop04,
+}
+
 var XnSP__Zm_D__mod_c1___PgZ___Zt_D_ = []operand{
 	a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_Xs2223_ModAmt1Check,
 	a_PREGZM_Pg1013_ZeroPredCheck,
@@ -11677,6 +11941,12 @@ var XnSP__Zm_D__mod_c1___Pg___Zt_D_ = []operand{
 	a_REGLIST1_Zt05_ArngDCheck,
 }
 
+var XnSP__Zm_D__mod_c1___Pg__prfop = []operand{
+	a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_Xs2223_ModAmt1Check,
+	a_PREG_Pg1013_Noop,
+	a_SPECIAL_Prfop04,
+}
+
 var XnSP__Zm_D__mod_c2___PgZ___Zt_D_ = []operand{
 	a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_Xs2223_ModAmt2Check,
 	a_PREGZM_Pg1013_ZeroPredCheck,
@@ -11689,6 +11959,12 @@ var XnSP__Zm_D__mod_c2___Pg___Zt_D_ = []operand{
 	a_REGLIST1_Zt05_ArngDCheck,
 }
 
+var XnSP__Zm_D__mod_c2___Pg__prfop = []operand{
+	a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_Xs2223_ModAmt2Check,
+	a_PREG_Pg1013_Noop,
+	a_SPECIAL_Prfop04,
+}
+
 var XnSP__Zm_D__mod_c3___PgZ___Zt_D_ = []operand{
 	a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_Xs2223_ModAmt3Check,
 	a_PREGZM_Pg1013_ZeroPredCheck,
@@ -11701,6 +11977,12 @@ var XnSP__Zm_D__mod_c3___Pg___Zt_D_ = []operand{
 	a_REGLIST1_Zt05_ArngDCheck,
 }
 
+var XnSP__Zm_D__mod_c3___Pg__prfop = []operand{
+	a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_Xs2223_ModAmt3Check,
+	a_PREG_Pg1013_Noop,
+	a_SPECIAL_Prfop04,
+}
+
 var XnSP__Zm_S__mod___PgZ___Zt_S_ = []operand{
 	a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngSCheck_Xs2223_NoAmtCheck,
 	a_PREGZM_Pg1013_ZeroPredCheck,
@@ -11713,6 +11995,12 @@ var XnSP__Zm_S__mod___Pg___Zt_S_ = []operand{
 	a_REGLIST1_Zt05_ArngSCheck,
 }
 
+var XnSP__Zm_S__mod___Pg__prfop = []operand{
+	a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngSCheck_Xs2223_NoAmtCheck,
+	a_PREG_Pg1013_Noop,
+	a_SPECIAL_Prfop04,
+}
+
 var XnSP__Zm_S__mod_c1___PgZ___Zt_S_ = []operand{
 	a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngSCheck_Xs2223_ModAmt1Check,
 	a_PREGZM_Pg1013_ZeroPredCheck,
@@ -11725,6 +12013,12 @@ var XnSP__Zm_S__mod_c1___Pg___Zt_S_ = []operand{
 	a_REGLIST1_Zt05_ArngSCheck,
 }
 
+var XnSP__Zm_S__mod_c1___Pg__prfop = []operand{
+	a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngSCheck_Xs2223_ModAmt1Check,
+	a_PREG_Pg1013_Noop,
+	a_SPECIAL_Prfop04,
+}
+
 var XnSP__Zm_S__mod_c2___PgZ___Zt_S_ = []operand{
 	a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngSCheck_Xs2223_ModAmt2Check,
 	a_PREGZM_Pg1013_ZeroPredCheck,
@@ -11737,6 +12031,18 @@ var XnSP__Zm_S__mod_c2___Pg___Zt_S_ = []operand{
 	a_REGLIST1_Zt05_ArngSCheck,
 }
 
+var XnSP__Zm_S__mod_c2___Pg__prfop = []operand{
+	a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngSCheck_Xs2223_ModAmt2Check,
+	a_PREG_Pg1013_Noop,
+	a_SPECIAL_Prfop04,
+}
+
+var XnSP__Zm_S__mod_c3___Pg__prfop = []operand{
+	a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngSCheck_Xs2223_ModAmt3Check,
+	a_PREG_Pg1013_Noop,
+	a_SPECIAL_Prfop04,
+}
+
 var Za_D__Zm_D__Zdn_D = []operand{
 	a_ARNG_Za5103Rd_ArngDCheck,
 	a_ARNG_Zm1621V2_ArngDCheck,
@@ -12949,3 +13255,16 @@ var const__Zm_Tb__Zn_Tb__Zda_T = []operand{
 }
 
 var oc = []operand{}
+
+var vl__PNn_T__Xd = []operand{
+	a_SPECIAL_Vl1011,
+	a_ARNG_PNn59_SizeBHSD2224,
+	a_SPZGREG_Noop_Rd05,
+}
+
+var vl__Xm__Xn__PNd_T = []operand{
+	a_SPECIAL_Vl1314,
+	a_SPZGREG_Noop_Rm1621V1,
+	a_SPZGREG_Noop_Rn510,
+	a_ARNG_PNd_SizeBHSD2224,
+}
diff --git a/src/cmd/internal/obj/arm64/specialoperand_string.go b/src/cmd/internal/obj/arm64/specialoperand_string.go
index 8fb3e9603e..b4dcbc5fda 100644
--- a/src/cmd/internal/obj/arm64/specialoperand_string.go
+++ b/src/cmd/internal/obj/arm64/specialoperand_string.go
@@ -27,143 +27,146 @@ func _() {
 	_ = x[SPOP_PSTL2STRM-15]
 	_ = x[SPOP_PSTL3KEEP-16]
 	_ = x[SPOP_PSTL3STRM-17]
-	_ = x[SPOP_VMALLE1IS-18]
-	_ = x[SPOP_VAE1IS-19]
-	_ = x[SPOP_ASIDE1IS-20]
-	_ = x[SPOP_VAAE1IS-21]
-	_ = x[SPOP_VALE1IS-22]
-	_ = x[SPOP_VAALE1IS-23]
-	_ = x[SPOP_VMALLE1-24]
-	_ = x[SPOP_VAE1-25]
-	_ = x[SPOP_ASIDE1-26]
-	_ = x[SPOP_VAAE1-27]
-	_ = x[SPOP_VALE1-28]
-	_ = x[SPOP_VAALE1-29]
-	_ = x[SPOP_IPAS2E1IS-30]
-	_ = x[SPOP_IPAS2LE1IS-31]
-	_ = x[SPOP_ALLE2IS-32]
-	_ = x[SPOP_VAE2IS-33]
-	_ = x[SPOP_ALLE1IS-34]
-	_ = x[SPOP_VALE2IS-35]
-	_ = x[SPOP_VMALLS12E1IS-36]
-	_ = x[SPOP_IPAS2E1-37]
-	_ = x[SPOP_IPAS2LE1-38]
-	_ = x[SPOP_ALLE2-39]
-	_ = x[SPOP_VAE2-40]
-	_ = x[SPOP_ALLE1-41]
-	_ = x[SPOP_VALE2-42]
-	_ = x[SPOP_VMALLS12E1-43]
-	_ = x[SPOP_ALLE3IS-44]
-	_ = x[SPOP_VAE3IS-45]
-	_ = x[SPOP_VALE3IS-46]
-	_ = x[SPOP_ALLE3-47]
-	_ = x[SPOP_VAE3-48]
-	_ = x[SPOP_VALE3-49]
-	_ = x[SPOP_VMALLE1OS-50]
-	_ = x[SPOP_VAE1OS-51]
-	_ = x[SPOP_ASIDE1OS-52]
-	_ = x[SPOP_VAAE1OS-53]
-	_ = x[SPOP_VALE1OS-54]
-	_ = x[SPOP_VAALE1OS-55]
-	_ = x[SPOP_RVAE1IS-56]
-	_ = x[SPOP_RVAAE1IS-57]
-	_ = x[SPOP_RVALE1IS-58]
-	_ = x[SPOP_RVAALE1IS-59]
-	_ = x[SPOP_RVAE1OS-60]
-	_ = x[SPOP_RVAAE1OS-61]
-	_ = x[SPOP_RVALE1OS-62]
-	_ = x[SPOP_RVAALE1OS-63]
-	_ = x[SPOP_RVAE1-64]
-	_ = x[SPOP_RVAAE1-65]
-	_ = x[SPOP_RVALE1-66]
-	_ = x[SPOP_RVAALE1-67]
-	_ = x[SPOP_RIPAS2E1IS-68]
-	_ = x[SPOP_RIPAS2LE1IS-69]
-	_ = x[SPOP_ALLE2OS-70]
-	_ = x[SPOP_VAE2OS-71]
-	_ = x[SPOP_ALLE1OS-72]
-	_ = x[SPOP_VALE2OS-73]
-	_ = x[SPOP_VMALLS12E1OS-74]
-	_ = x[SPOP_RVAE2IS-75]
-	_ = x[SPOP_RVALE2IS-76]
-	_ = x[SPOP_IPAS2E1OS-77]
-	_ = x[SPOP_RIPAS2E1-78]
-	_ = x[SPOP_RIPAS2E1OS-79]
-	_ = x[SPOP_IPAS2LE1OS-80]
-	_ = x[SPOP_RIPAS2LE1-81]
-	_ = x[SPOP_RIPAS2LE1OS-82]
-	_ = x[SPOP_RVAE2OS-83]
-	_ = x[SPOP_RVALE2OS-84]
-	_ = x[SPOP_RVAE2-85]
-	_ = x[SPOP_RVALE2-86]
-	_ = x[SPOP_ALLE3OS-87]
-	_ = x[SPOP_VAE3OS-88]
-	_ = x[SPOP_VALE3OS-89]
-	_ = x[SPOP_RVAE3IS-90]
-	_ = x[SPOP_RVALE3IS-91]
-	_ = x[SPOP_RVAE3OS-92]
-	_ = x[SPOP_RVALE3OS-93]
-	_ = x[SPOP_RVAE3-94]
-	_ = x[SPOP_RVALE3-95]
-	_ = x[SPOP_IVAC-96]
-	_ = x[SPOP_ISW-97]
-	_ = x[SPOP_CSW-98]
-	_ = x[SPOP_CISW-99]
-	_ = x[SPOP_ZVA-100]
-	_ = x[SPOP_CVAC-101]
-	_ = x[SPOP_CVAU-102]
-	_ = x[SPOP_CIVAC-103]
-	_ = x[SPOP_IGVAC-104]
-	_ = x[SPOP_IGSW-105]
-	_ = x[SPOP_IGDVAC-106]
-	_ = x[SPOP_IGDSW-107]
-	_ = x[SPOP_CGSW-108]
-	_ = x[SPOP_CGDSW-109]
-	_ = x[SPOP_CIGSW-110]
-	_ = x[SPOP_CIGDSW-111]
-	_ = x[SPOP_GVA-112]
-	_ = x[SPOP_GZVA-113]
-	_ = x[SPOP_CGVAC-114]
-	_ = x[SPOP_CGDVAC-115]
-	_ = x[SPOP_CGVAP-116]
-	_ = x[SPOP_CGDVAP-117]
-	_ = x[SPOP_CGVADP-118]
-	_ = x[SPOP_CGDVADP-119]
-	_ = x[SPOP_CIGVAC-120]
-	_ = x[SPOP_CIGDVAC-121]
-	_ = x[SPOP_CVAP-122]
-	_ = x[SPOP_CVADP-123]
-	_ = x[SPOP_DAIFSet-124]
-	_ = x[SPOP_DAIFClr-125]
-	_ = x[SPOP_EQ-126]
-	_ = x[SPOP_NE-127]
-	_ = x[SPOP_HS-128]
-	_ = x[SPOP_LO-129]
-	_ = x[SPOP_MI-130]
-	_ = x[SPOP_PL-131]
-	_ = x[SPOP_VS-132]
-	_ = x[SPOP_VC-133]
-	_ = x[SPOP_HI-134]
-	_ = x[SPOP_LS-135]
-	_ = x[SPOP_GE-136]
-	_ = x[SPOP_LT-137]
-	_ = x[SPOP_GT-138]
-	_ = x[SPOP_LE-139]
-	_ = x[SPOP_AL-140]
-	_ = x[SPOP_NV-141]
-	_ = x[SPOP_C-142]
-	_ = x[SPOP_J-143]
-	_ = x[SPOP_JC-144]
-	_ = x[SPOP_END-145]
+	_ = x[SPOP_VLx2-18]
+	_ = x[SPOP_VLx4-19]
+	_ = x[SPOP_VMALLE1IS-20]
+	_ = x[SPOP_VAE1IS-21]
+	_ = x[SPOP_ASIDE1IS-22]
+	_ = x[SPOP_VAAE1IS-23]
+	_ = x[SPOP_VALE1IS-24]
+	_ = x[SPOP_VAALE1IS-25]
+	_ = x[SPOP_VMALLE1-26]
+	_ = x[SPOP_VAE1-27]
+	_ = x[SPOP_ASIDE1-28]
+	_ = x[SPOP_VAAE1-29]
+	_ = x[SPOP_VALE1-30]
+	_ = x[SPOP_VAALE1-31]
+	_ = x[SPOP_IPAS2E1IS-32]
+	_ = x[SPOP_IPAS2LE1IS-33]
+	_ = x[SPOP_ALLE2IS-34]
+	_ = x[SPOP_VAE2IS-35]
+	_ = x[SPOP_ALLE1IS-36]
+	_ = x[SPOP_VALE2IS-37]
+	_ = x[SPOP_VMALLS12E1IS-38]
+	_ = x[SPOP_IPAS2E1-39]
+	_ = x[SPOP_IPAS2LE1-40]
+	_ = x[SPOP_ALLE2-41]
+	_ = x[SPOP_VAE2-42]
+	_ = x[SPOP_ALLE1-43]
+	_ = x[SPOP_VALE2-44]
+	_ = x[SPOP_VMALLS12E1-45]
+	_ = x[SPOP_ALLE3IS-46]
+	_ = x[SPOP_VAE3IS-47]
+	_ = x[SPOP_VALE3IS-48]
+	_ = x[SPOP_ALLE3-49]
+	_ = x[SPOP_VAE3-50]
+	_ = x[SPOP_VALE3-51]
+	_ = x[SPOP_VMALLE1OS-52]
+	_ = x[SPOP_VAE1OS-53]
+	_ = x[SPOP_ASIDE1OS-54]
+	_ = x[SPOP_VAAE1OS-55]
+	_ = x[SPOP_VALE1OS-56]
+	_ = x[SPOP_VAALE1OS-57]
+	_ = x[SPOP_RVAE1IS-58]
+	_ = x[SPOP_RVAAE1IS-59]
+	_ = x[SPOP_RVALE1IS-60]
+	_ = x[SPOP_RVAALE1IS-61]
+	_ = x[SPOP_RVAE1OS-62]
+	_ = x[SPOP_RVAAE1OS-63]
+	_ = x[SPOP_RVALE1OS-64]
+	_ = x[SPOP_RVAALE1OS-65]
+	_ = x[SPOP_RVAE1-66]
+	_ = x[SPOP_RVAAE1-67]
+	_ = x[SPOP_RVALE1-68]
+	_ = x[SPOP_RVAALE1-69]
+	_ = x[SPOP_RIPAS2E1IS-70]
+	_ = x[SPOP_RIPAS2LE1IS-71]
+	_ = x[SPOP_ALLE2OS-72]
+	_ = x[SPOP_VAE2OS-73]
+	_ = x[SPOP_ALLE1OS-74]
+	_ = x[SPOP_VALE2OS-75]
+	_ = x[SPOP_VMALLS12E1OS-76]
+	_ = x[SPOP_RVAE2IS-77]
+	_ = x[SPOP_RVALE2IS-78]
+	_ = x[SPOP_IPAS2E1OS-79]
+	_ = x[SPOP_RIPAS2E1-80]
+	_ = x[SPOP_RIPAS2E1OS-81]
+	_ = x[SPOP_IPAS2LE1OS-82]
+	_ = x[SPOP_RIPAS2LE1-83]
+	_ = x[SPOP_RIPAS2LE1OS-84]
+	_ = x[SPOP_RVAE2OS-85]
+	_ = x[SPOP_RVALE2OS-86]
+	_ = x[SPOP_RVAE2-87]
+	_ = x[SPOP_RVALE2-88]
+	_ = x[SPOP_ALLE3OS-89]
+	_ = x[SPOP_VAE3OS-90]
+	_ = x[SPOP_VALE3OS-91]
+	_ = x[SPOP_RVAE3IS-92]
+	_ = x[SPOP_RVALE3IS-93]
+	_ = x[SPOP_RVAE3OS-94]
+	_ = x[SPOP_RVALE3OS-95]
+	_ = x[SPOP_RVAE3-96]
+	_ = x[SPOP_RVALE3-97]
+	_ = x[SPOP_IVAC-98]
+	_ = x[SPOP_ISW-99]
+	_ = x[SPOP_CSW-100]
+	_ = x[SPOP_CISW-101]
+	_ = x[SPOP_ZVA-102]
+	_ = x[SPOP_CVAC-103]
+	_ = x[SPOP_CVAU-104]
+	_ = x[SPOP_CIVAC-105]
+	_ = x[SPOP_IGVAC-106]
+	_ = x[SPOP_IGSW-107]
+	_ = x[SPOP_IGDVAC-108]
+	_ = x[SPOP_IGDSW-109]
+	_ = x[SPOP_CGSW-110]
+	_ = x[SPOP_CGDSW-111]
+	_ = x[SPOP_CIGSW-112]
+	_ = x[SPOP_CIGDSW-113]
+	_ = x[SPOP_GVA-114]
+	_ = x[SPOP_GZVA-115]
+	_ = x[SPOP_CGVAC-116]
+	_ = x[SPOP_CGDVAC-117]
+	_ = x[SPOP_CGVAP-118]
+	_ = x[SPOP_CGDVAP-119]
+	_ = x[SPOP_CGVADP-120]
+	_ = x[SPOP_CGDVADP-121]
+	_ = x[SPOP_CIGVAC-122]
+	_ = x[SPOP_CIGDVAC-123]
+	_ = x[SPOP_CVAP-124]
+	_ = x[SPOP_CVADP-125]
+	_ = x[SPOP_DAIFSet-126]
+	_ = x[SPOP_DAIFClr-127]
+	_ = x[SPOP_EQ-128]
+	_ = x[SPOP_NE-129]
+	_ = x[SPOP_HS-130]
+	_ = x[SPOP_LO-131]
+	_ = x[SPOP_MI-132]
+	_ = x[SPOP_PL-133]
+	_ = x[SPOP_VS-134]
+	_ = x[SPOP_VC-135]
+	_ = x[SPOP_HI-136]
+	_ = x[SPOP_LS-137]
+	_ = x[SPOP_GE-138]
+	_ = x[SPOP_LT-139]
+	_ = x[SPOP_GT-140]
+	_ = x[SPOP_LE-141]
+	_ = x[SPOP_AL-142]
+	_ = x[SPOP_NV-143]
+	_ = x[SPOP_C-144]
+	_ = x[SPOP_J-145]
+	_ = x[SPOP_JC-146]
+	_ = x[SPOP_END-147]
 }
 
-const _SpecialOperand_name = "PLDL1KEEPPLDL1STRMPLDL2KEEPPLDL2STRMPLDL3KEEPPLDL3STRMPLIL1KEEPPLIL1STRMPLIL2KEEPPLIL2STRMPLIL3KEEPPLIL3STRMPSTL1KEEPPSTL1STRMPSTL2KEEPPSTL2STRMPSTL3KEEPPSTL3STRMVMALLE1ISVAE1ISASIDE1ISVAAE1ISVALE1ISVAALE1ISVMALLE1VAE1ASIDE1VAAE1VALE1VAALE1IPAS2E1ISIPAS2LE1ISALLE2ISVAE2ISALLE1ISVALE2ISVMALLS12E1ISIPAS2E1IPAS2LE1ALLE2VAE2ALLE1VALE2VMALLS12E1ALLE3ISVAE3ISVALE3ISALLE3VAE3VALE3VMALLE1OSVAE1OSASIDE1OSVAAE1OSVALE1OSVAALE1OSRVAE1ISRVAAE1ISRVALE1ISRVAALE1ISRVAE1OSRVAAE1OSRVALE1OSRVAALE1OSRVAE1RVAAE1RVALE1RVAALE1RIPAS2E1ISRIPAS2LE1ISALLE2OSVAE2OSALLE1OSVALE2OSVMALLS12E1OSRVAE2ISRVALE2ISIPAS2E1OSRIPAS2E1RIPAS2E1OSIPAS2LE1OSRIPAS2LE1RIPAS2LE1OSRVAE2OSRVALE2OSRVAE2RVALE2ALLE3OSVAE3OSVALE3OSRVAE3ISRVALE3ISRVAE3OSRVALE3OSRVAE3RVALE3IVACISWCSWCISWZVACVACCVAUCIVACIGVACIGSWIGDVACIGDSWCGSWCGDSWCIGSWCIGDSWGVAGZVACGVACCGDVACCGVAPCGDVAPCGVADPCGDVADPCIGVACCIGDVACCVAPCVADPDAIFSetDAIFClrEQNEHSLOMIPLVSVCHILSGELTGTLEALNVCJJCEND"
+const _SpecialOperand_name = "PLDL1KEEPPLDL1STRMPLDL2KEEPPLDL2STRMPLDL3KEEPPLDL3STRMPLIL1KEEPPLIL1STRMPLIL2KEEPPLIL2STRMPLIL3KEEPPLIL3STRMPSTL1KEEPPSTL1STRMPSTL2KEEPPSTL2STRMPSTL3KEEPPSTL3STRMVLx2VLx4VMALLE1ISVAE1ISASIDE1ISVAAE1ISVALE1ISVAALE1ISVMALLE1VAE1ASIDE1VAAE1VALE1VAALE1IPAS2E1ISIPAS2LE1ISALLE2ISVAE2ISALLE1ISVALE2ISVMALLS12E1ISIPAS2E1IPAS2LE1ALLE2VAE2ALLE1VALE2VMALLS12E1ALLE3ISVAE3ISVALE3ISALLE3VAE3VALE3VMALLE1OSVAE1OSASIDE1OSVAAE1OSVALE1OSVAALE1OSRVAE1ISRVAAE1ISRVALE1ISRVAALE1ISRVAE1OSRVAAE1OSRVALE1OSRVAALE1OSRVAE1RVAAE1RVALE1RVAALE1RIPAS2E1ISRIPAS2LE1ISALLE2OSVAE2OSALLE1OSVALE2OSVMALLS12E1OSRVAE2ISRVALE2ISIPAS2E1OSRIPAS2E1RIPAS2E1OSIPAS2LE1OSRIPAS2LE1RIPAS2LE1OSRVAE2OSRVALE2OSRVAE2RVALE2ALLE3OSVAE3OSVALE3OSRVAE3ISRVALE3ISRVAE3OSRVALE3OSRVAE3RVALE3IVACISWCSWCISWZVACVACCVAUCIVACIGVACIGSWIGDVACIGDSWCGSWCGDSWCIGSWCIGDSWGVAGZVACGVACCGDVACCGVAPCGDVAPCGVADPCGDVADPCIGVACCIGDVACCVAPCVADPDAIFSetDAIFClrEQNEHSLOMIPLVSVCHILSGELTGTLEALNVCJJCEND"
 
-var _SpecialOperand_index = [...]uint16{0, 9, 18, 27, 36, 45, 54, 63, 72, 81, 90, 99, 108, 117, 126, 135, 144, 153, 162, 171, 177, 185, 192, 199, 207, 214, 218, 224, 229, 234, 240, 249, 259, 266, 272, 279, 286, 298, 305, 313, 318, 322, 327, 332, 342, 349, 355, 362, 367, 371, 376, 385, 391, 399, 406, 413, 421, 428, 436, 444, 453, 460, 468, 476, 485, 490, 496, 502, 509, 519, 530, 537, 543, 550, 557, 569, 576, 584, 593, 601, 611, 621, 630, 641, 648, 656, 661, 667, 674, 680, 687, 694, 702, 709, 717, 722, 728, 732, 735, 738, 742, 745, 749, 753, 758, 763, 767, 773, 778, 782, 787, 792, 798, 801, 805, 810, 816, 821, 827, 833, 840, 846, 853, 857, 862, 869, 876, 878, 880, 882, 884, 886, 888, 890, 892, 894, 896, 898, 900, 902, 904, 906, 908, 909, 910, 912, 915}
+var _SpecialOperand_index = [...]uint16{0, 9, 18, 27, 36, 45, 54, 63, 72, 81, 90, 99, 108, 117, 126, 135, 144, 153, 162, 166, 170, 179, 185, 193, 200, 207, 215, 222, 226, 232, 237, 242, 248, 257, 267, 274, 280, 287, 294, 306, 313, 321, 326, 330, 335, 340, 350, 357, 363, 370, 375, 379, 384, 393, 399, 407, 414, 421, 429, 436, 444, 452, 461, 468, 476, 484, 493, 498, 504, 510, 517, 527, 538, 545, 551, 558, 565, 577, 584, 592, 601, 609, 619, 629, 638, 649, 656, 664, 669, 675, 682, 688, 695, 702, 710, 717, 725, 730, 736, 740, 743, 746, 750, 753, 757, 761, 766, 771, 775, 781, 786, 790, 795, 800, 806, 809, 813, 818, 824, 829, 835, 841, 848, 854, 861, 865, 870, 877, 884, 886, 888, 890, 892, 894, 896, 898, 900, 902, 904, 906, 908, 910, 912, 914, 916, 917, 918, 920, 923}
 
 func (i SpecialOperand) String() string {
-	if i < 0 || i >= SpecialOperand(len(_SpecialOperand_index)-1) {
+	idx := int(i) - 0
+	if i < 0 || idx >= len(_SpecialOperand_index)-1 {
 		return "SpecialOperand(" + strconv.FormatInt(int64(i), 10) + ")"
 	}
-	return _SpecialOperand_name[_SpecialOperand_index[i]:_SpecialOperand_index[i+1]]
+	return _SpecialOperand_name[_SpecialOperand_index[idx]:_SpecialOperand_index[idx+1]]
 }