From 7d70f84f547a1b60279985fa91c407ddfde9bd64 Mon Sep 17 00:00:00 2001 From: Cherry Zhang Date: Wed, 6 Jul 2016 10:04:45 -0400 Subject: [dev.ssa] cmd/compile: add floating point optimizations in SSA for ARM Add some simplification rules for floating point ops. cmd/internal/obj/arm supports instructions that compare FP register to 0, but runtime softfloat simulator does not. This CL adds these instructions to softfloat simulator as well. Updates #15365. Change-Id: I29405b2bfcb4c8cf106cb7a1a811409fec91b170 Reviewed-on: https://go-review.googlesource.com/24790 Run-TryBot: Cherry Zhang TryBot-Result: Gobot Gobot Reviewed-by: David Chase --- src/runtime/softfloat_arm.go | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'src/runtime/softfloat_arm.go') diff --git a/src/runtime/softfloat_arm.go b/src/runtime/softfloat_arm.go index 5f609c80d3..802a151fbf 100644 --- a/src/runtime/softfloat_arm.go +++ b/src/runtime/softfloat_arm.go @@ -464,6 +464,24 @@ execute: } return 1 + case 0xeeb50bc0: // D[regd] :: 0 (CMPD) + cmp, nan := fcmp64(fgetd(regd), 0) + m.fflag = fstatus(nan, cmp) + + if fptrace > 0 { + print("*** cmp D[", regd, "]::0 ", hex(m.fflag), "\n") + } + return 1 + + case 0xeeb50ac0: // F[regd] :: 0 (CMPF) + cmp, nan := fcmp64(f32to64(m.freglo[regd]), 0) + m.fflag = fstatus(nan, cmp) + + if fptrace > 0 { + print("*** cmp F[", regd, "]::0 ", hex(m.fflag), "\n") + } + return 1 + case 0xeeb70ac0: // D[regd] = F[regm] (MOVFD) fputd(regd, f32to64(m.freglo[regm])) -- cgit v1.3