From 41054cdb1cd9f2a7400668d385ec1a030d90389c Mon Sep 17 00:00:00 2001
From: Junyang Shao <shaojunyang@google.com>
Date: Tue, 15 Jul 2025 21:38:28 +0000
Subject: [dev.simd] simd, internal/cpu: support more AVX CPU Feature checks

This CL adds more checks, it also changes HasAVX512GFNI to be exactly
checking GFNI instead of being a virtual feature.

This CL copies its logic from x/sys/arch.

Change-Id: I4612b0409b8a3518928300562ae08bcf123d53a7
Reviewed-on: https://go-review.googlesource.com/c/go/+/688276
LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
Reviewed-by: David Chase <drchase@google.com>
---
 src/internal/cpu/cpu.go | 61 ++++++++++++++++++++++++++-----------------------
 1 file changed, 33 insertions(+), 28 deletions(-)

(limited to 'src/internal/cpu/cpu.go')

diff --git a/src/internal/cpu/cpu.go b/src/internal/cpu/cpu.go
index 1eeb580711..53633c7ca8 100644
--- a/src/internal/cpu/cpu.go
+++ b/src/internal/cpu/cpu.go
@@ -26,34 +26,39 @@ var CacheLineSize uintptr = CacheLinePadSize
 // in addition to the cpuid feature bit being set.
 // The struct is padded to avoid false sharing.
 var X86 struct {
-	_             CacheLinePad
-	HasAES        bool
-	HasADX        bool
-	HasAVX        bool
-	HasAVX2       bool
-	HasAVX512GFNI bool // Virtual feature: F+CD+BW+DQ+VL+GFNI
-	HasAVX512     bool // Virtual feature: F+CD+BW+DQ+VL
-	HasAVX512F    bool
-	HasAVX512CD   bool
-	HasAVX512BW   bool
-	HasAVX512DQ   bool
-	HasAVX512VL   bool
-	HasBMI1       bool
-	HasBMI2       bool
-	HasERMS       bool
-	HasFSRM       bool
-	HasFMA        bool
-	HasGFNI       bool
-	HasOSXSAVE    bool
-	HasPCLMULQDQ  bool
-	HasPOPCNT     bool
-	HasRDTSCP     bool
-	HasSHA        bool
-	HasSSE3       bool
-	HasSSSE3      bool
-	HasSSE41      bool
-	HasSSE42      bool
-	_             CacheLinePad
+	_                  CacheLinePad
+	HasAES             bool
+	HasADX             bool
+	HasAVX             bool
+	HasAVXVNNI         bool
+	HasAVX2            bool
+	HasAVX512          bool // Virtual feature: F+CD+BW+DQ+VL
+	HasAVX512F         bool
+	HasAVX512CD        bool
+	HasAVX512BW        bool
+	HasAVX512DQ        bool
+	HasAVX512VL        bool
+	HasAVX512GFNI      bool
+	HasAVX512VNNI      bool
+	HasAVX512VBMI      bool
+	HasAVX512VBMI2     bool
+	HasAVX512BITALG    bool
+	HasAVX512VPOPCNTDQ bool
+	HasBMI1            bool
+	HasBMI2            bool
+	HasERMS            bool
+	HasFSRM            bool
+	HasFMA             bool
+	HasOSXSAVE         bool
+	HasPCLMULQDQ       bool
+	HasPOPCNT          bool
+	HasRDTSCP          bool
+	HasSHA             bool
+	HasSSE3            bool
+	HasSSSE3           bool
+	HasSSE41           bool
+	HasSSE42           bool
+	_                  CacheLinePad
 }
 
 // The booleans in ARM contain the correspondingly named cpu feature bit.
-- 
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