From 371c1d2fcb48fa79ac30812231ecef0e26f539dc Mon Sep 17 00:00:00 2001 From: wangboyao Date: Thu, 24 Jul 2025 14:49:44 +0800 Subject: cmd/internal/obj/riscv: add support for vector unit-stride fault-only-first load instructions Add support for vector unit-stride fault-only-first load instructions to the RISC-V assembler. This includes vle8ff, vle16ff, vle32ff and vle64ff. Change-Id: I5575a1ea155663852f92194fb79f08b5d52203de Reviewed-on: https://go-review.googlesource.com/c/go/+/690115 Reviewed-by: Junyang Shao Reviewed-by: Meng Zhuo Reviewed-by: Cherry Mui Reviewed-by: Joel Sing LUCI-TryBot-Result: Go LUCI --- src/cmd/internal/obj/riscv/obj.go | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'src/cmd/internal/obj') diff --git a/src/cmd/internal/obj/riscv/obj.go b/src/cmd/internal/obj/riscv/obj.go index 9d595f301c..91642ffbcb 100644 --- a/src/cmd/internal/obj/riscv/obj.go +++ b/src/cmd/internal/obj/riscv/obj.go @@ -2176,6 +2176,12 @@ var instructions = [ALAST & obj.AMask]instructionData{ AVSOXEI32V & obj.AMask: {enc: sVIVEncoding}, AVSOXEI64V & obj.AMask: {enc: sVIVEncoding}, + // 31.7.7: Unit-stride Fault-Only-First Loads + AVLE8FFV & obj.AMask: {enc: iVEncoding}, + AVLE16FFV & obj.AMask: {enc: iVEncoding}, + AVLE32FFV & obj.AMask: {enc: iVEncoding}, + AVLE64FFV & obj.AMask: {enc: iVEncoding}, + // 31.7.8: Vector Load/Store Segment Instructions AVLSEG2E8V & obj.AMask: {enc: iVEncoding}, AVLSEG3E8V & obj.AMask: {enc: iVEncoding}, @@ -3839,7 +3845,7 @@ func instructionsForProg(p *obj.Prog) []*instruction { ins.rs1 = uint32(p.From.Offset) } - case AVLE8V, AVLE16V, AVLE32V, AVLE64V, AVSE8V, AVSE16V, AVSE32V, AVSE64V, AVLMV, AVSMV, + case AVLE8V, AVLE16V, AVLE32V, AVLE64V, AVSE8V, AVSE16V, AVSE32V, AVSE64V, AVLE8FFV, AVLE16FFV, AVLE32FFV, AVLE64FFV, AVLMV, AVSMV, AVLSEG2E8V, AVLSEG3E8V, AVLSEG4E8V, AVLSEG5E8V, AVLSEG6E8V, AVLSEG7E8V, AVLSEG8E8V, AVLSEG2E16V, AVLSEG3E16V, AVLSEG4E16V, AVLSEG5E16V, AVLSEG6E16V, AVLSEG7E16V, AVLSEG8E16V, AVLSEG2E32V, AVLSEG3E32V, AVLSEG4E32V, AVLSEG5E32V, AVLSEG6E32V, AVLSEG7E32V, AVLSEG8E32V, -- cgit v1.3 From 76d088eb74115ea14f774d1940557ca3047e1ebb Mon Sep 17 00:00:00 2001 From: Joel Sing Date: Wed, 10 Sep 2025 01:00:22 +1000 Subject: cmd/internal/obj/riscv: remove ACFLWSP/ACFSWSP and ACFLW/ACFSW These are RV32-only instructions that will not be implemented. Updates #71105 Change-Id: Ie386fe36e56f1151bb8756088dd79804584317c0 Reviewed-on: https://go-review.googlesource.com/c/go/+/702395 LUCI-TryBot-Result: Go LUCI Reviewed-by: Meng Zhuo Reviewed-by: Mark Ryan Reviewed-by: Mark Freeman Reviewed-by: Michael Pratt --- src/cmd/internal/obj/riscv/anames.go | 4 ---- src/cmd/internal/obj/riscv/cpu.go | 4 ---- 2 files changed, 8 deletions(-) (limited to 'src/cmd/internal/obj') diff --git a/src/cmd/internal/obj/riscv/anames.go b/src/cmd/internal/obj/riscv/anames.go index a8807fc7a8..6c48e2f7de 100644 --- a/src/cmd/internal/obj/riscv/anames.go +++ b/src/cmd/internal/obj/riscv/anames.go @@ -195,20 +195,16 @@ var Anames = []string{ "FLTQ", "FCLASSQ", "CLWSP", - "CFLWSP", "CLDSP", "CFLDSP", "CSWSP", "CSDSP", - "CFSWSP", "CFSDSP", "CLW", "CLD", - "CFLW", "CFLD", "CSW", "CSD", - "CFSW", "CFSD", "CJ", "CJR", diff --git a/src/cmd/internal/obj/riscv/cpu.go b/src/cmd/internal/obj/riscv/cpu.go index 305ef061e3..60174a0b3a 100644 --- a/src/cmd/internal/obj/riscv/cpu.go +++ b/src/cmd/internal/obj/riscv/cpu.go @@ -588,22 +588,18 @@ const ( // 26.3.1: Compressed Stack-Pointer-Based Loads and Stores ACLWSP - ACFLWSP ACLDSP ACFLDSP ACSWSP ACSDSP - ACFSWSP ACFSDSP // 26.3.2: Compressed Register-Based Loads and Stores ACLW ACLD - ACFLW ACFLD ACSW ACSD - ACFSW ACFSD // 26.4: Compressed Control Transfer Instructions -- cgit v1.3