From 6837583eec31bf197a8f16bcb431e3beb73b2aa5 Mon Sep 17 00:00:00 2001 From: Guoqi Chen Date: Fri, 6 Feb 2026 10:09:10 +0800 Subject: cmd/internal/obj/loong64: improve ARNG type register name conversion When resolving ARNG type names, the base value was not subtracted when calculating the variable simd_type, causing its actual value to not match the expected meaning after the base value adjustment. Fixes #77414 Change-Id: I713bab849ecdb5610d2593ba9bd9e1169842f00e Reviewed-on: https://go-review.googlesource.com/c/go/+/742980 LUCI-TryBot-Result: Go LUCI Reviewed-by: WANG Xuerui Reviewed-by: Michael Pratt Reviewed-by: Junyang Shao Reviewed-by: Meidan Li --- src/cmd/internal/obj/loong64/list.go | 87 +++++++++++++++++++----------------- 1 file changed, 45 insertions(+), 42 deletions(-) (limited to 'src/cmd/internal/obj') diff --git a/src/cmd/internal/obj/loong64/list.go b/src/cmd/internal/obj/loong64/list.go index dba8aab029..1a7926f818 100644 --- a/src/cmd/internal/obj/loong64/list.go +++ b/src/cmd/internal/obj/loong64/list.go @@ -10,52 +10,73 @@ import ( ) func init() { - obj.RegisterRegister(obj.RBaseLOONG64, REG_LAST, rconv) + obj.RegisterRegister(obj.RBaseLOONG64, REG_LAST, RegName) obj.RegisterOpcode(obj.ABaseLoong64, Anames) } -func arrange(a int16) string { - switch a { +func arrange(valid int16) string { + var regPrefix string + var arngName string + + // bits 0-4 indicates register: Vn or Xn + // bits 5-9 indicates arrangement: + // bits 10 indicates SMID type: 0: LSX, 1: LASX + simdType := (valid >> EXT_SIMDTYPE_SHIFT) & EXT_SIMDTYPE_MASK + simdReg := (valid >> EXT_REG_SHIFT) & EXT_REG_MASK + arngType := (valid >> EXT_TYPE_SHIFT) & EXT_TYPE_MASK + + switch simdType { + case LSX: + regPrefix = "V" + case LASX: + regPrefix = "X" + default: + regPrefix = "#" + } + + switch arngType { case ARNG_32B: - return "B32" + arngName = "B32" case ARNG_16H: - return "H16" + arngName = "H16" case ARNG_8W: - return "W8" + arngName = "W8" case ARNG_4V: - return "V4" + arngName = "V4" case ARNG_2Q: - return "Q2" + arngName = "Q2" case ARNG_16B: - return "B16" + arngName = "B16" case ARNG_8H: - return "H8" + arngName = "H8" case ARNG_4W: - return "W4" + arngName = "W4" case ARNG_2V: - return "V2" + arngName = "V2" case ARNG_B: - return "B" + arngName = "B" case ARNG_H: - return "H" + arngName = "H" case ARNG_W: - return "W" + arngName = "W" case ARNG_V: - return "V" + arngName = "V" case ARNG_BU: - return "BU" + arngName = "BU" case ARNG_HU: - return "HU" + arngName = "HU" case ARNG_WU: - return "WU" + arngName = "WU" case ARNG_VU: - return "VU" + arngName = "VU" default: - return "ARNG_???" + arngName = "ARNG_???" } + + return fmt.Sprintf("%s%d.%s", regPrefix, simdReg, arngName) } -func rconv(r int) string { +func RegName(r int) string { switch { case r == 0: return "NONE" @@ -74,28 +95,10 @@ func rconv(r int) string { return fmt.Sprintf("V%d", r-REG_V0) case REG_X0 <= r && r <= REG_X31: return fmt.Sprintf("X%d", r-REG_X0) - } - - // bits 0-4 indicates register: Vn or Xn - // bits 5-9 indicates arrangement: - // bits 10 indicates SMID type: 0: LSX, 1: LASX - simd_type := (int16(r) >> EXT_SIMDTYPE_SHIFT) & EXT_SIMDTYPE_MASK - reg_num := (int16(r) >> EXT_REG_SHIFT) & EXT_REG_MASK - arng_type := (int16(r) >> EXT_TYPE_SHIFT) & EXT_TYPE_MASK - reg_prefix := "#" - switch simd_type { - case LSX: - reg_prefix = "V" - case LASX: - reg_prefix = "X" - } - - switch { case REG_ARNG <= r && r < REG_ELEM: - return fmt.Sprintf("%s%d.%s", reg_prefix, reg_num, arrange(arng_type)) - + return arrange(int16(r - REG_ARNG)) case REG_ELEM <= r && r < REG_ELEM_END: - return fmt.Sprintf("%s%d.%s", reg_prefix, reg_num, arrange(arng_type)) + return arrange(int16(r - REG_ELEM)) } return fmt.Sprintf("badreg(%d)", r-obj.RBaseLOONG64) -- cgit v1.3