From 4b2f7b4b51180424c4e84b50d99e1fba5b6f3e89 Mon Sep 17 00:00:00 2001 From: Ben Shi Date: Fri, 28 Apr 2017 10:55:41 +0000 Subject: cmd/asm: fix operand order of ARM's MULA instruction As discussion in issue #19141, the addend should be the third argument of MULA. This patch fixes it in both the front end and the back end of the assembler. And also tests are added to the encoding test. Fixes #19141 Change-Id: Idbc6f338b8fdfcad97a135f27a98c5b375b27d43 Reviewed-on: https://go-review.googlesource.com/42028 Run-TryBot: Cherry Zhang TryBot-Result: Gobot Gobot Reviewed-by: Cherry Zhang --- src/cmd/internal/obj/util.go | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/cmd/internal/obj/util.go') diff --git a/src/cmd/internal/obj/util.go b/src/cmd/internal/obj/util.go index 2e3ba15542..9bcdbbd127 100644 --- a/src/cmd/internal/obj/util.go +++ b/src/cmd/internal/obj/util.go @@ -240,7 +240,7 @@ func Dconv(p *Prog, a *Addr) string { str = fmt.Sprintf("(%v, %v)", Rconv(int(a.Reg)), Rconv(int(a.Offset))) case TYPE_REGREG2: - str = fmt.Sprintf("%v, %v", Rconv(int(a.Reg)), Rconv(int(a.Offset))) + str = fmt.Sprintf("%v, %v", Rconv(int(a.Offset)), Rconv(int(a.Reg))) case TYPE_REGLIST: str = regListConv(int(a.Offset)) -- cgit v1.3-5-g45d5