From e00a38c89a4e0afa985072bdffe5dd30de7eccda Mon Sep 17 00:00:00 2001 From: Ben Shi Date: Fri, 16 Jun 2017 11:19:01 +0000 Subject: cmd/internal/obj/arm: fix setting U bit in shifted register offset of MOVBS "MOVBS.U R0<<0(R1), R2" is assembled to 0xe19120d0 (ldrsb r2, [r1, r0]), but it is expected to be 0xe11120d0 (ldrsb r2, [r1, -r0]). This patch fixes it and adds more encoding tests. fixes #20701 Change-Id: Ic1fb46438d71a978dbef06d97494a70c95fcbf3a Reviewed-on: https://go-review.googlesource.com/45996 Run-TryBot: Cherry Zhang TryBot-Result: Gobot Gobot Reviewed-by: Cherry Zhang --- src/cmd/internal/obj/arm/asm5.go | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'src/cmd/internal/obj/arm') diff --git a/src/cmd/internal/obj/arm/asm5.go b/src/cmd/internal/obj/arm/asm5.go index 417da44574..6cb6072769 100644 --- a/src/cmd/internal/obj/arm/asm5.go +++ b/src/cmd/internal/obj/arm/asm5.go @@ -2249,10 +2249,13 @@ func (c *ctxt5) asmout(p *obj.Prog, o *Optab, out []uint32) { } if p.From.Offset&(^0xf) != 0 { - c.ctxt.Diag("bad shift in LDRSB") + c.ctxt.Diag("bad shift: %v", p) } o1 = c.olhrr(int(p.From.Offset), int(p.From.Reg), int(p.To.Reg), int(p.Scond)) o1 ^= 1<<5 | 1<<6 + if p.Scond&C_UBIT != 0 { + o1 &^= 1 << 23 + } case 61: /* movw/b/bu R,R<<[IR](R) -> str indexed */ if p.To.Reg == 0 { -- cgit v1.3