From c0f02c11fff439cf3a99dfca34698b583bb3ce48 Mon Sep 17 00:00:00 2001 From: Xiaolin Zhao Date: Tue, 18 Nov 2025 16:00:35 +0800 Subject: cmd/internal/obj/loong64: add aliases to 32-bit arithmetic instructions Both the MULW and MUL instructions point to the mul.w instruction in the loong64 ISA. Previously, MULW was not encoded; now it is encoded and used as an alias for MUL. The same applies to the following instructions: ADD, SUB, DIV. For consistency, we have added additional aliases for DIVU, REM and REMU. Change-Id: Iba201a3c4c2893ff7d301ef877fad9c81e54291b Reviewed-on: https://go-review.googlesource.com/c/go/+/721523 Reviewed-by: Cherry Mui Auto-Submit: abner chenc Reviewed-by: abner chenc Reviewed-by: Meidan Li Reviewed-by: Dmitri Shuralyov LUCI-TryBot-Result: Go LUCI --- src/cmd/asm/internal/asm/testdata/loong64enc1.s | 16 ++++++++++++++++ src/cmd/asm/internal/asm/testdata/loong64enc2.s | 4 ++++ src/cmd/asm/internal/asm/testdata/loong64enc3.s | 4 ++++ 3 files changed, 24 insertions(+) (limited to 'src/cmd/asm/internal') diff --git a/src/cmd/asm/internal/asm/testdata/loong64enc1.s b/src/cmd/asm/internal/asm/testdata/loong64enc1.s index fc6e277416..20fd014434 100644 --- a/src/cmd/asm/internal/asm/testdata/loong64enc1.s +++ b/src/cmd/asm/internal/asm/testdata/loong64enc1.s @@ -33,13 +33,17 @@ lable2: MOVV R4, R5 // 85001500 MOVBU R4, R5 // 85fc4303 SUB R4, R5, R6 // a6101100 + SUBW R4, R5, R6 // a6101100 SUBV R4, R5, R6 // a6901100 ADD R4, R5, R6 // a6101000 + ADDW R4, R5, R6 // a6101000 ADDV R4, R5, R6 // a6901000 AND R4, R5, R6 // a6901400 SUB R4, R5 // a5101100 + SUBW R4, R5 // a5101100 SUBV R4, R5 // a5901100 ADD R4, R5 // a5101000 + ADDW R4, R5 // a5101000 ADDV R4, R5 // a5901000 AND R4, R5 // a5901400 NEGW R4, R5 // 05101100 @@ -115,6 +119,8 @@ lable2: MOVV $1, R4 // 04048003 ADD $-1, R4, R5 // 85fcbf02 ADD $-1, R4 // 84fcbf02 + ADDW $-1, R4, R5 // 85fcbf02 + ADDW $-1, R4 // 84fcbf02 ADDV $-1, R4, R5 // 85fcff02 ADDV $-1, R4 // 84fcff02 AND $1, R4, R5 // 85044003 @@ -165,6 +171,8 @@ lable2: // mul MUL R4, R5 // a5101c00 MUL R4, R5, R6 // a6101c00 + MULW R4, R5 // a5101c00 + MULW R4, R5, R6 // a6101c00 MULV R4, R5 // a5901d00 MULV R4, R5, R6 // a6901d00 MULVU R4, R5 // a5901d00 @@ -199,12 +207,20 @@ lable2: MULHU R4, R5, R6 // a6101d00 REM R4, R5 // a5902000 REM R4, R5, R6 // a6902000 + REMW R4, R5 // a5902000 + REMW R4, R5, R6 // a6902000 REMU R4, R5 // a5902100 REMU R4, R5, R6 // a6902100 + REMWU R4, R5 // a5902100 + REMWU R4, R5, R6 // a6902100 DIV R4, R5 // a5102000 DIV R4, R5, R6 // a6102000 + DIVW R4, R5 // a5102000 + DIVW R4, R5, R6 // a6102000 DIVU R4, R5 // a5102100 DIVU R4, R5, R6 // a6102100 + DIVWU R4, R5 // a5102100 + DIVWU R4, R5, R6 // a6102100 SRLV R4, R5 // a5101900 SRLV R4, R5, R6 // a6101900 SRLV $4, R4, R5 // 85104500 diff --git a/src/cmd/asm/internal/asm/testdata/loong64enc2.s b/src/cmd/asm/internal/asm/testdata/loong64enc2.s index 91aed4e2c7..0ac85f3225 100644 --- a/src/cmd/asm/internal/asm/testdata/loong64enc2.s +++ b/src/cmd/asm/internal/asm/testdata/loong64enc2.s @@ -21,6 +21,10 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$0 ADD $4096, R4, R5 // 3e00001485781000 ADD $65536, R4 // 1e02001484781000 ADD $4096, R4 // 3e00001484781000 + ADDW $65536, R4, R5 // 1e02001485781000 + ADDW $4096, R4, R5 // 3e00001485781000 + ADDW $65536, R4 // 1e02001484781000 + ADDW $4096, R4 // 3e00001484781000 ADDV $65536, R4, R5 // 1e02001485f81000 ADDV $4096, R4, R5 // 3e00001485f81000 ADDV $65536, R4 // 1e02001484f81000 diff --git a/src/cmd/asm/internal/asm/testdata/loong64enc3.s b/src/cmd/asm/internal/asm/testdata/loong64enc3.s index 2dc6529dcb..c8fb1acb39 100644 --- a/src/cmd/asm/internal/asm/testdata/loong64enc3.s +++ b/src/cmd/asm/internal/asm/testdata/loong64enc3.s @@ -11,12 +11,16 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$0 MOVV $4096(R4), R5 // 3e000014de03800385f81000 ADD $74565, R4 // 5e020014de178d0384781000 ADD $4097, R4 // 3e000014de07800384781000 + ADDW $74565, R4 // 5e020014de178d0384781000 + ADDW $4097, R4 // 3e000014de07800384781000 ADDV $74565, R4 // 5e020014de178d0384f81000 ADDV $4097, R4 // 3e000014de07800384f81000 AND $74565, R4 // 5e020014de178d0384f81400 AND $4097, R4 // 3e000014de07800384f81400 ADD $74565, R4, R5 // 5e020014de178d0385781000 ADD $4097, R4, R5 // 3e000014de07800385781000 + ADDW $74565, R4, R5 // 5e020014de178d0385781000 + ADDW $4097, R4, R5 // 3e000014de07800385781000 ADDV $74565, R4, R5 // 5e020014de178d0385f81000 ADDV $4097, R4, R5 // 3e000014de07800385f81000 AND $74565, R4, R5 // 5e020014de178d0385f81400 -- cgit v1.3-5-g9baa