From 14685c05aae4e87c455f8489258ad9ee13b0273c Mon Sep 17 00:00:00 2001 From: Junyang Shao Date: Wed, 8 Apr 2026 22:08:30 +0000 Subject: cmd/asm, cmd/internal/obj/arm64: support memory with extensions in SVE This CL is generated by CL 764800. Supported addressing patterns: (Z7.D.SXTW<<2)(Z6.D), where Z6.D is the base, Z7.D is the indices. SXTW/UXTW represents signed/unsigned extension, << represents LSL. Change-Id: Ifc6c47833d5113be7cfe96943d369ab977b3a6ee Reviewed-on: https://go-review.googlesource.com/c/go/+/764780 Reviewed-by: David Chase LUCI-TryBot-Result: golang-scoped@luci-project-accounts.iam.gserviceaccount.com Commit-Queue: Junyang Shao --- src/cmd/asm/internal/asm/parse.go | 125 + src/cmd/asm/internal/asm/testdata/arm64sveenc.s | 184 + src/cmd/asm/internal/asm/testdata/arm64sveerror.s | 184 + src/cmd/internal/obj/arm64/anames_gen.go | 70 + src/cmd/internal/obj/arm64/asm7.go | 6 +- src/cmd/internal/obj/arm64/encoding_gen.go | 472 +- src/cmd/internal/obj/arm64/goops_gen.go | 70 + src/cmd/internal/obj/arm64/inst.go | 40 +- src/cmd/internal/obj/arm64/inst_gen.go | 9270 +++++++++++++-------- src/cmd/internal/obj/util.go | 41 +- 10 files changed, 7014 insertions(+), 3448 deletions(-) diff --git a/src/cmd/asm/internal/asm/parse.go b/src/cmd/asm/internal/asm/parse.go index bf3bc033bc..38acb47afc 100644 --- a/src/cmd/asm/internal/asm/parse.go +++ b/src/cmd/asm/internal/asm/parse.go @@ -971,8 +971,133 @@ func (p *Parser) registerIndirect(a *obj.Addr, prefix rune) { if !ok { p.errorf("indirect through non-register %s", tok) } + // SVE extended addressing support + var ext string + var mod int64 + var amount int64 + isSVEMemExt := false + + if p.arch.Family == sys.ARM64 && (p.peek() == '.' || p.peek() == lex.LSH) { + // The index is a vector register, or contains a shift, then this is SVE extended addressing. + isSVEMemExt = true + if p.peek() == '.' { + p.get('.') + tok2 := p.next() + str := tok2.String() + if str == "UXTW" || str == "SXTW" { + switch str { + case "UXTW": + mod = 1 + case "SXTW": + mod = 2 + } + } else { + ext = str + if p.peek() == '.' { + p.get('.') + tok3 := p.next() + modStr := tok3.String() + switch modStr { + case "UXTW": + mod = 1 + case "SXTW": + mod = 2 + default: + p.errorf("unknown modifier %s", modStr) + } + } + } + } + if p.peek() == lex.LSH { + p.get(lex.LSH) + tok4 := p.get(scanner.Int) + amount, _ = strconv.ParseInt(tok4.String(), 10, 16) + } + } p.get(')') a.Type = obj.TYPE_MEM + + if isSVEMemExt { + encodedR1 := r1 + if ext != "" { + if r1 >= arm64.REG_Z0 && r1 <= arm64.REG_Z31 { + var arng int + switch ext { + case "B": + arng = arm64.ARNG_B + case "H": + arng = arm64.ARNG_H + case "S": + arng = arm64.ARNG_S + case "D": + arng = arm64.ARNG_D + case "Q": + arng = arm64.ARNG_Q + default: + p.errorf("unknown arrangement %s", ext) + } + if arng != 0 { + encodedR1 = arm64.REG_ZARNG + (r1 & 31) + int16((arng&15)<<5) + } + } else { + p.errorf("arrangement not allowed for this register") + } + } + + if p.peek() != '(' { + p.errorf("expected second parenthesis for SVE extended addressing") + return + } + p.get('(') + tok5 := p.next() + r2, ok := p.registerReference(tok5.String()) + if !ok { + p.errorf("expected register") + } + var ext2 string + if p.peek() == '.' { + p.get('.') + tok6 := p.next() + ext2 = tok6.String() + } + p.get(')') + + encodedR2 := r2 + if ext2 != "" { + if r2 >= arm64.REG_Z0 && r2 <= arm64.REG_Z31 { + var arng int + switch ext2 { + case "B": + arng = arm64.ARNG_B + case "H": + arng = arm64.ARNG_H + case "S": + arng = arm64.ARNG_S + case "D": + arng = arm64.ARNG_D + case "Q": + arng = arm64.ARNG_Q + default: + p.errorf("unknown arrangement %s", ext2) + } + if arng != 0 { + encodedR2 = arm64.REG_ZARNG + (r2 & 31) + int16((arng&15)<<5) + } + } else { + p.errorf("arrangement not allowed for this register") + } + } + + a.Index = encodedR2 // Base + a.Reg = encodedR1 // Index + a.Offset = 0 // Ensure offset is 0 + + var scaleValue int16 = -32768 // Bit 15 set + scaleValue |= int16(amount << 12) + scaleValue |= int16(mod << 9) + a.Scale = scaleValue + return + } if r1 < 0 { // Pseudo-register reference. if r2 != 0 { diff --git a/src/cmd/asm/internal/asm/testdata/arm64sveenc.s b/src/cmd/asm/internal/asm/testdata/arm64sveenc.s index 4a50cac41d..53e0a26931 100644 --- a/src/cmd/asm/internal/asm/testdata/arm64sveenc.s +++ b/src/cmd/asm/internal/asm/testdata/arm64sveenc.s @@ -937,4 +937,188 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$-8 // TODO: LUTI6 ZSPLICE [Z7.D, Z8.D], P4, Z13.D // ed90ed05 ZTBLQ Z7.D, [Z23.D], Z13.D // edfac744 + ZADR (Z16.S)(Z12.S), Z13.S // 8da1b004 + ZADR (Z7.D.SXTW<<2)(Z6.D), Z23.D // d7a82704 + ZADR (Z7.D.UXTW<<2)(Z6.D), Z23.D // d7a86704 + ZLD1B (R6)(R14), P4.Z, [Z13.B] // cd5106a4 + ZLD1B (R6)(R14), P4.Z, [Z13.H] // cd5126a4 + ZLD1B (R6)(R14), P4.Z, [Z13.S] // cd5146a4 + ZLD1B (R6)(R14), P4.Z, [Z13.D] // cd5166a4 + ZLD1B (Z10.D)(R19), P3.Z, [Z15.D] // 6fce4ac4 + ZLD1B (Z4.S.UXTW)(R3), P3.Z, [Z4.S] // 644c0484 + ZLD1B (Z6.D)(R14), P4.Z, [Z13.D] // cdd146c4 + ZLD1D (Z23.D<<3)(R24), P1.Z, [Z22.D] // 16c7f7c5 + ZLD1D (Z10.D)(R19), P3.Z, [Z15.D] // 6fcecac5 + ZLD1D (Z6.D<<3)(R14), P4.Z, [Z13.D] // cdd1e6c5 + ZLD1D (Z6.D)(R14), P4.Z, [Z13.D] // cdd1c6c5 + ZLD1H (R6<<1)(R14), P4.Z, [Z13.H] // cd51a6a4 + ZLD1H (R6<<1)(R14), P4.Z, [Z13.S] // cd51c6a4 + ZLD1H (R6<<1)(R14), P4.Z, [Z13.D] // cd51e6a4 + ZLD1H (Z4.S.UXTW<<1)(R3), P3.Z, [Z4.S] // 644ca484 + ZLD1H (Z23.D<<1)(R24), P1.Z, [Z22.D] // 16c7f7c4 + ZLD1H (Z10.D)(R19), P3.Z, [Z15.D] // 6fcecac4 + ZLD1H (Z4.S.UXTW)(R3), P3.Z, [Z4.S] // 644c8484 + ZLD1H (Z6.D<<1)(R14), P4.Z, [Z13.D] // cdd1e6c4 + ZLD1H (Z6.D)(R14), P4.Z, [Z13.D] // cdd1c6c4 + ZLD1Q (R6)(Z7.D), P4.Z, [Z13.Q] // edb006c4 + ZLD1ROB (R6)(R14), P4.Z, [Z13.B] // cd1126a4 + ZLD1ROD (R6<<3)(R14), P4.Z, [Z13.D] // cd11a6a5 + ZLD1ROH (R6<<1)(R14), P4.Z, [Z13.H] // cd11a6a4 + ZLD1ROW (R6<<2)(R14), P4.Z, [Z13.S] // cd1126a5 + ZLD1RQB (R6)(R14), P4.Z, [Z13.B] // cd1106a4 + ZLD1RQD (R6<<3)(R14), P4.Z, [Z13.D] // cd1186a5 + ZLD1RQH (R6<<1)(R14), P4.Z, [Z13.H] // cd1186a4 + ZLD1RQW (R6<<2)(R14), P4.Z, [Z13.S] // cd1106a5 + ZLD1SB (R6)(R14), P4.Z, [Z13.H] // cd51c6a5 + ZLD1SB (R6)(R14), P4.Z, [Z13.S] // cd51a6a5 + ZLD1SB (R6)(R14), P4.Z, [Z13.D] // cd5186a5 + ZLD1SB (Z10.D)(R19), P3.Z, [Z15.D] // 6f8e4ac4 + ZLD1SB (Z4.S.UXTW)(R3), P3.Z, [Z4.S] // 640c0484 + ZLD1SB (Z6.D)(R14), P4.Z, [Z13.D] // cd9146c4 + ZLD1SH (R6<<1)(R14), P4.Z, [Z13.S] // cd5126a5 + ZLD1SH (R6<<1)(R14), P4.Z, [Z13.D] // cd5106a5 + ZLD1SH (Z4.S.UXTW<<1)(R3), P3.Z, [Z4.S] // 640ca484 + ZLD1SH (Z23.D<<1)(R24), P1.Z, [Z22.D] // 1687f7c4 + ZLD1SH (Z10.D)(R19), P3.Z, [Z15.D] // 6f8ecac4 + ZLD1SH (Z4.S.UXTW)(R3), P3.Z, [Z4.S] // 640c8484 + ZLD1SH (Z6.D<<1)(R14), P4.Z, [Z13.D] // cd91e6c4 + ZLD1SH (Z6.D)(R14), P4.Z, [Z13.D] // cd91c6c4 + ZLD1SW (R6<<2)(R14), P4.Z, [Z13.D] // cd5186a4 + ZLD1SW (Z23.D<<2)(R24), P1.Z, [Z22.D] // 168777c5 + ZLD1SW (Z10.D)(R19), P3.Z, [Z15.D] // 6f8e4ac5 + ZLD1SW (Z6.D<<2)(R14), P4.Z, [Z13.D] // cd9166c5 + ZLD1SW (Z6.D)(R14), P4.Z, [Z13.D] // cd9146c5 + ZLD1W (Z4.S.UXTW<<2)(R3), P3.Z, [Z4.S] // 644c2485 + ZLD1W (Z23.D<<2)(R24), P1.Z, [Z22.D] // 16c777c5 + ZLD1W (Z10.D)(R19), P3.Z, [Z15.D] // 6fce4ac5 + ZLD1W (Z4.S.UXTW)(R3), P3.Z, [Z4.S] // 644c0485 + ZLD1W (Z6.D<<2)(R14), P4.Z, [Z13.D] // cdd166c5 + ZLD1W (Z6.D)(R14), P4.Z, [Z13.D] // cdd146c5 + ZLD2B (R6)(R14), P4.Z, [Z13.B, Z14.B] // cdd126a4 + ZLD2D (R6<<3)(R14), P4.Z, [Z13.D, Z14.D] // cdd1a6a5 + ZLD2H (R6<<1)(R14), P4.Z, [Z13.H, Z14.H] // cdd1a6a4 + ZLD2Q (R6<<4)(R14), P4.Z, [Z13.Q, Z14.Q] // cd91a6a4 + ZLD2W (R6<<2)(R14), P4.Z, [Z13.S, Z14.S] // cdd126a5 + ZLD3B (R6)(R14), P4.Z, [Z13.B, Z14.B, Z15.B] // cdd146a4 + ZLD3D (R6<<3)(R14), P4.Z, [Z13.D, Z14.D, Z15.D] // cdd1c6a5 + ZLD3H (R6<<1)(R14), P4.Z, [Z13.H, Z14.H, Z15.H] // cdd1c6a4 + ZLD3Q (R6<<4)(R14), P4.Z, [Z13.Q, Z14.Q, Z15.Q] // cd9126a5 + ZLD3W (R6<<2)(R14), P4.Z, [Z13.S, Z14.S, Z15.S] // cdd146a5 + ZLD4B (R6)(R14), P4.Z, [Z13.B, Z14.B, Z15.B, Z16.B]// cdd166a4 + ZLD4D (R6<<3)(R14), P4.Z, [Z13.D, Z14.D, Z15.D, Z16.D]// cdd1e6a5 + ZLD4H (R6<<1)(R14), P4.Z, [Z13.H, Z14.H, Z15.H, Z16.H]// cdd1e6a4 + ZLD4Q (R6<<4)(R14), P4.Z, [Z13.Q, Z14.Q, Z15.Q, Z16.Q]// cd91a6a5 + ZLD4W (R6<<2)(R14), P4.Z, [Z13.S, Z14.S, Z15.S, Z16.S]// cdd166a5 + ZLDFF1B (R6)(R14), P4.Z, [Z13.B] // cd7106a4 + ZLDFF1B (R6)(R14), P4.Z, [Z13.H] // cd7126a4 + ZLDFF1B (R6)(R14), P4.Z, [Z13.S] // cd7146a4 + ZLDFF1B (R6)(R14), P4.Z, [Z13.D] // cd7166a4 + ZLDFF1B (Z10.D)(R19), P3.Z, [Z15.D] // 6fee4ac4 + ZLDFF1B (Z4.S.UXTW)(R3), P3.Z, [Z4.S] // 646c0484 + ZLDFF1B (Z6.D)(R14), P4.Z, [Z13.D] // cdf146c4 + ZLDFF1D (R6<<3)(R14), P4.Z, [Z13.D] // cd71e6a5 + ZLDFF1D (Z23.D<<3)(R24), P1.Z, [Z22.D] // 16e7f7c5 + ZLDFF1D (Z10.D)(R19), P3.Z, [Z15.D] // 6feecac5 + ZLDFF1D (Z6.D<<3)(R14), P4.Z, [Z13.D] // cdf1e6c5 + ZLDFF1D (Z6.D)(R14), P4.Z, [Z13.D] // cdf1c6c5 + ZLDFF1H (R6<<1)(R14), P4.Z, [Z13.H] // cd71a6a4 + ZLDFF1H (R6<<1)(R14), P4.Z, [Z13.S] // cd71c6a4 + ZLDFF1H (R6<<1)(R14), P4.Z, [Z13.D] // cd71e6a4 + ZLDFF1H (Z4.S.UXTW<<1)(R3), P3.Z, [Z4.S] // 646ca484 + ZLDFF1H (Z23.D<<1)(R24), P1.Z, [Z22.D] // 16e7f7c4 + ZLDFF1H (Z10.D)(R19), P3.Z, [Z15.D] // 6feecac4 + ZLDFF1H (Z4.S.UXTW)(R3), P3.Z, [Z4.S] // 646c8484 + ZLDFF1H (Z6.D<<1)(R14), P4.Z, [Z13.D] // cdf1e6c4 + ZLDFF1H (Z6.D)(R14), P4.Z, [Z13.D] // cdf1c6c4 + ZLDFF1SB (R6)(R14), P4.Z, [Z13.H] // cd71c6a5 + ZLDFF1SB (R6)(R14), P4.Z, [Z13.S] // cd71a6a5 + ZLDFF1SB (R6)(R14), P4.Z, [Z13.D] // cd7186a5 + ZLDFF1SB (Z10.D)(R19), P3.Z, [Z15.D] // 6fae4ac4 + ZLDFF1SB (Z4.S.UXTW)(R3), P3.Z, [Z4.S] // 642c0484 + ZLDFF1SB (Z6.D)(R14), P4.Z, [Z13.D] // cdb146c4 + ZLDFF1SH (R6<<1)(R14), P4.Z, [Z13.S] // cd7126a5 + ZLDFF1SH (R6<<1)(R14), P4.Z, [Z13.D] // cd7106a5 + ZLDFF1SH (Z4.S.UXTW<<1)(R3), P3.Z, [Z4.S] // 642ca484 + ZLDFF1SH (Z23.D<<1)(R24), P1.Z, [Z22.D] // 16a7f7c4 + ZLDFF1SH (Z10.D)(R19), P3.Z, [Z15.D] // 6faecac4 + ZLDFF1SH (Z4.S.UXTW)(R3), P3.Z, [Z4.S] // 642c8484 + ZLDFF1SH (Z6.D<<1)(R14), P4.Z, [Z13.D] // cdb1e6c4 + ZLDFF1SH (Z6.D)(R14), P4.Z, [Z13.D] // cdb1c6c4 + ZLDFF1SW (R6<<2)(R14), P4.Z, [Z13.D] // cd7186a4 + ZLDFF1SW (Z23.D<<2)(R24), P1.Z, [Z22.D] // 16a777c5 + ZLDFF1SW (Z10.D)(R19), P3.Z, [Z15.D] // 6fae4ac5 + ZLDFF1SW (Z6.D<<2)(R14), P4.Z, [Z13.D] // cdb166c5 + ZLDFF1SW (Z6.D)(R14), P4.Z, [Z13.D] // cdb146c5 + ZLDFF1W (R6<<2)(R14), P4.Z, [Z13.S] // cd7146a5 + ZLDFF1W (R6<<2)(R14), P4.Z, [Z13.D] // cd7166a5 + ZLDFF1W (Z4.S.UXTW<<2)(R3), P3.Z, [Z4.S] // 646c2485 + ZLDFF1W (Z23.D<<2)(R24), P1.Z, [Z22.D] // 16e777c5 + ZLDFF1W (Z10.D)(R19), P3.Z, [Z15.D] // 6fee4ac5 + ZLDFF1W (Z4.S.UXTW)(R3), P3.Z, [Z4.S] // 646c0485 + ZLDFF1W (Z6.D<<2)(R14), P4.Z, [Z13.D] // cdf166c5 + ZLDFF1W (Z6.D)(R14), P4.Z, [Z13.D] // cdf146c5 + ZLDNT1B (R6)(R14), P4.Z, [Z13.B] // cdd106a4 + ZLDNT1B (R6)(Z7.S), P4.Z, [Z13.S] // edb00684 + ZLDNT1B (R6)(Z7.D), P4.Z, [Z13.D] // edd006c4 + ZLDNT1D (R6<<3)(R14), P4.Z, [Z13.D] // cdd186a5 + ZLDNT1D (R6)(Z7.D), P4.Z, [Z13.D] // edd086c5 + ZLDNT1H (R6<<1)(R14), P4.Z, [Z13.H] // cdd186a4 + ZLDNT1H (R6)(Z7.S), P4.Z, [Z13.S] // edb08684 + ZLDNT1H (R6)(Z7.D), P4.Z, [Z13.D] // edd086c4 + ZLDNT1SB (R6)(Z7.S), P4.Z, [Z13.S] // ed900684 + ZLDNT1SB (R6)(Z7.D), P4.Z, [Z13.D] // ed9006c4 + ZLDNT1SH (R6)(Z7.S), P4.Z, [Z13.S] // ed908684 + ZLDNT1SH (R6)(Z7.D), P4.Z, [Z13.D] // ed9086c4 + ZLDNT1SW (R6)(Z7.D), P4.Z, [Z13.D] // ed9006c5 + ZLDNT1W (R6<<2)(R14), P4.Z, [Z13.S] // cdd106a5 + ZLDNT1W (R6)(Z7.S), P4.Z, [Z13.S] // edb00685 + ZLDNT1W (R6)(Z7.D), P4.Z, [Z13.D] // edd006c5 + ZST1B (R6)(R14), P4, [Z13.B] // cd5106e4 + ZST1B (Z10.D)(R19), P3, [Z15.D] // 6fae0ae4 + ZST1B (Z4.S.UXTW)(R3), P3, [Z4.S] // 648c44e4 + ZST1B (Z6.D)(R14), P4, [Z13.D] // cdb106e4 + ZST1D (Z23.D<<3)(R24), P1, [Z22.D] // 16a7b7e5 + ZST1D (Z10.D)(R19), P3, [Z15.D] // 6fae8ae5 + ZST1D (Z6.D<<3)(R14), P4, [Z13.D] // cdb1a6e5 + ZST1D (Z6.D)(R14), P4, [Z13.D] // cdb186e5 + ZST1H (R6<<1)(RSP), P1, [Z12.S] // ec47c6e4 + ZST1H (Z4.S.UXTW<<1)(R3), P3, [Z4.S] // 648ce4e4 + ZST1H (Z23.D<<1)(R24), P1, [Z22.D] // 16a7b7e4 + ZST1H (Z10.D)(R19), P3, [Z15.D] // 6fae8ae4 + ZST1H (Z4.S.UXTW)(R3), P3, [Z4.S] // 648cc4e4 + ZST1H (Z6.D<<1)(R14), P4, [Z13.D] // cdb1a6e4 + ZST1H (Z6.D)(R14), P4, [Z13.D] // cdb186e4 + ZST1Q (R6)(Z7.D), P4, [Z13.Q] // ed3026e4 + ZST1W (Z4.S.UXTW<<2)(R3), P3, [Z4.S] // 648c64e5 + ZST1W (Z23.D<<2)(R24), P1, [Z22.D] // 16a737e5 + ZST1W (Z10.D)(R19), P3, [Z15.D] // 6fae0ae5 + ZST1W (Z4.S.UXTW)(R3), P3, [Z4.S] // 648c44e5 + ZST1W (Z6.D<<2)(R14), P4, [Z13.D] // cdb126e5 + ZST1W (Z6.D)(R14), P4, [Z13.D] // cdb106e5 + ZST2B (R6)(R14), P4, [Z13.B, Z14.B] // cd7126e4 + ZST2D (R6<<3)(R14), P4, [Z13.D, Z14.D] // cd71a6e5 + ZST2H (R6<<1)(R14), P4, [Z13.H, Z14.H] // cd71a6e4 + ZST2Q (R6<<4)(R14), P4, [Z13.Q, Z14.Q] // cd1166e4 + ZST2W (R6<<2)(R14), P4, [Z13.S, Z14.S] // cd7126e5 + ZST3B (R6)(R14), P4, [Z13.B, Z14.B, Z15.B] // cd7146e4 + ZST3D (R6<<3)(R14), P4, [Z13.D, Z14.D, Z15.D] // cd71c6e5 + ZST3H (R6<<1)(R14), P4, [Z13.H, Z14.H, Z15.H] // cd71c6e4 + ZST3Q (R6<<4)(R14), P4, [Z13.Q, Z14.Q, Z15.Q] // cd11a6e4 + ZST3W (R6<<2)(R14), P4, [Z13.S, Z14.S, Z15.S] // cd7146e5 + ZST4B (R6)(R14), P4, [Z13.B, Z14.B, Z15.B, Z16.B] // cd7166e4 + ZST4D (R6<<3)(R14), P4, [Z13.D, Z14.D, Z15.D, Z16.D]// cd71e6e5 + ZST4H (R6<<1)(R14), P4, [Z13.H, Z14.H, Z15.H, Z16.H]// cd71e6e4 + ZST4Q (R6<<4)(R14), P4, [Z13.Q, Z14.Q, Z15.Q, Z16.Q]// cd11e6e4 + ZST4W (R6<<2)(R14), P4, [Z13.S, Z14.S, Z15.S, Z16.S]// cd7166e5 + ZSTNT1B (R6)(R14), P4, [Z13.B] // cd7106e4 + ZSTNT1B (R6)(Z7.S), P4, [Z13.S] // ed3046e4 + ZSTNT1B (R6)(Z7.D), P4, [Z13.D] // ed3006e4 + ZSTNT1D (R6<<3)(R14), P4, [Z13.D] // cd7186e5 + ZSTNT1D (R6)(Z7.D), P4, [Z13.D] // ed3086e5 + ZSTNT1H (R6<<1)(R14), P4, [Z13.H] // cd7186e4 + ZSTNT1H (R6)(Z7.S), P4, [Z13.S] // ed30c6e4 + ZSTNT1H (R6)(Z7.D), P4, [Z13.D] // ed3086e4 + ZSTNT1W (R6<<2)(R14), P4, [Z13.S] // cd7106e5 + ZSTNT1W (R6)(Z7.S), P4, [Z13.S] // ed3046e5 + ZSTNT1W (R6)(Z7.D), P4, [Z13.D] // ed3006e5 RET diff --git a/src/cmd/asm/internal/asm/testdata/arm64sveerror.s b/src/cmd/asm/internal/asm/testdata/arm64sveerror.s index 0a7069ae69..848cab0f59 100644 --- a/src/cmd/asm/internal/asm/testdata/arm64sveerror.s +++ b/src/cmd/asm/internal/asm/testdata/arm64sveerror.s @@ -936,4 +936,188 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$-8 // TODO: LUTI6 ZSPLICE [Z1.S, Z2.S], P13.Z, Z11.B // ERROR "illegal combination from SVE" ZTBLQ Z1.S, [Z26.S], Z11.B // ERROR "illegal combination from SVE" + ZADR (Z26.S.SXTW<<1)(Z1.S), Z7.D // ERROR "illegal combination from SVE" + ZADR (Z27.D.SXTW<<3)(Z1.D), Z25.Q // ERROR "illegal combination from SVE" + ZADR (Z27.D.UXTW<<3)(Z1.D), Z25.Q // ERROR "illegal combination from SVE" + ZLD1B (R27)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1B (R27)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1B (R27)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1B (R27)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1B (Z27.D.UXTW)(RSP), P7.Z, [Z6.H] // ERROR "illegal combination from SVE" + ZLD1B (Z27.S.UXTW)(RSP), P7.Z, [Z6.H] // ERROR "illegal combination from SVE" + ZLD1B (Z27.D)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1D (Z27.D.UXTW<<3)(RSP), P7.Z, [Z6.H] // ERROR "illegal combination from SVE" + ZLD1D (Z27.D.UXTW)(RSP), P7.Z, [Z6.H] // ERROR "illegal combination from SVE" + ZLD1D (Z27.D<<3)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1D (Z27.D)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1H (R27<<1)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1H (R27<<1)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1H (R27<<1)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1H (Z27.S.UXTW<<1)(RSP), P7.Z, [Z6.H] // ERROR "illegal combination from SVE" + ZLD1H (Z27.D.UXTW<<1)(RSP), P7.Z, [Z6.H] // ERROR "illegal combination from SVE" + ZLD1H (Z27.D.UXTW)(RSP), P7.Z, [Z6.H] // ERROR "illegal combination from SVE" + ZLD1H (Z27.S.UXTW)(RSP), P7.Z, [Z6.H] // ERROR "illegal combination from SVE" + ZLD1H (Z27.D<<1)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1H (Z27.D)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1Q (R27)(Z1.D), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1ROB (R27)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1ROD (R27<<3)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1ROH (R27<<1)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1ROW (R27<<2)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1RQB (R27)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1RQD (R27<<3)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1RQH (R27<<1)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1RQW (R27<<2)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1SB (R27)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1SB (R27)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1SB (R27)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1SB (Z27.D.UXTW)(RSP), P7.Z, [Z6.H] // ERROR "illegal combination from SVE" + ZLD1SB (Z27.S.UXTW)(RSP), P7.Z, [Z6.H] // ERROR "illegal combination from SVE" + ZLD1SB (Z27.D)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1SH (R27<<1)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1SH (R27<<1)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1SH (Z27.S.UXTW<<1)(RSP), P7.Z, [Z6.H] // ERROR "illegal combination from SVE" + ZLD1SH (Z27.D.UXTW<<1)(RSP), P7.Z, [Z6.H] // ERROR "illegal combination from SVE" + ZLD1SH (Z27.D.UXTW)(RSP), P7.Z, [Z6.H] // ERROR "illegal combination from SVE" + ZLD1SH (Z27.S.UXTW)(RSP), P7.Z, [Z6.H] // ERROR "illegal combination from SVE" + ZLD1SH (Z27.D<<1)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1SH (Z27.D)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1SW (R27<<2)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1SW (Z27.D.UXTW<<2)(RSP), P7.Z, [Z6.H] // ERROR "illegal combination from SVE" + ZLD1SW (Z27.D.UXTW)(RSP), P7.Z, [Z6.H] // ERROR "illegal combination from SVE" + ZLD1SW (Z27.D<<2)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1SW (Z27.D)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1W (Z27.S.UXTW<<2)(RSP), P7.Z, [Z6.H] // ERROR "illegal combination from SVE" + ZLD1W (Z27.D.UXTW<<2)(RSP), P7.Z, [Z6.H] // ERROR "illegal combination from SVE" + ZLD1W (Z27.D.UXTW)(RSP), P7.Z, [Z6.H] // ERROR "illegal combination from SVE" + ZLD1W (Z27.S.UXTW)(RSP), P7.Z, [Z6.H] // ERROR "illegal combination from SVE" + ZLD1W (Z27.D<<2)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD1W (Z27.D)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLD2B (R27)(RSP), P13.Z, [Z11.B, Z12.B] // ERROR "illegal combination from SVE" + ZLD2D (R27<<3)(RSP), P13.Z, [Z11.B, Z12.B] // ERROR "illegal combination from SVE" + ZLD2H (R27<<1)(RSP), P13.Z, [Z11.B, Z12.B] // ERROR "illegal combination from SVE" + ZLD2Q (R27<<4)(RSP), P13.Z, [Z11.B, Z12.B] // ERROR "illegal combination from SVE" + ZLD2W (R27<<2)(RSP), P13.Z, [Z11.B, Z12.B] // ERROR "illegal combination from SVE" + ZLD3B (R27)(RSP), P13.Z, [Z11.B, Z12.B, Z13.B] // ERROR "illegal combination from SVE" + ZLD3D (R27<<3)(RSP), P13.Z, [Z11.B, Z12.B, Z13.B] // ERROR "illegal combination from SVE" + ZLD3H (R27<<1)(RSP), P13.Z, [Z11.B, Z12.B, Z13.B] // ERROR "illegal combination from SVE" + ZLD3Q (R27<<4)(RSP), P13.Z, [Z11.B, Z12.B, Z13.B] // ERROR "illegal combination from SVE" + ZLD3W (R27<<2)(RSP), P13.Z, [Z11.B, Z12.B, Z13.B] // ERROR "illegal combination from SVE" + ZLD4B (R27)(RSP), P13.Z, [Z11.B, Z12.B, Z13.B, Z14.B]// ERROR "illegal combination from SVE" + ZLD4D (R27<<3)(RSP), P13.Z, [Z11.B, Z12.B, Z13.B, Z14.B]// ERROR "illegal combination from SVE" + ZLD4H (R27<<1)(RSP), P13.Z, [Z11.B, Z12.B, Z13.B, Z14.B]// ERROR "illegal combination from SVE" + ZLD4Q (R27<<4)(RSP), P13.Z, [Z11.B, Z12.B, Z13.B, Z14.B]// ERROR "illegal combination from SVE" + ZLD4W (R27<<2)(RSP), P13.Z, [Z11.B, Z12.B, Z13.B, Z14.B]// ERROR "illegal combination from SVE" + ZLDFF1B (R27)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDFF1B (R27)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDFF1B (R27)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDFF1B (R27)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDFF1B (Z27.D.UXTW)(RSP), P7.Z, [Z6.H] // ERROR "illegal combination from SVE" + ZLDFF1B (Z27.S.UXTW)(RSP), P7.Z, [Z6.H] // ERROR "illegal combination from SVE" + ZLDFF1B (Z27.D)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDFF1D (R27<<3)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDFF1D (Z27.D.UXTW<<3)(RSP), P7.Z, [Z6.H] // ERROR "illegal combination from SVE" + ZLDFF1D (Z27.D.UXTW)(RSP), P7.Z, [Z6.H] // ERROR "illegal combination from SVE" + ZLDFF1D (Z27.D<<3)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDFF1D (Z27.D)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDFF1H (R27<<1)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDFF1H (R27<<1)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDFF1H (R27<<1)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDFF1H (Z27.S.UXTW<<1)(RSP), P7.Z, [Z6.H] // ERROR "illegal combination from SVE" + ZLDFF1H (Z27.D.UXTW<<1)(RSP), P7.Z, [Z6.H] // ERROR "illegal combination from SVE" + ZLDFF1H (Z27.D.UXTW)(RSP), P7.Z, [Z6.H] // ERROR "illegal combination from SVE" + ZLDFF1H (Z27.S.UXTW)(RSP), P7.Z, [Z6.H] // ERROR "illegal combination from SVE" + ZLDFF1H (Z27.D<<1)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDFF1H (Z27.D)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDFF1SB (R27)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDFF1SB (R27)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDFF1SB (R27)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDFF1SB (Z27.D.UXTW)(RSP), P7.Z, [Z6.H] // ERROR "illegal combination from SVE" + ZLDFF1SB (Z27.S.UXTW)(RSP), P7.Z, [Z6.H] // ERROR "illegal combination from SVE" + ZLDFF1SB (Z27.D)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDFF1SH (R27<<1)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDFF1SH (R27<<1)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDFF1SH (Z27.S.UXTW<<1)(RSP), P7.Z, [Z6.H] // ERROR "illegal combination from SVE" + ZLDFF1SH (Z27.D.UXTW<<1)(RSP), P7.Z, [Z6.H] // ERROR "illegal combination from SVE" + ZLDFF1SH (Z27.D.UXTW)(RSP), P7.Z, [Z6.H] // ERROR "illegal combination from SVE" + ZLDFF1SH (Z27.S.UXTW)(RSP), P7.Z, [Z6.H] // ERROR "illegal combination from SVE" + ZLDFF1SH (Z27.D<<1)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDFF1SH (Z27.D)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDFF1SW (R27<<2)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDFF1SW (Z27.D.UXTW<<2)(RSP), P7.Z, [Z6.H] // ERROR "illegal combination from SVE" + ZLDFF1SW (Z27.D.UXTW)(RSP), P7.Z, [Z6.H] // ERROR "illegal combination from SVE" + ZLDFF1SW (Z27.D<<2)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDFF1SW (Z27.D)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDFF1W (R27<<2)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDFF1W (R27<<2)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDFF1W (Z27.S.UXTW<<2)(RSP), P7.Z, [Z6.H] // ERROR "illegal combination from SVE" + ZLDFF1W (Z27.D.UXTW<<2)(RSP), P7.Z, [Z6.H] // ERROR "illegal combination from SVE" + ZLDFF1W (Z27.D.UXTW)(RSP), P7.Z, [Z6.H] // ERROR "illegal combination from SVE" + ZLDFF1W (Z27.S.UXTW)(RSP), P7.Z, [Z6.H] // ERROR "illegal combination from SVE" + ZLDFF1W (Z27.D<<2)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDFF1W (Z27.D)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDNT1B (R27)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDNT1B (R27)(Z1.S), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDNT1B (R27)(Z1.D), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDNT1D (R27<<3)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDNT1D (R27)(Z1.D), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDNT1H (R27<<1)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDNT1H (R27)(Z1.S), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDNT1H (R27)(Z1.D), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDNT1SB (R27)(Z1.S), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDNT1SB (R27)(Z1.D), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDNT1SH (R27)(Z1.S), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDNT1SH (R27)(Z1.D), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDNT1SW (R27)(Z1.D), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDNT1W (R27<<2)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDNT1W (R27)(Z1.S), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZLDNT1W (R27)(Z1.D), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZST1B (R27)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZST1B (Z27.D.UXTW)(RSP), P7.Z, [Z6.H] // ERROR "illegal combination from SVE" + ZST1B (Z27.S.UXTW)(RSP), P7.Z, [Z6.H] // ERROR "illegal combination from SVE" + ZST1B (Z27.D)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZST1D (Z27.D.UXTW<<3)(RSP), P7.Z, [Z6.H] // ERROR "illegal combination from SVE" + ZST1D (Z27.D.UXTW)(RSP), P7.Z, [Z6.H] // ERROR "illegal combination from SVE" + ZST1D (Z27.D<<3)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZST1D (Z27.D)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZST1H (R27<<1)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZST1H (Z27.S.UXTW<<1)(RSP), P7.Z, [Z6.H] // ERROR "illegal combination from SVE" + ZST1H (Z27.D.UXTW<<1)(RSP), P7.Z, [Z6.H] // ERROR "illegal combination from SVE" + ZST1H (Z27.D.UXTW)(RSP), P7.Z, [Z6.H] // ERROR "illegal combination from SVE" + ZST1H (Z27.S.UXTW)(RSP), P7.Z, [Z6.H] // ERROR "illegal combination from SVE" + ZST1H (Z27.D<<1)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZST1H (Z27.D)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZST1Q (R27)(Z1.D), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZST1W (Z27.S.UXTW<<2)(RSP), P7.Z, [Z6.H] // ERROR "illegal combination from SVE" + ZST1W (Z27.D.UXTW<<2)(RSP), P7.Z, [Z6.H] // ERROR "illegal combination from SVE" + ZST1W (Z27.D.UXTW)(RSP), P7.Z, [Z6.H] // ERROR "illegal combination from SVE" + ZST1W (Z27.S.UXTW)(RSP), P7.Z, [Z6.H] // ERROR "illegal combination from SVE" + ZST1W (Z27.D<<2)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZST1W (Z27.D)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZST2B (R27)(RSP), P13.Z, [Z11.B, Z12.B] // ERROR "illegal combination from SVE" + ZST2D (R27<<3)(RSP), P13.Z, [Z11.B, Z12.B] // ERROR "illegal combination from SVE" + ZST2H (R27<<1)(RSP), P13.Z, [Z11.B, Z12.B] // ERROR "illegal combination from SVE" + ZST2Q (R27<<4)(RSP), P13.Z, [Z11.B, Z12.B] // ERROR "illegal combination from SVE" + ZST2W (R27<<2)(RSP), P13.Z, [Z11.B, Z12.B] // ERROR "illegal combination from SVE" + ZST3B (R27)(RSP), P13.Z, [Z11.B, Z12.B, Z13.B] // ERROR "illegal combination from SVE" + ZST3D (R27<<3)(RSP), P13.Z, [Z11.B, Z12.B, Z13.B] // ERROR "illegal combination from SVE" + ZST3H (R27<<1)(RSP), P13.Z, [Z11.B, Z12.B, Z13.B] // ERROR "illegal combination from SVE" + ZST3Q (R27<<4)(RSP), P13.Z, [Z11.B, Z12.B, Z13.B] // ERROR "illegal combination from SVE" + ZST3W (R27<<2)(RSP), P13.Z, [Z11.B, Z12.B, Z13.B] // ERROR "illegal combination from SVE" + ZST4B (R27)(RSP), P13.Z, [Z11.B, Z12.B, Z13.B, Z14.B]// ERROR "illegal combination from SVE" + ZST4D (R27<<3)(RSP), P13.Z, [Z11.B, Z12.B, Z13.B, Z14.B]// ERROR "illegal combination from SVE" + ZST4H (R27<<1)(RSP), P13.Z, [Z11.B, Z12.B, Z13.B, Z14.B]// ERROR "illegal combination from SVE" + ZST4Q (R27<<4)(RSP), P13.Z, [Z11.B, Z12.B, Z13.B, Z14.B]// ERROR "illegal combination from SVE" + ZST4W (R27<<2)(RSP), P13.Z, [Z11.B, Z12.B, Z13.B, Z14.B]// ERROR "illegal combination from SVE" + ZSTNT1B (R27)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZSTNT1B (R27)(Z1.S), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZSTNT1B (R27)(Z1.D), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZSTNT1D (R27<<3)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZSTNT1D (R27)(Z1.D), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZSTNT1H (R27<<1)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZSTNT1H (R27)(Z1.S), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZSTNT1H (R27)(Z1.D), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZSTNT1W (R27<<2)(RSP), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZSTNT1W (R27)(Z1.S), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" + ZSTNT1W (R27)(Z1.D), P13.Z, [Z11.B] // ERROR "illegal combination from SVE" RET diff --git a/src/cmd/internal/obj/arm64/anames_gen.go b/src/cmd/internal/obj/arm64/anames_gen.go index 0bb768900d..87620b1e10 100644 --- a/src/cmd/internal/obj/arm64/anames_gen.go +++ b/src/cmd/internal/obj/arm64/anames_gen.go @@ -97,6 +97,7 @@ var sveAnames = []string{ "ZADDQP", "ZADDQV", "ZADDSUBP", + "ZADR", "ZAESD", "ZAESE", "ZAESIMC", @@ -327,6 +328,51 @@ var sveAnames = []string{ "ZLASTBH", "ZLASTBS", "ZLASTBW", + "ZLD1B", + "ZLD1D", + "ZLD1H", + "ZLD1Q", + "ZLD1ROB", + "ZLD1ROD", + "ZLD1ROH", + "ZLD1ROW", + "ZLD1RQB", + "ZLD1RQD", + "ZLD1RQH", + "ZLD1RQW", + "ZLD1SB", + "ZLD1SH", + "ZLD1SW", + "ZLD1W", + "ZLD2B", + "ZLD2D", + "ZLD2H", + "ZLD2Q", + "ZLD2W", + "ZLD3B", + "ZLD3D", + "ZLD3H", + "ZLD3Q", + "ZLD3W", + "ZLD4B", + "ZLD4D", + "ZLD4H", + "ZLD4Q", + "ZLD4W", + "ZLDFF1B", + "ZLDFF1D", + "ZLDFF1H", + "ZLDFF1SB", + "ZLDFF1SH", + "ZLDFF1SW", + "ZLDFF1W", + "ZLDNT1B", + "ZLDNT1D", + "ZLDNT1H", + "ZLDNT1SB", + "ZLDNT1SH", + "ZLDNT1SW", + "ZLDNT1W", "ZLSL", "ZLSLR", "ZLSR", @@ -477,6 +523,30 @@ var sveAnames = []string{ "ZSSUBLTB", "ZSSUBWB", "ZSSUBWT", + "ZST1B", + "ZST1D", + "ZST1H", + "ZST1Q", + "ZST1W", + "ZST2B", + "ZST2D", + "ZST2H", + "ZST2Q", + "ZST2W", + "ZST3B", + "ZST3D", + "ZST3H", + "ZST3Q", + "ZST3W", + "ZST4B", + "ZST4D", + "ZST4H", + "ZST4Q", + "ZST4W", + "ZSTNT1B", + "ZSTNT1D", + "ZSTNT1H", + "ZSTNT1W", "ZSUB", "ZSUBHNB", "ZSUBHNT", diff --git a/src/cmd/internal/obj/arm64/asm7.go b/src/cmd/internal/obj/arm64/asm7.go index 972980defe..eb6974e567 100644 --- a/src/cmd/internal/obj/arm64/asm7.go +++ b/src/cmd/internal/obj/arm64/asm7.go @@ -8465,7 +8465,11 @@ func EncodeRegisterExtension(a *obj.Addr, ext string, reg, num int16, isAmount, a.Reg = REG_ZARNGELEM + (reg & 31) + int16((arng&15)<<5) a.Index = num } else { - a.Reg = REG_ZARNG + (reg & 31) + int16((arng&15)<<5) + if a.Type == obj.TYPE_MEM { + a.Index = REG_ZARNG + (reg & 31) + int16((arng&15)<<5) + } else { + a.Reg = REG_ZARNG + (reg & 31) + int16((arng&15)<<5) + } } } else if REG_P0 <= reg && reg <= REG_PN15 { var arng int diff --git a/src/cmd/internal/obj/arm64/encoding_gen.go b/src/cmd/internal/obj/arm64/encoding_gen.go index 2743a2d7cf..dbd4b67cf9 100644 --- a/src/cmd/internal/obj/arm64/encoding_gen.go +++ b/src/cmd/internal/obj/arm64/encoding_gen.go @@ -2,6 +2,34 @@ package arm64 +import "cmd/internal/obj" + +// stripRawZ first checks if v is a raw Z register, if so +// it tries to verify that it's indeed a Z register, if it's not +// it will return ok as false. +// Otherwise, it will strip additional information and return ok as true. +func stripRawZ(v *uint32) bool { + if *v >= obj.RBaseARM64 { + if !(*v >= REG_Z0 && *v <= REG_Z31) && !(*v >= REG_ZARNG && *v < REG_ZARNGELEM) { + return false + } + } + *v = *v & 31 + return true +} + +// checkIsR checks if v is a scalar register. +// In the encoding scheme, R is always assumed to be passed in as raw, i.e. +// starting at RBaseARM64. If it's not a raw R register, it will strip +// additional information and return ok as true. +// Otherwise, it will return ok as false. +func checkIsR(v uint32) bool { + if v > REG_R31 && v != REG_RSP { + return false + } + return true +} + const ( enc_NIL component = iota enc_i1_tsz @@ -37,6 +65,7 @@ const ( enc_Zk enc_Zm enc_Zn + enc_Zt enc_i1 enc_i2 enc_imm13 @@ -48,13 +77,27 @@ const ( enc_imm6 enc_imm7 enc_imm8 + enc_msz enc_rot enc_size enc_size0 enc_sz enc_tsz + enc_xs ) +// encodeNoModCheck is the implementation of the following encoding logic: +// Check that there is no modifier (UXTW, SXTW, LSL) +func encodeNoModCheck(v uint32) (uint32, bool) { + return 0, v == 0 +} + +// encodeNoAmtCheck is the implementation of the following encoding logic: +// Check that there is no modifier amount +func encodeNoAmtCheck(v uint32) (uint32, bool) { + return 0, v == 0 +} + // encodeXCheck is the implementation of the following encoding logic: // Check this is a 64-bit scalar register func encodeXCheck(v uint32) (uint32, bool) { @@ -133,6 +176,69 @@ func encodeFimm0_0_56(v uint32) (uint32, bool) { return 0, true } +// encodeModAmt1Check is the implementation of the following encoding logic: +// Check this is mod amount and is 1 +func encodeModAmt1Check(v uint32) (uint32, bool) { + if v == 1 { + return 0, true + } + return 0, false +} + +// encodeModAmt2Check is the implementation of the following encoding logic: +// Check this is mod amount and is 2 +func encodeModAmt2Check(v uint32) (uint32, bool) { + if v == 2 { + return 0, true + } + return 0, false +} + +// encodeModAmt3Check is the implementation of the following encoding logic: +// Check this is mod amount and is 3 +func encodeModAmt3Check(v uint32) (uint32, bool) { + if v == 3 { + return 0, true + } + return 0, false +} + +// encodeModAmt4Check is the implementation of the following encoding logic: +// Check this is mod amount and is 4 +func encodeModAmt4Check(v uint32) (uint32, bool) { + if v == 4 { + return 0, true + } + return 0, false +} + +// encodeModLSLCheck is the implementation of the following encoding logic: +// Check this is mod and is LSL +func encodeModLSLCheck(v uint32) (uint32, bool) { + if v&0b100 != 0 { + return 0, true + } + return 0, false +} + +// encodeModSXTWCheck is the implementation of the following encoding logic: +// Check this is mod and is SXTW +func encodeModSXTWCheck(v uint32) (uint32, bool) { + if v&0b10 != 0 { + return 0, true + } + return 0, false +} + +// encodeModUXTWCheck is the implementation of the following encoding logic: +// Check this is mod and is UXTW +func encodeModUXTWCheck(v uint32) (uint32, bool) { + if v&0b1 != 0 { + return 0, true + } + return 0, false +} + // encodeI2_1921_16To32Bit is the implementation of the following encoding logic: // For the "16-bit to 32-bit" variant: is the immediate index of a pair of 16-bit elements within each 128-bit vector segment, in the range 0 to 3, encoded in the "i2" field. // bit range mappings: @@ -160,6 +266,9 @@ func encodeI1_2021_16To64Bit(v uint32) (uint32, bool) { // bit range mappings: // Zm: [16:20) func encodeZm1620_16To64Bit(v uint32) (uint32, bool) { + if !stripRawZ(&v) { + return 0, false + } if v > 15 { return 0, false } @@ -171,6 +280,9 @@ func encodeZm1620_16To64Bit(v uint32) (uint32, bool) { // bit range mappings: // Zm: [16:19) func encodeZm1619_16Bit32Bit(v uint32) (uint32, bool) { + if !stripRawZ(&v) { + return 0, false + } if v > 7 { return 0, false } @@ -205,6 +317,9 @@ func encodeI3hI3l_1923_16Bit(v uint32) (uint32, bool) { // bit range mappings: // Zm: [16:19) func encodeZm_1619_Range0_7V1(v uint32) (uint32, bool) { + if !stripRawZ(&v) { + return 0, false + } if v <= 7 { return v << 16, true } @@ -250,6 +365,9 @@ func encodeI3hI3l_1119_32Bit(v uint32) (uint32, bool) { // bit range mappings: // Zm: [16:20) func encodeZm_1620_Range0_15(v uint32) (uint32, bool) { + if !stripRawZ(&v) { + return 0, false + } if v <= 15 { return v << 16, true } @@ -261,6 +379,9 @@ func encodeZm_1620_Range0_15(v uint32) (uint32, bool) { // bit range mappings: // Zm: [16:19) func encodeZm1619_32Bit(v uint32) (uint32, bool) { + if !stripRawZ(&v) { + return 0, false + } if v > 7 { return 0, false } @@ -295,6 +416,9 @@ func encodeI2hI2l_1120_64Bit(v uint32) (uint32, bool) { // bit range mappings: // Zm: [16:20) func encodeZm1620_64Bit(v uint32) (uint32, bool) { + if !stripRawZ(&v) { + return 0, false + } if v > 15 { return 0, false } @@ -329,6 +453,9 @@ func encodeI2_1921_8To32Bit(v uint32) (uint32, bool) { // bit range mappings: // Zm: [16:19) func encodeZm1619_8To32Bit(v uint32) (uint32, bool) { + if !stripRawZ(&v) { + return 0, false + } if v > 7 { return 0, false } @@ -411,6 +538,9 @@ func encodeI1_2021_DoublePrecision(v uint32) (uint32, bool) { // bit range mappings: // Zm: [16:20) func encodeZm1620_DoublePrecision(v uint32) (uint32, bool) { + if !stripRawZ(&v) { + return 0, false + } if v > 15 { return 0, false } @@ -445,6 +575,9 @@ func encodeImm5Signed_1621V2(v uint32) (uint32, bool) { // bit range mappings: // Zm: [16:19) func encodeZm1619_HalfSinglePrecision(v uint32) (uint32, bool) { + if !stripRawZ(&v) { + return 0, false + } if v > 7 { return 0, false } @@ -479,6 +612,9 @@ func encodeI2_1921_Half(v uint32) (uint32, bool) { // bit range mappings: // Zm: [16:19) func encodeZm_1619_Half(v uint32) (uint32, bool) { + if !stripRawZ(&v) { + return 0, false + } if v <= 7 { return v << 16, true } @@ -574,6 +710,9 @@ func encodeI1_2021_Single(v uint32) (uint32, bool) { // bit range mappings: // Zm: [16:20) func encodeZm_1620_Single(v uint32) (uint32, bool) { + if !stripRawZ(&v) { + return 0, false + } if v <= 15 { return v << 16, true } @@ -727,6 +866,9 @@ func encodeImm8UnsignedLsl8(v uint32) (uint32, bool) { // bit range mappings: // Rdn: [0:5) func encodeWdn05(v uint32) (uint32, bool) { + if !checkIsR(v) { + return 0, false + } if v == REG_RSP { return 0, false } @@ -746,6 +888,9 @@ func encodeVd0564(v uint32) (uint32, bool) { // bit range mappings: // Rd: [0:5) func encodeRd05_SPAllowed(v uint32) (uint32, bool) { + if !checkIsR(v) { + return 0, false + } if v == REG_R31 { return 0, false } @@ -760,6 +905,9 @@ func encodeRd05_SPAllowed(v uint32) (uint32, bool) { // bit range mappings: // Rd: [0:5) func encodeRd05(v uint32) (uint32, bool) { + if !checkIsR(v) { + return 0, false + } if v == REG_RSP { return 0, false } @@ -771,17 +919,54 @@ func encodeRd05(v uint32) (uint32, bool) { // bit range mappings: // Rn: [5:10) func encodeRn510(v uint32) (uint32, bool) { + if !checkIsR(v) { + return 0, false + } if v == REG_RSP { return 0, false } return (v & 31) << 5, true } -// encodeRm1621 is the implementation of the following encoding logic: +// encodeRn510SPV2 is the implementation of the following encoding logic: +// Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. +// bit range mappings: +// Rn: [5:10) +func encodeRn510SPV2(v uint32) (uint32, bool) { + if !checkIsR(v) { + return 0, false + } + if v == REG_R31 { + return 0, false + } + if v == REG_RSP { + return 31 << 5, true + } + return (v & 31) << 5, true +} + +// encodeRm1621V2 is the implementation of the following encoding logic: +// Is the 64-bit name of the general-purpose offset register, encoded in the "Rm" field. +// bit range mappings: +// Rm: [16:21) +func encodeRm1621V2(v uint32) (uint32, bool) { + if !checkIsR(v) { + return 0, false + } + if v == REG_RSP { + return 0, false + } + return (v & 31) << 16, true +} + +// encodeRm1621V1 is the implementation of the following encoding logic: // Is the 64-bit name of the second source general-purpose register, encoded in the "Rm" field. // bit range mappings: // Rm: [16:21) -func encodeRm1621(v uint32) (uint32, bool) { +func encodeRm1621V1(v uint32) (uint32, bool) { + if !checkIsR(v) { + return 0, false + } if v == REG_RSP { return 0, false } @@ -793,6 +978,9 @@ func encodeRm1621(v uint32) (uint32, bool) { // bit range mappings: // Rdn: [0:5) func encodeXdn05(v uint32) (uint32, bool) { + if !checkIsR(v) { + return 0, false + } if v == REG_RSP { return 0, false } @@ -804,6 +992,9 @@ func encodeXdn05(v uint32) (uint32, bool) { // bit range mappings: // Rn: [16:21) func encodeRn1621_SPAllowed(v uint32) (uint32, bool) { + if !checkIsR(v) { + return 0, false + } if v == REG_R31 { return 0, false } @@ -1107,6 +1298,83 @@ func encodeShiftTsz58Range1(v uint32) (uint32, bool) { return codeShift588102224, false } +// encodeMsz1012 is the implementation of the following encoding logic: +// Is the index extend and shift specifier, +// msz +// 00 [absent] +// x1 LSL +// 10 LSL +// bit range mappings: +// msz: [10:12) +func encodeMsz1012(v uint32) (uint32, bool) { + // This does not accept UXTW and SXTW, check that + if v&0b11 != 0 { + return 0, false + } + // Note: this encoding function's semantic is entailed by its peer that + // encode , so just do nothing. + return codeNoOp, false +} + +// encodeXs1415 is the implementation of the following encoding logic: +// Is the index extend and shift specifier, +// xs +// 0 UXTW +// 1 SXTW +// bit range mappings: +// xs: [14:15) +func encodeXs1415(v uint32) (uint32, bool) { + if v&0b1 != 0 { + return 0, true + } else if v&0b10 != 0 { + return 1 << 14, true + } + return 0, false +} + +// encodeXs2223 is the implementation of the following encoding logic: +// Is the index extend and shift specifier, +// xs +// 0 UXTW +// 1 SXTW +// bit range mappings: +// xs: [22:23) +func encodeXs2223(v uint32) (uint32, bool) { + if v&0b1 != 0 { + return 0, true + } else if v&0b10 != 0 { + return 1 << 22, true + } + return 0, false +} + +// encodeMsz1012Amount is the implementation of the following encoding logic: +// Is the index shift amount, +// msz +// 00 [absent] +// 01 #1 +// 10 #2 +// 11 #3 +// bit range mappings: +// msz: [10:12) +func encodeMsz1012Amount(v uint32) (uint32, bool) { + if v <= 3 { + return v << 10, true + } + return 0, false +} + +// encodeZn510V2 is the implementation of the following encoding logic: +// Is the name of the base scalable vector register, encoded in the "Zn" field. +// bit range mappings: +// Zn: [5:10) +func encodeZn510V2(v uint32) (uint32, bool) { + if !stripRawZ(&v) { + return 0, false + } + return v << 5, true +} + // encodeVd is the implementation of the following encoding logic: // Is the name of the destination SIMD&FP register, encoded in the "Vd" field. // bit range mappings: @@ -1140,6 +1408,9 @@ func encodePd(v uint32) (uint32, bool) { // bit range mappings: // Zd: [0:5) func encodeZd(v uint32) (uint32, bool) { + if !stripRawZ(&v) { + return 0, false + } return v, true } @@ -1170,9 +1441,23 @@ func encodePd04(v uint32) (uint32, bool) { // bit range mappings: // Zn: [5:10) func encodeZn510MultiSrc1(v uint32) (uint32, bool) { + if !stripRawZ(&v) { + return 0, false + } return v << 5, true } +// encodeZt051 is the implementation of the following encoding logic: +// Is the name of the first scalable vector register to be transferred, encoded in the "Zt" field. +// bit range mappings: +// Zt: [0:5) +func encodeZt051(v uint32) (uint32, bool) { + if !stripRawZ(&v) { + return 0, false + } + return v, true +} + // encodePdnDest is the implementation of the following encoding logic: // Is the name of the first source and destination scalable predicate register, encoded in the "Pdn" field. // bit range mappings: @@ -1186,6 +1471,9 @@ func encodePdnDest(v uint32) (uint32, bool) { // bit range mappings: // Zdn: [0:5) func encodeZdnDest(v uint32) (uint32, bool) { + if !stripRawZ(&v) { + return 0, false + } return v, true } @@ -1209,11 +1497,14 @@ func encodePn59(v uint32) (uint32, bool) { return v << 5, true } -// encodeZn510 is the implementation of the following encoding logic: +// encodeZn510V1 is the implementation of the following encoding logic: // Is the name of the first source scalable vector register, encoded in the "Zn" field. // bit range mappings: // Zn: [5:10) -func encodeZn510(v uint32) (uint32, bool) { +func encodeZn510V1(v uint32) (uint32, bool) { + if !stripRawZ(&v) { + return 0, false + } return v << 5, true } @@ -1225,6 +1516,17 @@ func encodeZn510Table1(v uint32) (uint32, bool) { return v << 5, true } +// encodeZt054 is the implementation of the following encoding logic: +// Is the name of the fourth scalable vector register to be transferred, encoded as "Zt" plus 3 modulo 32. +// bit range mappings: +// Zt: [0:5) +func encodeZt054(v uint32) (uint32, bool) { + if !stripRawZ(&v) { + return 0, false + } + return (v - 3) % 32, true +} + // encodePg1013 is the implementation of the following encoding logic: // Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field. // bit range mappings: @@ -1260,6 +1562,28 @@ func encodePg59(v uint32) (uint32, bool) { return v << 5, true } +// encodeZm1621V3 is the implementation of the following encoding logic: +// Is the name of the offset scalable vector register, encoded in the "Zm" field. +// bit range mappings: +// Zm: [16:21) +func encodeZm1621V3(v uint32) (uint32, bool) { + if !stripRawZ(&v) { + return 0, false + } + return v << 16, true +} + +// encodeZt05 is the implementation of the following encoding logic: +// Is the name of the scalable vector register to be transferred, encoded in the "Zt" field. +// bit range mappings: +// Zt: [0:5) +func encodeZt05(v uint32) (uint32, bool) { + if !stripRawZ(&v) { + return 0, false + } + return v, true +} + // encodePd14Plus1 is the implementation of the following encoding logic: // Is the name of the second destination scalable predicate register, encoded as "Pd" times 2 plus 1. // bit range mappings: @@ -1285,9 +1609,23 @@ func encodePd04Plus1(v uint32) (uint32, bool) { // bit range mappings: // Zn: [5:10) func encodeZn510MultiSrc2(v uint32) (uint32, bool) { + if !stripRawZ(&v) { + return 0, false + } return (v - 1) << 5, true } +// encodeZt052 is the implementation of the following encoding logic: +// Is the name of the second scalable vector register to be transferred, encoded as "Zt" plus 1 modulo 32. +// bit range mappings: +// Zt: [0:5) +func encodeZt052(v uint32) (uint32, bool) { + if !stripRawZ(&v) { + return 0, false + } + return (v - 1) % 32, true +} + // encodePdmDest is the implementation of the following encoding logic: // Is the name of the second source and destination scalable predicate register, encoded in the "Pdm" field. // bit range mappings: @@ -1301,6 +1639,9 @@ func encodePdmDest(v uint32) (uint32, bool) { // bit range mappings: // Zda: [0:5) func encodeZdaDest(v uint32) (uint32, bool) { + if !stripRawZ(&v) { + return 0, false + } return v, true } @@ -1328,6 +1669,9 @@ func encodeZm_1619_Range0_7V2(v uint32) (uint32, bool) { // bit range mappings: // Zm: [16:21) func encodeZm1621V2(v uint32) (uint32, bool) { + if !stripRawZ(&v) { + return 0, false + } return v << 16, true } @@ -1336,6 +1680,9 @@ func encodeZm1621V2(v uint32) (uint32, bool) { // bit range mappings: // Zm: [5:10) func encodeZm510V1(v uint32) (uint32, bool) { + if !stripRawZ(&v) { + return 0, false + } return (v & 31) << 5, true } @@ -1360,6 +1707,9 @@ func encodePdnSrcDst(v uint32) (uint32, bool) { // bit range mappings: // Zdn: [0:5) func encodeZdnSrcDst(v uint32) (uint32, bool) { + if !stripRawZ(&v) { + return 0, false + } return v, true } @@ -1384,6 +1734,9 @@ func encodePn59v2(v uint32) (uint32, bool) { // bit range mappings: // Zm: [16:21) func encodeZm1621V1(v uint32) (uint32, bool) { + if !stripRawZ(&v) { + return 0, false + } return v << 16, true } @@ -1392,6 +1745,9 @@ func encodeZm1621V1(v uint32) (uint32, bool) { // bit range mappings: // Zm: [5:10) func encodeZm510V2(v uint32) (uint32, bool) { + if !stripRawZ(&v) { + return 0, false + } return (v & 31) << 5, true } @@ -1400,6 +1756,9 @@ func encodeZm510V2(v uint32) (uint32, bool) { // bit range mappings: // Zn: [5:10) func encodeZn510Src(v uint32) (uint32, bool) { + if !stripRawZ(&v) { + return 0, false + } return (v & 31) << 5, true } @@ -1411,11 +1770,25 @@ func encodeZn510Table3(v uint32) (uint32, bool) { return v << 5, true } +// encodeZt053 is the implementation of the following encoding logic: +// Is the name of the third scalable vector register to be transferred, encoded as "Zt" plus 2 modulo 32. +// bit range mappings: +// Zt: [0:5) +func encodeZt053(v uint32) (uint32, bool) { + if !stripRawZ(&v) { + return 0, false + } + return (v - 2) % 32, true +} + // encodeZda3RdSrcDst is the implementation of the following encoding logic: // Is the name of the third source and destination scalable vector register, encoded in the "Zda" field. // bit range mappings: // Zda: [0:5) func encodeZda3RdSrcDst(v uint32) (uint32, bool) { + if !stripRawZ(&v) { + return 0, false + } return v, true } @@ -1424,6 +1797,9 @@ func encodeZda3RdSrcDst(v uint32) (uint32, bool) { // bit range mappings: // Za: [16:21) func encodeZa16213Rd(v uint32) (uint32, bool) { + if !stripRawZ(&v) { + return 0, false + } return v << 16, true } @@ -1432,6 +1808,9 @@ func encodeZa16213Rd(v uint32) (uint32, bool) { // bit range mappings: // Za: [5:10) func encodeZa5103Rd(v uint32) (uint32, bool) { + if !stripRawZ(&v) { + return 0, false + } return v << 5, true } @@ -1440,6 +1819,9 @@ func encodeZa5103Rd(v uint32) (uint32, bool) { // bit range mappings: // Zk: [5:10) func encodeZk5103Rd(v uint32) (uint32, bool) { + if !stripRawZ(&v) { + return 0, false + } return v << 5, true } @@ -1472,6 +1854,9 @@ func encodePv59(v uint32) (uint32, bool) { // bit range mappings: // Rd: [0:5) func encodeRd05ZR(v uint32) (uint32, bool) { + if !checkIsR(v) { + return 0, false + } if v == REG_RSP { return 0, false } @@ -1479,11 +1864,14 @@ func encodeRd05ZR(v uint32) (uint32, bool) { return v & 31, true } -// encodeRn510SP is the implementation of the following encoding logic: +// encodeRn510SPV1 is the implementation of the following encoding logic: // Is the number [0-30] of the general-purpose source register or the name SP (31), encoded in the "Rn" field. // bit range mappings: // Rn: [5:10) -func encodeRn510SP(v uint32) (uint32, bool) { +func encodeRn510SPV1(v uint32) (uint32, bool) { + if !checkIsR(v) { + return 0, false + } if v == REG_R31 { return 0, false } @@ -1498,6 +1886,9 @@ func encodeRn510SP(v uint32) (uint32, bool) { // bit range mappings: // Rdn: [0:5) func encodeRdn05ZR(v uint32) (uint32, bool) { + if !checkIsR(v) { + return 0, false + } if v == REG_RSP { return 0, false } @@ -1509,6 +1900,9 @@ func encodeRdn05ZR(v uint32) (uint32, bool) { // bit range mappings: // Rm: [16:21) func encodeRm1621ZR(v uint32) (uint32, bool) { + if !checkIsR(v) { + return 0, false + } if v == REG_RSP { return 0, false } @@ -1520,6 +1914,9 @@ func encodeRm1621ZR(v uint32) (uint32, bool) { // bit range mappings: // Rm: [5:10) func encodeRm510ZR(v uint32) (uint32, bool) { + if !checkIsR(v) { + return 0, false + } if v == REG_RSP { return 0, false } @@ -1531,6 +1928,9 @@ func encodeRm510ZR(v uint32) (uint32, bool) { // bit range mappings: // Rn: [5:10) func encodeRn510ZR(v uint32) (uint32, bool) { + if !checkIsR(v) { + return 0, false + } if v == REG_RSP { return 0, false } @@ -1569,6 +1969,21 @@ func encodeVdn05(v uint32) (uint32, bool) { return v & 31, true } +// encodeRm1621XZR is the implementation of the following encoding logic: +// Is the optional 64-bit name of the general-purpose offset register, defaulting to XZR, encoded in the "Rm" field. +// bit range mappings: +// Rm: [16:21) +func encodeRm1621XZR(v uint32) (uint32, bool) { + if v == 0 { + // absent case, according to the spec this should be ZR (R31) + return 31, true + } + if !checkIsR(v) { + return 0, false + } + return (v & 31) << 16, true +} + // encodeI189 is the implementation of the following encoding logic: // Is the portion index, in the range 0 to 1, encoded in the "i1" field. // bit range mappings: @@ -1696,6 +2111,30 @@ func encodeSizeImm13NoOp(v uint32) (uint32, bool) { return codeNoOp, false } +// encodeSize2123V1 is the implementation of the following encoding logic: +// Is the size specifier, +// size +// 00 B +// 01 H +// 10 S +// 11 D +// bit range mappings: +// size: [21:23) +func encodeSize2123V1(v uint32) (uint32, bool) { + switch v { + case ARNG_B: + return 0, true + case ARNG_H: + return 1 << 21, true + case ARNG_S: + return 2 << 21, true + case ARNG_D: + return 3 << 21, true + default: + return 0, false + } +} + // encodeSizeBHSD2224 is the implementation of the following encoding logic: // Is the size specifier, // size @@ -1803,6 +2242,27 @@ func encodeSizeHSD1719(v uint32) (uint32, bool) { return 0, false } +// encodeSize2123V2 is the implementation of the following encoding logic: +// Is the size specifier, +// size +// 00 RESERVED +// 01 H +// 10 S +// 11 D +// bit range mappings: +// size: [21:23) +func encodeSize2123V2(v uint32) (uint32, bool) { + switch v { + case ARNG_H: + return 1 << 21, true + case ARNG_S: + return 2 << 21, true + case ARNG_D: + return 3 << 21, true + } + return 0, false +} + // encodeSizeHSD2224 is the implementation of the following encoding logic: // Is the size specifier, // size diff --git a/src/cmd/internal/obj/arm64/goops_gen.go b/src/cmd/internal/obj/arm64/goops_gen.go index ceb403eb66..53816d3ead 100644 --- a/src/cmd/internal/obj/arm64/goops_gen.go +++ b/src/cmd/internal/obj/arm64/goops_gen.go @@ -98,6 +98,7 @@ const ( AZADDQP AZADDQV AZADDSUBP + AZADR AZAESD AZAESE AZAESIMC @@ -328,6 +329,51 @@ const ( AZLASTBH AZLASTBS AZLASTBW + AZLD1B + AZLD1D + AZLD1H + AZLD1Q + AZLD1ROB + AZLD1ROD + AZLD1ROH + AZLD1ROW + AZLD1RQB + AZLD1RQD + AZLD1RQH + AZLD1RQW + AZLD1SB + AZLD1SH + AZLD1SW + AZLD1W + AZLD2B + AZLD2D + AZLD2H + AZLD2Q + AZLD2W + AZLD3B + AZLD3D + AZLD3H + AZLD3Q + AZLD3W + AZLD4B + AZLD4D + AZLD4H + AZLD4Q + AZLD4W + AZLDFF1B + AZLDFF1D + AZLDFF1H + AZLDFF1SB + AZLDFF1SH + AZLDFF1SW + AZLDFF1W + AZLDNT1B + AZLDNT1D + AZLDNT1H + AZLDNT1SB + AZLDNT1SH + AZLDNT1SW + AZLDNT1W AZLSL AZLSLR AZLSR @@ -478,6 +524,30 @@ const ( AZSSUBLTB AZSSUBWB AZSSUBWT + AZST1B + AZST1D + AZST1H + AZST1Q + AZST1W + AZST2B + AZST2D + AZST2H + AZST2Q + AZST2W + AZST3B + AZST3D + AZST3H + AZST3Q + AZST3W + AZST4B + AZST4D + AZST4H + AZST4Q + AZST4W + AZSTNT1B + AZSTNT1D + AZSTNT1H + AZSTNT1W AZSUB AZSUBHNB AZSUBHNT diff --git a/src/cmd/internal/obj/arm64/inst.go b/src/cmd/internal/obj/arm64/inst.go index 688e990bcf..0bf4b9950d 100644 --- a/src/cmd/internal/obj/arm64/inst.go +++ b/src/cmd/internal/obj/arm64/inst.go @@ -143,6 +143,9 @@ func aclass(a *obj.Addr) AClass { return AC_REGLIST4 } } + if a.Type == obj.TYPE_MEM { + return AC_MEMEXT + } panic("unknown AClass") } @@ -329,6 +332,39 @@ func addrComponent(a *obj.Addr, acl AClass, index int) uint32 { default: panic(fmt.Errorf("unknown elm index at %d in AClass %d", index, acl)) } + // AClass: AC_MEMEXT + // GNU mnemonic: [., ., ] + // Go mnemonic: + // (reg2.T2.mod<> 5) & 15) + case 2: + return uint32(a.Reg) + case 3: + return uint32((a.Reg >> 5) & 15) + case 4: + // mod is either 1 (UXTW), 2 (SXTW), or 4 (LSL) + mod := uint32((a.Scale >> 9) & 0x7) + amount := uint32((a.Scale >> 12) & 0x7) + if mod == 0 && amount > 0 { + // LSL is implied when no extension is specified but amount > 0 + mod |= 1 << 2 + } + return mod + case 5: + return uint32((a.Scale >> 12) & 0x7) + default: + panic(fmt.Errorf("unknown elm index at %d in AClass %d", index, acl)) + } } // TODO: handle more AClasses. panic(fmt.Errorf("unknown AClass %d", acl)) @@ -696,7 +732,8 @@ func (i *instEncoder) tryEncode(p *obj.Prog) (uint32, bool) { } return 0, false } - if enc.comp != enc_NIL { + if enc.comp != enc_NIL && specialB != codeNoOp { + // NoOp encodings don't need bookkeeping. encoded[enc.comp] = b } } else { @@ -704,6 +741,5 @@ func (i *instEncoder) tryEncode(p *obj.Prog) (uint32, bool) { } } } - return bin, true } diff --git a/src/cmd/internal/obj/arm64/inst_gen.go b/src/cmd/internal/obj/arm64/inst_gen.go index ada9c32fa7..6c68daa26b 100644 --- a/src/cmd/internal/obj/arm64/inst_gen.go +++ b/src/cmd/internal/obj/arm64/inst_gen.go @@ -927,6 +927,27 @@ var insts = [][]instEncoder{ args: Zm_T__Zn_T__Zd_T__1, }, }, + // ZADR + { + // ZADR [.D, .D, SXTW{}], .D + { + goOp: AZADR, + fixedBits: 0x420a000, + args: Zn_D__Zm_D__SXTWamount___Zd_D, + }, + // ZADR [.D, .D, UXTW{}], .D + { + goOp: AZADR, + fixedBits: 0x460a000, + args: Zn_D__Zm_D__UXTWamount___Zd_D, + }, + // ZADR [., .{, }], . + { + goOp: AZADR, + fixedBits: 0x4a0a000, + args: Zn_T__Zm_T__mod_amount___Zd_T, + }, + }, // ZAESD { // ZAESD .B, .B, .B @@ -4011,5375 +4032,7709 @@ var insts = [][]instEncoder{ args: Zn_T__Pg__Rd, }, }, - // ZLSL + // ZLD1B { - // ZLSL .D, ., /M, . + // ZLD1B [, ], /Z, { .B } { - goOp: AZLSL, - fixedBits: 0x41b8000, - args: Zm_D__Zdn_T__PgM__Zdn_T, + goOp: AZLD1B, + fixedBits: 0xa4004000, + args: XnSP__Xm___PgZ___Zt_B_, }, - // ZLSL .D, ., . + // ZLD1B [, ], /Z, { .D } { - goOp: AZLSL, - fixedBits: 0x4208c00, - args: Zm_D__Zn_T__Zd_T, + goOp: AZLD1B, + fixedBits: 0xa4604000, + args: XnSP__Xm___PgZ___Zt_D_, }, - // ZLSL ., ., /M, . + // ZLD1B [, ], /Z, { .H } { - goOp: AZLSL, - fixedBits: 0x4138000, - args: Zm_T__Zdn_T__PgM__Zdn_T__1, + goOp: AZLD1B, + fixedBits: 0xa4204000, + args: XnSP__Xm___PgZ___Zt_H_, }, - // ZLSL #, ., /M, . + // ZLD1B [, ], /Z, { .S } { - goOp: AZLSL, - fixedBits: 0x4038000, - args: cconst__Zdn_T__PgM__Zdn_T__2, + goOp: AZLD1B, + fixedBits: 0xa4404000, + args: XnSP__Xm___PgZ___Zt_S_, }, - // ZLSL #, ., . + // ZLD1B [, .D], /Z, { .D } { - goOp: AZLSL, - fixedBits: 0x4209c00, - args: cconst__Zn_T__Zd_T__2, + goOp: AZLD1B, + fixedBits: 0xc440c000, + args: XnSP__Zm_D___PgZ___Zt_D_, + }, + // ZLD1B [, .D, ], /Z, { .D } + { + goOp: AZLD1B, + fixedBits: 0xc4004000, + args: XnSP__Zm_D__mod___PgZ___Zt_D_, + }, + // ZLD1B [, .S, ], /Z, { .S } + { + goOp: AZLD1B, + fixedBits: 0x84004000, + args: XnSP__Zm_S__mod___PgZ___Zt_S_, }, }, - // ZLSLR + // ZLD1D { - // ZLSLR ., ., /M, . + // ZLD1D [, .D, LSL #3], /Z, { .D } { - goOp: AZLSLR, - fixedBits: 0x4178000, - args: Zm_T__Zdn_T__PgM__Zdn_T__1, + goOp: AZLD1D, + fixedBits: 0xc5e0c000, + args: XnSP__Zm_D__LSL_c3___PgZ___Zt_D_, + }, + // ZLD1D [, .D], /Z, { .D } + { + goOp: AZLD1D, + fixedBits: 0xc5c0c000, + args: XnSP__Zm_D___PgZ___Zt_D_, + }, + // ZLD1D [, .D, ], /Z, { .D } + { + goOp: AZLD1D, + fixedBits: 0xc5804000, + args: XnSP__Zm_D__mod___PgZ___Zt_D_, + }, + // ZLD1D [, .D, #3], /Z, { .D } + { + goOp: AZLD1D, + fixedBits: 0xc5a04000, + args: XnSP__Zm_D__mod_c3___PgZ___Zt_D_, }, }, - // ZLSR + // ZLD1H { - // ZLSR .D, ., /M, . + // ZLD1H [, , LSL #1], /Z, { .D } { - goOp: AZLSR, - fixedBits: 0x4198000, - args: Zm_D__Zdn_T__PgM__Zdn_T, + goOp: AZLD1H, + fixedBits: 0xa4e04000, + args: XnSP__Xm__LSL_c1___PgZ___Zt_D_, }, - // ZLSR .D, ., . + // ZLD1H [, , LSL #1], /Z, { .H } { - goOp: AZLSR, - fixedBits: 0x4208400, - args: Zm_D__Zn_T__Zd_T, + goOp: AZLD1H, + fixedBits: 0xa4a04000, + args: XnSP__Xm__LSL_c1___PgZ___Zt_H_, }, - // ZLSR ., ., /M, . + // ZLD1H [, , LSL #1], /Z, { .S } { - goOp: AZLSR, - fixedBits: 0x4118000, - args: Zm_T__Zdn_T__PgM__Zdn_T__1, + goOp: AZLD1H, + fixedBits: 0xa4c04000, + args: XnSP__Xm__LSL_c1___PgZ___Zt_S_, }, - // ZLSR #, ., /M, . + // ZLD1H [, .D, LSL #1], /Z, { .D } { - goOp: AZLSR, - fixedBits: 0x4018000, - args: cconst__Zdn_T__PgM__Zdn_T__1, + goOp: AZLD1H, + fixedBits: 0xc4e0c000, + args: XnSP__Zm_D__LSL_c1___PgZ___Zt_D_, }, - // ZLSR #, ., . + // ZLD1H [, .D], /Z, { .D } { - goOp: AZLSR, - fixedBits: 0x4209400, - args: cconst__Zn_T__Zd_T__1, + goOp: AZLD1H, + fixedBits: 0xc4c0c000, + args: XnSP__Zm_D___PgZ___Zt_D_, }, - }, - // ZLSRR - { - // ZLSRR ., ., /M, . + // ZLD1H [, .D, ], /Z, { .D } { - goOp: AZLSRR, - fixedBits: 0x4158000, - args: Zm_T__Zdn_T__PgM__Zdn_T__1, + goOp: AZLD1H, + fixedBits: 0xc4804000, + args: XnSP__Zm_D__mod___PgZ___Zt_D_, }, - }, - // ZLUTI2 - { - // ZLUTI2 [], { .B }, .B + // ZLD1H [, .D, #1], /Z, { .D } { - goOp: AZLUTI2, - fixedBits: 0x4520b000, - args: Zm_index____Zn_B___Zd_B__1, + goOp: AZLD1H, + fixedBits: 0xc4a04000, + args: XnSP__Zm_D__mod_c1___PgZ___Zt_D_, }, - // ZLUTI2 [], { .H }, .H + // ZLD1H [, .S, ], /Z, { .S } { - goOp: AZLUTI2, - fixedBits: 0x4520a800, - args: Zm_index____Zn_H___Zd_H__1, + goOp: AZLD1H, + fixedBits: 0x84804000, + args: XnSP__Zm_S__mod___PgZ___Zt_S_, + }, + // ZLD1H [, .S, #1], /Z, { .S } + { + goOp: AZLD1H, + fixedBits: 0x84a04000, + args: XnSP__Zm_S__mod_c1___PgZ___Zt_S_, }, }, - // ZLUTI4 + // ZLD1Q { - // ZLUTI4 [], { .H, .H }, .H + // ZLD1Q [.D{, }], /Z, { .Q } { - goOp: AZLUTI4, - fixedBits: 0x4520b400, - args: Zm_index____Zn1_H__Zn2_H___Zd_H__1, + goOp: AZLD1Q, + fixedBits: 0xc400a000, + args: Zn_D__Xm___PgZ___Zt_Q_, }, - // ZLUTI4 [], { .B }, .B + }, + // ZLD1ROB + { + // ZLD1ROB [, ], /Z, { .B } { - goOp: AZLUTI4, - fixedBits: 0x4560a400, - args: Zm_index____Zn_B___Zd_B__2, + goOp: AZLD1ROB, + fixedBits: 0xa4200000, + args: XnSP__Xm___PgZ___Zt_B_, }, - // ZLUTI4 [], { .H }, .H + }, + // ZLD1ROD + { + // ZLD1ROD [, , LSL #3], /Z, { .D } { - goOp: AZLUTI4, - fixedBits: 0x4520bc00, - args: Zm_index____Zn_H___Zd_H__2, + goOp: AZLD1ROD, + fixedBits: 0xa5a00000, + args: XnSP__Xm__LSL_c3___PgZ___Zt_D_, }, }, - // ZLUTI6 + // ZLD1ROH { - // ZLUTI6 , { .B, .B }, .B + // ZLD1ROH [, , LSL #1], /Z, { .H } { - goOp: AZLUTI6, - fixedBits: 0x4520ac00, - args: Zm___Zn1_B__Zn2_B___Zd_B, + goOp: AZLD1ROH, + fixedBits: 0xa4a00000, + args: XnSP__Xm__LSL_c1___PgZ___Zt_H_, }, - // ZLUTI6 [], { .H, .H }, .H + }, + // ZLD1ROW + { + // ZLD1ROW [, , LSL #2], /Z, { .S } { - goOp: AZLUTI6, - fixedBits: 0x4560ac00, - args: Zm_index____Zn1_H__Zn2_H___Zd_H__2, + goOp: AZLD1ROW, + fixedBits: 0xa5200000, + args: XnSP__Xm__LSL_c2___PgZ___Zt_S_, }, }, - // ZMAD + // ZLD1RQB { - // ZMAD ., ., /M, . + // ZLD1RQB [, ], /Z, { .B } { - goOp: AZMAD, - fixedBits: 0x400c000, - args: Za_T__Zm_T__PgM__Zdn_T__2, + goOp: AZLD1RQB, + fixedBits: 0xa4000000, + args: XnSP__Xm___PgZ___Zt_B_, }, }, - // ZMADPT + // ZLD1RQD { - // ZMADPT .D, .D, .D + // ZLD1RQD [, , LSL #3], /Z, { .D } { - goOp: AZMADPT, - fixedBits: 0x44c0d800, - args: Za_D__Zm_D__Zdn_D, + goOp: AZLD1RQD, + fixedBits: 0xa5800000, + args: XnSP__Xm__LSL_c3___PgZ___Zt_D_, }, }, - // ZMATCH + // ZLD1RQH { - // ZMATCH ., ., /Z, . + // ZLD1RQH [, , LSL #1], /Z, { .H } { - goOp: AZMATCH, - fixedBits: 0x45208000, - args: Zm_T__Zn_T__PgZ__Pd_T__3, + goOp: AZLD1RQH, + fixedBits: 0xa4800000, + args: XnSP__Xm__LSL_c1___PgZ___Zt_H_, }, }, - // ZMLA + // ZLD1RQW { - // ZMLA ., ., /M, . + // ZLD1RQW [, , LSL #2], /Z, { .S } { - goOp: AZMLA, - fixedBits: 0x4004000, - args: Zm_T__Zn_T__PgM__Zda_T__2, + goOp: AZLD1RQW, + fixedBits: 0xa5000000, + args: XnSP__Xm__LSL_c2___PgZ___Zt_S_, }, - // ZMLA .D[], .D, .D + }, + // ZLD1SB + { + // ZLD1SB [, ], /Z, { .D } { - goOp: AZMLA, - fixedBits: 0x44e00800, - args: Zm_D_imm___Zn_D__Zda_D__1, + goOp: AZLD1SB, + fixedBits: 0xa5804000, + args: XnSP__Xm___PgZ___Zt_D_, }, - // ZMLA .H[], .H, .H + // ZLD1SB [, ], /Z, { .H } { - goOp: AZMLA, - fixedBits: 0x44200800, - args: Zm_H_imm___Zn_H__Zda_H__1, + goOp: AZLD1SB, + fixedBits: 0xa5c04000, + args: XnSP__Xm___PgZ___Zt_H_, }, - // ZMLA .S[], .S, .S + // ZLD1SB [, ], /Z, { .S } { - goOp: AZMLA, - fixedBits: 0x44a00800, - args: Zm_S_imm___Zn_S__Zda_S__1, + goOp: AZLD1SB, + fixedBits: 0xa5a04000, + args: XnSP__Xm___PgZ___Zt_S_, }, - }, - // ZMLAPT - { - // ZMLAPT .D, .D, .D + // ZLD1SB [, .D], /Z, { .D } { - goOp: AZMLAPT, - fixedBits: 0x44c0d000, - args: Zm_D__Zn_D__Zda_D, + goOp: AZLD1SB, + fixedBits: 0xc4408000, + args: XnSP__Zm_D___PgZ___Zt_D_, + }, + // ZLD1SB [, .D, ], /Z, { .D } + { + goOp: AZLD1SB, + fixedBits: 0xc4000000, + args: XnSP__Zm_D__mod___PgZ___Zt_D_, + }, + // ZLD1SB [, .S, ], /Z, { .S } + { + goOp: AZLD1SB, + fixedBits: 0x84000000, + args: XnSP__Zm_S__mod___PgZ___Zt_S_, }, }, - // ZMLS + // ZLD1SH { - // ZMLS ., ., /M, . + // ZLD1SH [, , LSL #1], /Z, { .D } { - goOp: AZMLS, - fixedBits: 0x4006000, - args: Zm_T__Zn_T__PgM__Zda_T__2, + goOp: AZLD1SH, + fixedBits: 0xa5004000, + args: XnSP__Xm__LSL_c1___PgZ___Zt_D_, }, - // ZMLS .D[], .D, .D + // ZLD1SH [, , LSL #1], /Z, { .S } { - goOp: AZMLS, - fixedBits: 0x44e00c00, - args: Zm_D_imm___Zn_D__Zda_D__1, + goOp: AZLD1SH, + fixedBits: 0xa5204000, + args: XnSP__Xm__LSL_c1___PgZ___Zt_S_, }, - // ZMLS .H[], .H, .H + // ZLD1SH [, .D, LSL #1], /Z, { .D } { - goOp: AZMLS, - fixedBits: 0x44200c00, - args: Zm_H_imm___Zn_H__Zda_H__1, + goOp: AZLD1SH, + fixedBits: 0xc4e08000, + args: XnSP__Zm_D__LSL_c1___PgZ___Zt_D_, }, - // ZMLS .S[], .S, .S + // ZLD1SH [, .D], /Z, { .D } { - goOp: AZMLS, - fixedBits: 0x44a00c00, - args: Zm_S_imm___Zn_S__Zda_S__1, + goOp: AZLD1SH, + fixedBits: 0xc4c08000, + args: XnSP__Zm_D___PgZ___Zt_D_, }, - }, - // ZMOVPRFX - { - // ZMOVPRFX ., /, . + // ZLD1SH [, .D, ], /Z, { .D } { - goOp: AZMOVPRFX, - fixedBits: 0x4102000, - args: Zn_T__PgZM__Zd_T, + goOp: AZLD1SH, + fixedBits: 0xc4800000, + args: XnSP__Zm_D__mod___PgZ___Zt_D_, }, - // ZMOVPRFX , + // ZLD1SH [, .D, #1], /Z, { .D } { - goOp: AZMOVPRFX, - fixedBits: 0x420bc00, - args: Zn__Zd, + goOp: AZLD1SH, + fixedBits: 0xc4a00000, + args: XnSP__Zm_D__mod_c1___PgZ___Zt_D_, + }, + // ZLD1SH [, .S, ], /Z, { .S } + { + goOp: AZLD1SH, + fixedBits: 0x84800000, + args: XnSP__Zm_S__mod___PgZ___Zt_S_, + }, + // ZLD1SH [, .S, #1], /Z, { .S } + { + goOp: AZLD1SH, + fixedBits: 0x84a00000, + args: XnSP__Zm_S__mod_c1___PgZ___Zt_S_, }, }, - // ZMSB + // ZLD1SW { - // ZMSB ., ., /M, . + // ZLD1SW [, , LSL #2], /Z, { .D } { - goOp: AZMSB, - fixedBits: 0x400e000, - args: Za_T__Zm_T__PgM__Zdn_T__2, + goOp: AZLD1SW, + fixedBits: 0xa4804000, + args: XnSP__Xm__LSL_c2___PgZ___Zt_D_, + }, + // ZLD1SW [, .D, LSL #2], /Z, { .D } + { + goOp: AZLD1SW, + fixedBits: 0xc5608000, + args: XnSP__Zm_D__LSL_c2___PgZ___Zt_D_, + }, + // ZLD1SW [, .D], /Z, { .D } + { + goOp: AZLD1SW, + fixedBits: 0xc5408000, + args: XnSP__Zm_D___PgZ___Zt_D_, + }, + // ZLD1SW [, .D, ], /Z, { .D } + { + goOp: AZLD1SW, + fixedBits: 0xc5000000, + args: XnSP__Zm_D__mod___PgZ___Zt_D_, + }, + // ZLD1SW [, .D, #2], /Z, { .D } + { + goOp: AZLD1SW, + fixedBits: 0xc5200000, + args: XnSP__Zm_D__mod_c2___PgZ___Zt_D_, }, }, - // ZMUL + // ZLD1W { - // ZMUL ., ., /M, . + // ZLD1W [, .D, LSL #2], /Z, { .D } { - goOp: AZMUL, - fixedBits: 0x4100000, - args: Zm_T__Zdn_T__PgM__Zdn_T__1, + goOp: AZLD1W, + fixedBits: 0xc560c000, + args: XnSP__Zm_D__LSL_c2___PgZ___Zt_D_, }, - // ZMUL ., ., . + // ZLD1W [, .D], /Z, { .D } { - goOp: AZMUL, - fixedBits: 0x4206000, - args: Zm_T__Zn_T__Zd_T__1, + goOp: AZLD1W, + fixedBits: 0xc540c000, + args: XnSP__Zm_D___PgZ___Zt_D_, }, - // ZMUL .D[], .D, .D + // ZLD1W [, .D, ], /Z, { .D } { - goOp: AZMUL, - fixedBits: 0x44e0f800, - args: Zm_D_imm___Zn_D__Zd_D__1, + goOp: AZLD1W, + fixedBits: 0xc5004000, + args: XnSP__Zm_D__mod___PgZ___Zt_D_, }, - // ZMUL .H[], .H, .H + // ZLD1W [, .D, #2], /Z, { .D } { - goOp: AZMUL, - fixedBits: 0x4420f800, - args: Zm_H_imm___Zn_H__Zd_H__1, + goOp: AZLD1W, + fixedBits: 0xc5204000, + args: XnSP__Zm_D__mod_c2___PgZ___Zt_D_, }, - // ZMUL .S[], .S, .S + // ZLD1W [, .S, ], /Z, { .S } { - goOp: AZMUL, - fixedBits: 0x44a0f800, - args: Zm_S_imm___Zn_S__Zd_S__1, + goOp: AZLD1W, + fixedBits: 0x85004000, + args: XnSP__Zm_S__mod___PgZ___Zt_S_, }, - // ZMUL #, ., . + // ZLD1W [, .S, #2], /Z, { .S } { - goOp: AZMUL, - fixedBits: 0x2530c000, - args: cimm__Zdn_T__Zdn_T__1, + goOp: AZLD1W, + fixedBits: 0x85204000, + args: XnSP__Zm_S__mod_c2___PgZ___Zt_S_, }, }, - // ZNBSL + // ZLD2B { - // ZNBSL .D, .D, .D, .D + // ZLD2B [, ], /Z, { .B, .B } { - goOp: AZNBSL, - fixedBits: 0x4e03c00, - args: Zk_D__Zm_D__Zdn_D__Zdn_D, + goOp: AZLD2B, + fixedBits: 0xa420c000, + args: XnSP__Xm___PgZ___Zt1_B__Zt2_B_, }, }, - // ZNEG + // ZLD2D { - // ZNEG ., /M, . + // ZLD2D [, , LSL #3], /Z, { .D, .D } { - goOp: AZNEG, - fixedBits: 0x417a000, - args: Zn_T__PgM__Zd_T__2, + goOp: AZLD2D, + fixedBits: 0xa5a0c000, + args: XnSP__Xm__LSL_c3___PgZ___Zt1_D__Zt2_D_, }, - // ZNEG ., /Z, . + }, + // ZLD2H + { + // ZLD2H [, , LSL #1], /Z, { .H, .H } { - goOp: AZNEG, - fixedBits: 0x407a000, - args: Zn_T__PgZ__Zd_T__2, + goOp: AZLD2H, + fixedBits: 0xa4a0c000, + args: XnSP__Xm__LSL_c1___PgZ___Zt1_H__Zt2_H_, }, }, - // ZNMATCH + // ZLD2Q { - // ZNMATCH ., ., /Z, . + // ZLD2Q [, , LSL #4], /Z, { .Q, .Q } { - goOp: AZNMATCH, - fixedBits: 0x45208010, - args: Zm_T__Zn_T__PgZ__Pd_T__3, + goOp: AZLD2Q, + fixedBits: 0xa4a08000, + args: XnSP__Xm__LSL_c4___PgZ___Zt1_Q__Zt2_Q_, }, }, - // ZNOT + // ZLD2W { - // ZNOT ., /M, . + // ZLD2W [, , LSL #2], /Z, { .S, .S } { - goOp: AZNOT, - fixedBits: 0x41ea000, - args: Zn_T__PgM__Zd_T__2, + goOp: AZLD2W, + fixedBits: 0xa520c000, + args: XnSP__Xm__LSL_c2___PgZ___Zt1_S__Zt2_S_, }, - // ZNOT ., /Z, . - { - goOp: AZNOT, - fixedBits: 0x40ea000, - args: Zn_T__PgZ__Zd_T__2, + }, + // ZLD3B + { + // ZLD3B [, ], /Z, { .B, .B, .B } + { + goOp: AZLD3B, + fixedBits: 0xa440c000, + args: XnSP__Xm___PgZ___Zt1_B__Zt2_B__Zt3_B_, }, }, - // ZORQV + // ZLD3D { - // ZORQV ., , . + // ZLD3D [, , LSL #3], /Z, { .D, .D, .D } { - goOp: AZORQV, - fixedBits: 0x41c2000, - args: Zn_Tb__Pg__Vd_T__1, + goOp: AZLD3D, + fixedBits: 0xa5c0c000, + args: XnSP__Xm__LSL_c3___PgZ___Zt1_D__Zt2_D__Zt3_D_, }, }, - // ZORR + // ZLD3H { - // ZORR .D, .D, .D + // ZLD3H [, , LSL #1], /Z, { .H, .H, .H } { - goOp: AZORR, - fixedBits: 0x4603000, - args: Zm_D__Zn_D__Zd_D, + goOp: AZLD3H, + fixedBits: 0xa4c0c000, + args: XnSP__Xm__LSL_c1___PgZ___Zt1_H__Zt2_H__Zt3_H_, }, - // ZORR ., ., /M, . + }, + // ZLD3Q + { + // ZLD3Q [, , LSL #4], /Z, { .Q, .Q, .Q } { - goOp: AZORR, - fixedBits: 0x4180000, - args: Zm_T__Zdn_T__PgM__Zdn_T__1, + goOp: AZLD3Q, + fixedBits: 0xa5208000, + args: XnSP__Xm__LSL_c4___PgZ___Zt1_Q__Zt2_Q__Zt3_Q_, }, - // ZORR #, ., . + }, + // ZLD3W + { + // ZLD3W [, , LSL #2], /Z, { .S, .S, .S } { - goOp: AZORR, - fixedBits: 0x5000000, - args: cconst__Zdn_T__Zdn_T, + goOp: AZLD3W, + fixedBits: 0xa540c000, + args: XnSP__Xm__LSL_c2___PgZ___Zt1_S__Zt2_S__Zt3_S_, }, }, - // ZORVB + // ZLD4B { - // ZORVB ., , + // ZLD4B [, ], /Z, { .B, .B, .B, .B } { - goOp: AZORVB, - fixedBits: 0x4182000, - args: Zn_T__Pg__Vd__1, + goOp: AZLD4B, + fixedBits: 0xa460c000, + args: XnSP__Xm___PgZ___Zt1_B__Zt2_B__Zt3_B__Zt4_B_, }, }, - // ZORVD + // ZLD4D { - // ZORVD ., , + // ZLD4D [, , LSL #3], /Z, { .D, .D, .D, .D } { - goOp: AZORVD, - fixedBits: 0x4d82000, - args: Zn_T__Pg__Vd__1, + goOp: AZLD4D, + fixedBits: 0xa5e0c000, + args: XnSP__Xm__LSL_c3___PgZ___Zt1_D__Zt2_D__Zt3_D__Zt4_D_, }, }, - // ZORVH + // ZLD4H { - // ZORVH ., , + // ZLD4H [, , LSL #1], /Z, { .H, .H, .H, .H } { - goOp: AZORVH, - fixedBits: 0x4582000, - args: Zn_T__Pg__Vd__1, + goOp: AZLD4H, + fixedBits: 0xa4e0c000, + args: XnSP__Xm__LSL_c1___PgZ___Zt1_H__Zt2_H__Zt3_H__Zt4_H_, }, }, - // ZORVS + // ZLD4Q { - // ZORVS ., , + // ZLD4Q [, , LSL #4], /Z, { .Q, .Q, .Q, .Q } { - goOp: AZORVS, - fixedBits: 0x4982000, - args: Zn_T__Pg__Vd__1, + goOp: AZLD4Q, + fixedBits: 0xa5a08000, + args: XnSP__Xm__LSL_c4___PgZ___Zt1_Q__Zt2_Q__Zt3_Q__Zt4_Q_, }, }, - // ZPMOV + // ZLD4W { - // ZPMOV .B, + // ZLD4W [, , LSL #2], /Z, { .S, .S, .S, .S } { - goOp: AZPMOV, - fixedBits: 0x52b3800, - args: Pn_B__Zd, + goOp: AZLD4W, + fixedBits: 0xa560c000, + args: XnSP__Xm__LSL_c2___PgZ___Zt1_S__Zt2_S__Zt3_S__Zt4_S_, }, - // ZPMOV , .B + }, + // ZLDFF1B + { + // ZLDFF1B [{, }], /Z, { .B } { - goOp: AZPMOV, - fixedBits: 0x52a3800, - args: Zn__Pd_B, + goOp: AZLDFF1B, + fixedBits: 0xa4006000, + args: XnSP__Xm___PgZ___Zt_B__V2, }, - // ZPMOV .D, {[]} + // ZLDFF1B [{, }], /Z, { .D } { - goOp: AZPMOV, - fixedBits: 0x5a93800, - args: Pn_D__Zd_imm_, + goOp: AZLDFF1B, + fixedBits: 0xa4606000, + args: XnSP__Xm___PgZ___Zt_D__V2, }, - // ZPMOV .H, {[]} + // ZLDFF1B [{, }], /Z, { .H } { - goOp: AZPMOV, - fixedBits: 0x52d3800, - args: Pn_H__Zd_imm_, + goOp: AZLDFF1B, + fixedBits: 0xa4206000, + args: XnSP__Xm___PgZ___Zt_H__V2, }, - // ZPMOV .S, {[]} + // ZLDFF1B [{, }], /Z, { .S } { - goOp: AZPMOV, - fixedBits: 0x5693800, - args: Pn_S__Zd_imm_, + goOp: AZLDFF1B, + fixedBits: 0xa4406000, + args: XnSP__Xm___PgZ___Zt_S__V2, }, - // ZPMOV {[]}, .D + // ZLDFF1B [, .D], /Z, { .D } { - goOp: AZPMOV, - fixedBits: 0x5a83800, - args: Zn_imm___Pd_D, + goOp: AZLDFF1B, + fixedBits: 0xc440e000, + args: XnSP__Zm_D___PgZ___Zt_D_, }, - // ZPMOV {[]}, .H + // ZLDFF1B [, .D, ], /Z, { .D } { - goOp: AZPMOV, - fixedBits: 0x52c3800, - args: Zn_imm___Pd_H, + goOp: AZLDFF1B, + fixedBits: 0xc4006000, + args: XnSP__Zm_D__mod___PgZ___Zt_D_, }, - // ZPMOV {[]}, .S + // ZLDFF1B [, .S, ], /Z, { .S } { - goOp: AZPMOV, - fixedBits: 0x5683800, - args: Zn_imm___Pd_S, + goOp: AZLDFF1B, + fixedBits: 0x84006000, + args: XnSP__Zm_S__mod___PgZ___Zt_S_, }, }, - // ZPMUL + // ZLDFF1D { - // ZPMUL .B, .B, .B + // ZLDFF1D [{, , LSL #3}], /Z, { .D } { - goOp: AZPMUL, - fixedBits: 0x4206400, - args: Zm_B__Zn_B__Zd_B, + goOp: AZLDFF1D, + fixedBits: 0xa5e06000, + args: XnSP__Xm__LSL_c3___PgZ___Zt_D__V2, }, - }, - // ZPMULLB - { - // ZPMULLB .D, .D, .Q + // ZLDFF1D [, .D, LSL #3], /Z, { .D } { - goOp: AZPMULLB, - fixedBits: 0x45006800, - args: Zm_D__Zn_D__Zd_Q, + goOp: AZLDFF1D, + fixedBits: 0xc5e0e000, + args: XnSP__Zm_D__LSL_c3___PgZ___Zt_D_, }, - // ZPMULLB ., ., . + // ZLDFF1D [, .D], /Z, { .D } { - goOp: AZPMULLB, - fixedBits: 0x45006800, - args: Zm_Tb__Zn_Tb__Zd_T__3, + goOp: AZLDFF1D, + fixedBits: 0xc5c0e000, + args: XnSP__Zm_D___PgZ___Zt_D_, }, - }, - // ZPMULLT - { - // ZPMULLT .D, .D, .Q + // ZLDFF1D [, .D, ], /Z, { .D } { - goOp: AZPMULLT, - fixedBits: 0x45006c00, - args: Zm_D__Zn_D__Zd_Q, + goOp: AZLDFF1D, + fixedBits: 0xc5806000, + args: XnSP__Zm_D__mod___PgZ___Zt_D_, }, - // ZPMULLT ., ., . + // ZLDFF1D [, .D, #3], /Z, { .D } { - goOp: AZPMULLT, - fixedBits: 0x45006c00, - args: Zm_Tb__Zn_Tb__Zd_T__3, + goOp: AZLDFF1D, + fixedBits: 0xc5a06000, + args: XnSP__Zm_D__mod_c3___PgZ___Zt_D_, }, }, - // ZRADDHNB + // ZLDFF1H { - // ZRADDHNB ., ., . + // ZLDFF1H [{, , LSL #1}], /Z, { .D } { - goOp: AZRADDHNB, - fixedBits: 0x45206800, - args: Zm_Tb__Zn_Tb__Zd_T__2, + goOp: AZLDFF1H, + fixedBits: 0xa4e06000, + args: XnSP__Xm__LSL_c1___PgZ___Zt_D__V2, + }, + // ZLDFF1H [{, , LSL #1}], /Z, { .H } + { + goOp: AZLDFF1H, + fixedBits: 0xa4a06000, + args: XnSP__Xm__LSL_c1___PgZ___Zt_H__V2, + }, + // ZLDFF1H [{, , LSL #1}], /Z, { .S } + { + goOp: AZLDFF1H, + fixedBits: 0xa4c06000, + args: XnSP__Xm__LSL_c1___PgZ___Zt_S__V2, + }, + // ZLDFF1H [, .D, LSL #1], /Z, { .D } + { + goOp: AZLDFF1H, + fixedBits: 0xc4e0e000, + args: XnSP__Zm_D__LSL_c1___PgZ___Zt_D_, + }, + // ZLDFF1H [, .D], /Z, { .D } + { + goOp: AZLDFF1H, + fixedBits: 0xc4c0e000, + args: XnSP__Zm_D___PgZ___Zt_D_, + }, + // ZLDFF1H [, .D, ], /Z, { .D } + { + goOp: AZLDFF1H, + fixedBits: 0xc4806000, + args: XnSP__Zm_D__mod___PgZ___Zt_D_, + }, + // ZLDFF1H [, .D, #1], /Z, { .D } + { + goOp: AZLDFF1H, + fixedBits: 0xc4a06000, + args: XnSP__Zm_D__mod_c1___PgZ___Zt_D_, + }, + // ZLDFF1H [, .S, ], /Z, { .S } + { + goOp: AZLDFF1H, + fixedBits: 0x84806000, + args: XnSP__Zm_S__mod___PgZ___Zt_S_, + }, + // ZLDFF1H [, .S, #1], /Z, { .S } + { + goOp: AZLDFF1H, + fixedBits: 0x84a06000, + args: XnSP__Zm_S__mod_c1___PgZ___Zt_S_, }, }, - // ZRADDHNT + // ZLDFF1SB { - // ZRADDHNT ., ., . + // ZLDFF1SB [{, }], /Z, { .D } { - goOp: AZRADDHNT, - fixedBits: 0x45206c00, - args: Zm_Tb__Zn_Tb__Zd_T__2, + goOp: AZLDFF1SB, + fixedBits: 0xa5806000, + args: XnSP__Xm___PgZ___Zt_D__V2, + }, + // ZLDFF1SB [{, }], /Z, { .H } + { + goOp: AZLDFF1SB, + fixedBits: 0xa5c06000, + args: XnSP__Xm___PgZ___Zt_H__V2, + }, + // ZLDFF1SB [{, }], /Z, { .S } + { + goOp: AZLDFF1SB, + fixedBits: 0xa5a06000, + args: XnSP__Xm___PgZ___Zt_S__V2, + }, + // ZLDFF1SB [, .D], /Z, { .D } + { + goOp: AZLDFF1SB, + fixedBits: 0xc440a000, + args: XnSP__Zm_D___PgZ___Zt_D_, + }, + // ZLDFF1SB [, .D, ], /Z, { .D } + { + goOp: AZLDFF1SB, + fixedBits: 0xc4002000, + args: XnSP__Zm_D__mod___PgZ___Zt_D_, + }, + // ZLDFF1SB [, .S, ], /Z, { .S } + { + goOp: AZLDFF1SB, + fixedBits: 0x84002000, + args: XnSP__Zm_S__mod___PgZ___Zt_S_, }, }, - // ZRAX1 + // ZLDFF1SH { - // ZRAX1 .D, .D, .D + // ZLDFF1SH [{, , LSL #1}], /Z, { .D } { - goOp: AZRAX1, - fixedBits: 0x4520f400, - args: Zm_D__Zn_D__Zd_D, + goOp: AZLDFF1SH, + fixedBits: 0xa5006000, + args: XnSP__Xm__LSL_c1___PgZ___Zt_D__V2, + }, + // ZLDFF1SH [{, , LSL #1}], /Z, { .S } + { + goOp: AZLDFF1SH, + fixedBits: 0xa5206000, + args: XnSP__Xm__LSL_c1___PgZ___Zt_S__V2, + }, + // ZLDFF1SH [, .D, LSL #1], /Z, { .D } + { + goOp: AZLDFF1SH, + fixedBits: 0xc4e0a000, + args: XnSP__Zm_D__LSL_c1___PgZ___Zt_D_, + }, + // ZLDFF1SH [, .D], /Z, { .D } + { + goOp: AZLDFF1SH, + fixedBits: 0xc4c0a000, + args: XnSP__Zm_D___PgZ___Zt_D_, + }, + // ZLDFF1SH [, .D, ], /Z, { .D } + { + goOp: AZLDFF1SH, + fixedBits: 0xc4802000, + args: XnSP__Zm_D__mod___PgZ___Zt_D_, + }, + // ZLDFF1SH [, .D, #1], /Z, { .D } + { + goOp: AZLDFF1SH, + fixedBits: 0xc4a02000, + args: XnSP__Zm_D__mod_c1___PgZ___Zt_D_, + }, + // ZLDFF1SH [, .S, ], /Z, { .S } + { + goOp: AZLDFF1SH, + fixedBits: 0x84802000, + args: XnSP__Zm_S__mod___PgZ___Zt_S_, + }, + // ZLDFF1SH [, .S, #1], /Z, { .S } + { + goOp: AZLDFF1SH, + fixedBits: 0x84a02000, + args: XnSP__Zm_S__mod_c1___PgZ___Zt_S_, }, }, - // ZRBIT + // ZLDFF1SW { - // ZRBIT ., /M, . + // ZLDFF1SW [{, , LSL #2}], /Z, { .D } { - goOp: AZRBIT, - fixedBits: 0x5278000, - args: Zn_T__PgM__Zd_T__2, + goOp: AZLDFF1SW, + fixedBits: 0xa4806000, + args: XnSP__Xm__LSL_c2___PgZ___Zt_D__V2, }, - // ZRBIT ., /Z, . + // ZLDFF1SW [, .D, LSL #2], /Z, { .D } { - goOp: AZRBIT, - fixedBits: 0x527a000, - args: Zn_T__PgZ__Zd_T__2, + goOp: AZLDFF1SW, + fixedBits: 0xc560a000, + args: XnSP__Zm_D__LSL_c2___PgZ___Zt_D_, + }, + // ZLDFF1SW [, .D], /Z, { .D } + { + goOp: AZLDFF1SW, + fixedBits: 0xc540a000, + args: XnSP__Zm_D___PgZ___Zt_D_, + }, + // ZLDFF1SW [, .D, ], /Z, { .D } + { + goOp: AZLDFF1SW, + fixedBits: 0xc5002000, + args: XnSP__Zm_D__mod___PgZ___Zt_D_, + }, + // ZLDFF1SW [, .D, #2], /Z, { .D } + { + goOp: AZLDFF1SW, + fixedBits: 0xc5202000, + args: XnSP__Zm_D__mod_c2___PgZ___Zt_D_, }, }, - // ZREV + // ZLDFF1W { - // ZREV ., . + // ZLDFF1W [{, , LSL #2}], /Z, { .D } { - goOp: AZREV, - fixedBits: 0x5383800, - args: Zn_T__Zd_T__2, + goOp: AZLDFF1W, + fixedBits: 0xa5606000, + args: XnSP__Xm__LSL_c2___PgZ___Zt_D__V2, + }, + // ZLDFF1W [{, , LSL #2}], /Z, { .S } + { + goOp: AZLDFF1W, + fixedBits: 0xa5406000, + args: XnSP__Xm__LSL_c2___PgZ___Zt_S__V2, + }, + // ZLDFF1W [, .D, LSL #2], /Z, { .D } + { + goOp: AZLDFF1W, + fixedBits: 0xc560e000, + args: XnSP__Zm_D__LSL_c2___PgZ___Zt_D_, + }, + // ZLDFF1W [, .D], /Z, { .D } + { + goOp: AZLDFF1W, + fixedBits: 0xc540e000, + args: XnSP__Zm_D___PgZ___Zt_D_, + }, + // ZLDFF1W [, .D, ], /Z, { .D } + { + goOp: AZLDFF1W, + fixedBits: 0xc5006000, + args: XnSP__Zm_D__mod___PgZ___Zt_D_, + }, + // ZLDFF1W [, .D, #2], /Z, { .D } + { + goOp: AZLDFF1W, + fixedBits: 0xc5206000, + args: XnSP__Zm_D__mod_c2___PgZ___Zt_D_, + }, + // ZLDFF1W [, .S, ], /Z, { .S } + { + goOp: AZLDFF1W, + fixedBits: 0x85006000, + args: XnSP__Zm_S__mod___PgZ___Zt_S_, + }, + // ZLDFF1W [, .S, #2], /Z, { .S } + { + goOp: AZLDFF1W, + fixedBits: 0x85206000, + args: XnSP__Zm_S__mod_c2___PgZ___Zt_S_, }, }, - // ZREVB + // ZLDNT1B { - // ZREVB ., /M, . + // ZLDNT1B [, ], /Z, { .B } { - goOp: AZREVB, - fixedBits: 0x5248000, - args: Zn_T__PgM__Zd_T__4, + goOp: AZLDNT1B, + fixedBits: 0xa400c000, + args: XnSP__Xm___PgZ___Zt_B_, }, - // ZREVB ., /Z, . + // ZLDNT1B [.D{, }], /Z, { .D } { - goOp: AZREVB, - fixedBits: 0x524a000, - args: Zn_T__PgZ__Zd_T__4, + goOp: AZLDNT1B, + fixedBits: 0xc400c000, + args: Zn_D__Xm___PgZ___Zt_D_, + }, + // ZLDNT1B [.S{, }], /Z, { .S } + { + goOp: AZLDNT1B, + fixedBits: 0x8400a000, + args: Zn_S__Xm___PgZ___Zt_S_, }, }, - // ZREVD + // ZLDNT1D { - // ZREVD .Q, /M, .Q + // ZLDNT1D [, , LSL #3], /Z, { .D } { - goOp: AZREVD, - fixedBits: 0x52e8000, - args: Zn_Q__PgM__Zd_Q, + goOp: AZLDNT1D, + fixedBits: 0xa580c000, + args: XnSP__Xm__LSL_c3___PgZ___Zt_D_, }, - // ZREVD .Q, /Z, .Q + // ZLDNT1D [.D{, }], /Z, { .D } { - goOp: AZREVD, - fixedBits: 0x52ea000, - args: Zn_Q__PgZ__Zd_Q, + goOp: AZLDNT1D, + fixedBits: 0xc580c000, + args: Zn_D__Xm___PgZ___Zt_D_, }, }, - // ZREVH + // ZLDNT1H { - // ZREVH ., /M, . + // ZLDNT1H [, , LSL #1], /Z, { .H } { - goOp: AZREVH, - fixedBits: 0x5a58000, - args: Zn_T__PgM__Zd_T__5, + goOp: AZLDNT1H, + fixedBits: 0xa480c000, + args: XnSP__Xm__LSL_c1___PgZ___Zt_H_, }, - // ZREVH ., /Z, . + // ZLDNT1H [.D{, }], /Z, { .D } { - goOp: AZREVH, - fixedBits: 0x5a5a000, - args: Zn_T__PgZ__Zd_T__5, + goOp: AZLDNT1H, + fixedBits: 0xc480c000, + args: Zn_D__Xm___PgZ___Zt_D_, + }, + // ZLDNT1H [.S{, }], /Z, { .S } + { + goOp: AZLDNT1H, + fixedBits: 0x8480a000, + args: Zn_S__Xm___PgZ___Zt_S_, }, }, - // ZREVW + // ZLDNT1SB { - // ZREVW .D, /M, .D + // ZLDNT1SB [.D{, }], /Z, { .D } { - goOp: AZREVW, - fixedBits: 0x5e68000, - args: Zn_D__PgM__Zd_D, + goOp: AZLDNT1SB, + fixedBits: 0xc4008000, + args: Zn_D__Xm___PgZ___Zt_D_, }, - // ZREVW .D, /Z, .D + // ZLDNT1SB [.S{, }], /Z, { .S } { - goOp: AZREVW, - fixedBits: 0x5e6a000, - args: Zn_D__PgZ__Zd_D, + goOp: AZLDNT1SB, + fixedBits: 0x84008000, + args: Zn_S__Xm___PgZ___Zt_S_, }, }, - // ZRSHRNB + // ZLDNT1SH { - // ZRSHRNB #, ., . + // ZLDNT1SH [.D{, }], /Z, { .D } { - goOp: AZRSHRNB, - fixedBits: 0x45201800, - args: cconst__Zn_Tb__Zd_T__1, + goOp: AZLDNT1SH, + fixedBits: 0xc4808000, + args: Zn_D__Xm___PgZ___Zt_D_, + }, + // ZLDNT1SH [.S{, }], /Z, { .S } + { + goOp: AZLDNT1SH, + fixedBits: 0x84808000, + args: Zn_S__Xm___PgZ___Zt_S_, }, }, - // ZRSHRNT + // ZLDNT1SW { - // ZRSHRNT #, ., . + // ZLDNT1SW [.D{, }], /Z, { .D } { - goOp: AZRSHRNT, - fixedBits: 0x45201c00, - args: cconst__Zn_Tb__Zd_T__1, + goOp: AZLDNT1SW, + fixedBits: 0xc5008000, + args: Zn_D__Xm___PgZ___Zt_D_, }, }, - // ZRSUBHNB + // ZLDNT1W { - // ZRSUBHNB ., ., . + // ZLDNT1W [, , LSL #2], /Z, { .S } { - goOp: AZRSUBHNB, - fixedBits: 0x45207800, - args: Zm_Tb__Zn_Tb__Zd_T__2, + goOp: AZLDNT1W, + fixedBits: 0xa500c000, + args: XnSP__Xm__LSL_c2___PgZ___Zt_S_, }, - }, - // ZRSUBHNT - { - // ZRSUBHNT ., ., . + // ZLDNT1W [.D{, }], /Z, { .D } { - goOp: AZRSUBHNT, - fixedBits: 0x45207c00, - args: Zm_Tb__Zn_Tb__Zd_T__2, + goOp: AZLDNT1W, + fixedBits: 0xc500c000, + args: Zn_D__Xm___PgZ___Zt_D_, }, - }, - // ZSABA - { - // ZSABA ., ., . + // ZLDNT1W [.S{, }], /Z, { .S } { - goOp: AZSABA, - fixedBits: 0x4500f800, - args: Zm_T__Zn_T__Zda_T__2, + goOp: AZLDNT1W, + fixedBits: 0x8500a000, + args: Zn_S__Xm___PgZ___Zt_S_, }, }, - // ZSABAL + // ZLSL { - // ZSABAL ., ., . + // ZLSL .D, ., /M, . { - goOp: AZSABAL, - fixedBits: 0x4400d400, - args: Zm_Tb__Zn_Tb__Zda_T__1, + goOp: AZLSL, + fixedBits: 0x41b8000, + args: Zm_D__Zdn_T__PgM__Zdn_T, }, - }, - // ZSABALB - { - // ZSABALB ., ., . + // ZLSL .D, ., . { - goOp: AZSABALB, - fixedBits: 0x4500c000, - args: Zm_Tb__Zn_Tb__Zda_T__1, + goOp: AZLSL, + fixedBits: 0x4208c00, + args: Zm_D__Zn_T__Zd_T, }, - }, - // ZSABALT - { - // ZSABALT ., ., . + // ZLSL ., ., /M, . { - goOp: AZSABALT, - fixedBits: 0x4500c400, - args: Zm_Tb__Zn_Tb__Zda_T__1, + goOp: AZLSL, + fixedBits: 0x4138000, + args: Zm_T__Zdn_T__PgM__Zdn_T__1, + }, + // ZLSL #, ., /M, . + { + goOp: AZLSL, + fixedBits: 0x4038000, + args: cconst__Zdn_T__PgM__Zdn_T__2, + }, + // ZLSL #, ., . + { + goOp: AZLSL, + fixedBits: 0x4209c00, + args: cconst__Zn_T__Zd_T__2, }, }, - // ZSABD + // ZLSLR { - // ZSABD ., ., /M, . + // ZLSLR ., ., /M, . { - goOp: AZSABD, - fixedBits: 0x40c0000, + goOp: AZLSLR, + fixedBits: 0x4178000, args: Zm_T__Zdn_T__PgM__Zdn_T__1, }, }, - // ZSABDLB + // ZLSR { - // ZSABDLB ., ., . + // ZLSR .D, ., /M, . { - goOp: AZSABDLB, - fixedBits: 0x45003000, - args: Zm_Tb__Zn_Tb__Zd_T__1, + goOp: AZLSR, + fixedBits: 0x4198000, + args: Zm_D__Zdn_T__PgM__Zdn_T, }, - }, - // ZSABDLT - { - // ZSABDLT ., ., . + // ZLSR .D, ., . { - goOp: AZSABDLT, - fixedBits: 0x45003400, - args: Zm_Tb__Zn_Tb__Zd_T__1, + goOp: AZLSR, + fixedBits: 0x4208400, + args: Zm_D__Zn_T__Zd_T, }, - }, - // ZSADALP - { - // ZSADALP ., /M, . + // ZLSR ., ., /M, . { - goOp: AZSADALP, - fixedBits: 0x4404a000, - args: Zn_Tb__PgM__Zda_T, + goOp: AZLSR, + fixedBits: 0x4118000, + args: Zm_T__Zdn_T__PgM__Zdn_T__1, }, - }, - // ZSADDLB - { - // ZSADDLB ., ., . + // ZLSR #, ., /M, . { - goOp: AZSADDLB, - fixedBits: 0x45000000, - args: Zm_Tb__Zn_Tb__Zd_T__1, + goOp: AZLSR, + fixedBits: 0x4018000, + args: cconst__Zdn_T__PgM__Zdn_T__1, }, - }, - // ZSADDLBT - { - // ZSADDLBT ., ., . + // ZLSR #, ., . { - goOp: AZSADDLBT, - fixedBits: 0x45008000, - args: Zm_Tb__Zn_Tb__Zd_T__1, + goOp: AZLSR, + fixedBits: 0x4209400, + args: cconst__Zn_T__Zd_T__1, }, }, - // ZSADDLT + // ZLSRR { - // ZSADDLT ., ., . + // ZLSRR ., ., /M, . { - goOp: AZSADDLT, - fixedBits: 0x45000400, - args: Zm_Tb__Zn_Tb__Zd_T__1, + goOp: AZLSRR, + fixedBits: 0x4158000, + args: Zm_T__Zdn_T__PgM__Zdn_T__1, }, }, - // ZSADDVD + // ZLUTI2 { - // ZSADDVD ., ,
+ // ZLUTI2 [], { .B }, .B { - goOp: AZSADDVD, - fixedBits: 0x4002000, - args: Zn_T__Pg__Dd__1, + goOp: AZLUTI2, + fixedBits: 0x4520b000, + args: Zm_index____Zn_B___Zd_B__1, + }, + // ZLUTI2 [], { .H }, .H + { + goOp: AZLUTI2, + fixedBits: 0x4520a800, + args: Zm_index____Zn_H___Zd_H__1, }, }, - // ZSADDWB + // ZLUTI4 { - // ZSADDWB ., ., . + // ZLUTI4 [], { .H, .H }, .H { - goOp: AZSADDWB, - fixedBits: 0x45004000, - args: Zm_Tb__Zn_T__Zd_T, + goOp: AZLUTI4, + fixedBits: 0x4520b400, + args: Zm_index____Zn1_H__Zn2_H___Zd_H__1, + }, + // ZLUTI4 [], { .B }, .B + { + goOp: AZLUTI4, + fixedBits: 0x4560a400, + args: Zm_index____Zn_B___Zd_B__2, + }, + // ZLUTI4 [], { .H }, .H + { + goOp: AZLUTI4, + fixedBits: 0x4520bc00, + args: Zm_index____Zn_H___Zd_H__2, }, }, - // ZSADDWT + // ZLUTI6 { - // ZSADDWT ., ., . + // ZLUTI6 , { .B, .B }, .B { - goOp: AZSADDWT, - fixedBits: 0x45004400, - args: Zm_Tb__Zn_T__Zd_T, + goOp: AZLUTI6, + fixedBits: 0x4520ac00, + args: Zm___Zn1_B__Zn2_B___Zd_B, + }, + // ZLUTI6 [], { .H, .H }, .H + { + goOp: AZLUTI6, + fixedBits: 0x4560ac00, + args: Zm_index____Zn1_H__Zn2_H___Zd_H__2, }, }, - // ZSBCLB + // ZMAD { - // ZSBCLB ., ., . + // ZMAD ., ., /M, . { - goOp: AZSBCLB, - fixedBits: 0x4580d000, - args: Zm_T__Zn_T__Zda_T__1, + goOp: AZMAD, + fixedBits: 0x400c000, + args: Za_T__Zm_T__PgM__Zdn_T__2, }, }, - // ZSBCLT + // ZMADPT { - // ZSBCLT ., ., . + // ZMADPT .D, .D, .D { - goOp: AZSBCLT, - fixedBits: 0x4580d400, - args: Zm_T__Zn_T__Zda_T__1, + goOp: AZMADPT, + fixedBits: 0x44c0d800, + args: Za_D__Zm_D__Zdn_D, }, }, - // ZSCLAMP + // ZMATCH { - // ZSCLAMP ., ., . + // ZMATCH ., ., /Z, . { - goOp: AZSCLAMP, - fixedBits: 0x4400c000, - args: Zm_T__Zn_T__Zd_T__1, + goOp: AZMATCH, + fixedBits: 0x45208000, + args: Zm_T__Zn_T__PgZ__Pd_T__3, }, }, - // ZSCVTF + // ZMLA { - // ZSCVTF .D, /M, .D + // ZMLA ., ., /M, . { - goOp: AZSCVTF, - fixedBits: 0x65d6a000, - args: Zn_D__PgM__Zd_D, + goOp: AZMLA, + fixedBits: 0x4004000, + args: Zm_T__Zn_T__PgM__Zda_T__2, }, - // ZSCVTF .D, /M, .H + // ZMLA .D[], .D, .D { - goOp: AZSCVTF, - fixedBits: 0x6556a000, - args: Zn_D__PgM__Zd_H, + goOp: AZMLA, + fixedBits: 0x44e00800, + args: Zm_D_imm___Zn_D__Zda_D__1, }, - // ZSCVTF .D, /M, .S + // ZMLA .H[], .H, .H { - goOp: AZSCVTF, - fixedBits: 0x65d4a000, - args: Zn_D__PgM__Zd_S, + goOp: AZMLA, + fixedBits: 0x44200800, + args: Zm_H_imm___Zn_H__Zda_H__1, }, - // ZSCVTF .D, /Z, .D + // ZMLA .S[], .S, .S { - goOp: AZSCVTF, - fixedBits: 0x64ddc000, - args: Zn_D__PgZ__Zd_D, + goOp: AZMLA, + fixedBits: 0x44a00800, + args: Zm_S_imm___Zn_S__Zda_S__1, }, - // ZSCVTF .D, /Z, .H + }, + // ZMLAPT + { + // ZMLAPT .D, .D, .D { - goOp: AZSCVTF, - fixedBits: 0x645dc000, - args: Zn_D__PgZ__Zd_H, + goOp: AZMLAPT, + fixedBits: 0x44c0d000, + args: Zm_D__Zn_D__Zda_D, }, - // ZSCVTF .D, /Z, .S + }, + // ZMLS + { + // ZMLS ., ., /M, . { - goOp: AZSCVTF, - fixedBits: 0x64dd8000, - args: Zn_D__PgZ__Zd_S, + goOp: AZMLS, + fixedBits: 0x4006000, + args: Zm_T__Zn_T__PgM__Zda_T__2, }, - // ZSCVTF .H, /M, .H + // ZMLS .D[], .D, .D { - goOp: AZSCVTF, - fixedBits: 0x6552a000, - args: Zn_H__PgM__Zd_H, + goOp: AZMLS, + fixedBits: 0x44e00c00, + args: Zm_D_imm___Zn_D__Zda_D__1, }, - // ZSCVTF .H, /Z, .H + // ZMLS .H[], .H, .H { - goOp: AZSCVTF, - fixedBits: 0x645cc000, - args: Zn_H__PgZ__Zd_H, + goOp: AZMLS, + fixedBits: 0x44200c00, + args: Zm_H_imm___Zn_H__Zda_H__1, }, - // ZSCVTF .S, /M, .D + // ZMLS .S[], .S, .S { - goOp: AZSCVTF, - fixedBits: 0x65d0a000, - args: Zn_S__PgM__Zd_D, + goOp: AZMLS, + fixedBits: 0x44a00c00, + args: Zm_S_imm___Zn_S__Zda_S__1, }, - // ZSCVTF .S, /M, .H + }, + // ZMOVPRFX + { + // ZMOVPRFX ., /, . { - goOp: AZSCVTF, - fixedBits: 0x6554a000, - args: Zn_S__PgM__Zd_H, + goOp: AZMOVPRFX, + fixedBits: 0x4102000, + args: Zn_T__PgZM__Zd_T, }, - // ZSCVTF .S, /M, .S + // ZMOVPRFX , { - goOp: AZSCVTF, - fixedBits: 0x6594a000, - args: Zn_S__PgM__Zd_S, + goOp: AZMOVPRFX, + fixedBits: 0x420bc00, + args: Zn__Zd, }, - // ZSCVTF .S, /Z, .D + }, + // ZMSB + { + // ZMSB ., ., /M, . { - goOp: AZSCVTF, - fixedBits: 0x64dc8000, - args: Zn_S__PgZ__Zd_D, + goOp: AZMSB, + fixedBits: 0x400e000, + args: Za_T__Zm_T__PgM__Zdn_T__2, }, - // ZSCVTF .S, /Z, .H + }, + // ZMUL + { + // ZMUL ., ., /M, . { - goOp: AZSCVTF, - fixedBits: 0x645d8000, - args: Zn_S__PgZ__Zd_H, + goOp: AZMUL, + fixedBits: 0x4100000, + args: Zm_T__Zdn_T__PgM__Zdn_T__1, }, - // ZSCVTF .S, /Z, .S + // ZMUL ., ., . { - goOp: AZSCVTF, - fixedBits: 0x649d8000, - args: Zn_S__PgZ__Zd_S, + goOp: AZMUL, + fixedBits: 0x4206000, + args: Zm_T__Zn_T__Zd_T__1, }, - // ZSCVTF ., . + // ZMUL .D[], .D, .D { - goOp: AZSCVTF, - fixedBits: 0x650c3000, - args: Zn_Tb__Zd_T__1, + goOp: AZMUL, + fixedBits: 0x44e0f800, + args: Zm_D_imm___Zn_D__Zd_D__1, }, - }, - // ZSCVTFLT - { - // ZSCVTFLT ., . + // ZMUL .H[], .H, .H { - goOp: AZSCVTFLT, - fixedBits: 0x650c3800, - args: Zn_Tb__Zd_T__1, + goOp: AZMUL, + fixedBits: 0x4420f800, + args: Zm_H_imm___Zn_H__Zd_H__1, + }, + // ZMUL .S[], .S, .S + { + goOp: AZMUL, + fixedBits: 0x44a0f800, + args: Zm_S_imm___Zn_S__Zd_S__1, + }, + // ZMUL #, ., . + { + goOp: AZMUL, + fixedBits: 0x2530c000, + args: cimm__Zdn_T__Zdn_T__1, }, }, - // ZSDIV + // ZNBSL { - // ZSDIV ., ., /M, . + // ZNBSL .D, .D, .D, .D { - goOp: AZSDIV, - fixedBits: 0x4940000, - args: Zm_T__Zdn_T__PgM__Zdn_T__4, + goOp: AZNBSL, + fixedBits: 0x4e03c00, + args: Zk_D__Zm_D__Zdn_D__Zdn_D, }, }, - // ZSDIVR + // ZNEG { - // ZSDIVR ., ., /M, . + // ZNEG ., /M, . { - goOp: AZSDIVR, - fixedBits: 0x4960000, - args: Zm_T__Zdn_T__PgM__Zdn_T__4, + goOp: AZNEG, + fixedBits: 0x417a000, + args: Zn_T__PgM__Zd_T__2, + }, + // ZNEG ., /Z, . + { + goOp: AZNEG, + fixedBits: 0x407a000, + args: Zn_T__PgZ__Zd_T__2, }, }, - // ZSDOT + // ZNMATCH { - // ZSDOT .B, .B, .H + // ZNMATCH ., ., /Z, . { - goOp: AZSDOT, - fixedBits: 0x44400000, - args: Zm_B__Zn_B__Zda_H, + goOp: AZNMATCH, + fixedBits: 0x45208010, + args: Zm_T__Zn_T__PgZ__Pd_T__3, }, - // ZSDOT .H, .H, .S + }, + // ZNOT + { + // ZNOT ., /M, . { - goOp: AZSDOT, - fixedBits: 0x4400c800, - args: Zm_H__Zn_H__Zda_S, + goOp: AZNOT, + fixedBits: 0x41ea000, + args: Zn_T__PgM__Zd_T__2, }, - // ZSDOT ., ., . + // ZNOT ., /Z, . { - goOp: AZSDOT, - fixedBits: 0x44800000, - args: Zm_Tb__Zn_Tb__Zda_T__2, + goOp: AZNOT, + fixedBits: 0x40ea000, + args: Zn_T__PgZ__Zd_T__2, }, - // ZSDOT .B[], .B, .H + }, + // ZORQV + { + // ZORQV ., , . { - goOp: AZSDOT, - fixedBits: 0x44200000, - args: Zm_B_imm___Zn_B__Zda_H__2, + goOp: AZORQV, + fixedBits: 0x41c2000, + args: Zn_Tb__Pg__Vd_T__1, }, - // ZSDOT .B[], .B, .S + }, + // ZORR + { + // ZORR .D, .D, .D { - goOp: AZSDOT, - fixedBits: 0x44a00000, - args: Zm_B_imm___Zn_B__Zda_S__3, + goOp: AZORR, + fixedBits: 0x4603000, + args: Zm_D__Zn_D__Zd_D, }, - // ZSDOT .H[], .H, .D + // ZORR ., ., /M, . { - goOp: AZSDOT, - fixedBits: 0x44e00000, - args: Zm_H_imm___Zn_H__Zda_D, + goOp: AZORR, + fixedBits: 0x4180000, + args: Zm_T__Zdn_T__PgM__Zdn_T__1, }, - // ZSDOT .H[], .H, .S + // ZORR #, ., . { - goOp: AZSDOT, - fixedBits: 0x4480c800, - args: Zm_H_imm___Zn_H__Zda_S__4, + goOp: AZORR, + fixedBits: 0x5000000, + args: cconst__Zdn_T__Zdn_T, }, }, - // ZSEL + // ZORVB { - // ZSEL ., ., , . + // ZORVB ., , { - goOp: AZSEL, - fixedBits: 0x520c000, - args: Zm_T__Zn_T__Pv__Zd_T, + goOp: AZORVB, + fixedBits: 0x4182000, + args: Zn_T__Pg__Vd__1, }, }, - // ZSHADD + // ZORVD { - // ZSHADD ., ., /M, . + // ZORVD ., , { - goOp: AZSHADD, - fixedBits: 0x44108000, - args: Zm_T__Zdn_T__PgM__Zdn_T__1, + goOp: AZORVD, + fixedBits: 0x4d82000, + args: Zn_T__Pg__Vd__1, }, }, - // ZSHRNB + // ZORVH { - // ZSHRNB #, ., . + // ZORVH ., , { - goOp: AZSHRNB, - fixedBits: 0x45201000, - args: cconst__Zn_Tb__Zd_T__1, + goOp: AZORVH, + fixedBits: 0x4582000, + args: Zn_T__Pg__Vd__1, }, }, - // ZSHRNT + // ZORVS { - // ZSHRNT #, ., . + // ZORVS ., , { - goOp: AZSHRNT, - fixedBits: 0x45201400, - args: cconst__Zn_Tb__Zd_T__1, + goOp: AZORVS, + fixedBits: 0x4982000, + args: Zn_T__Pg__Vd__1, }, }, - // ZSHSUB + // ZPMOV { - // ZSHSUB ., ., /M, . + // ZPMOV .B, { - goOp: AZSHSUB, - fixedBits: 0x44128000, - args: Zm_T__Zdn_T__PgM__Zdn_T__1, + goOp: AZPMOV, + fixedBits: 0x52b3800, + args: Pn_B__Zd, }, - }, - // ZSHSUBR - { - // ZSHSUBR ., ., /M, . + // ZPMOV , .B { - goOp: AZSHSUBR, - fixedBits: 0x44168000, - args: Zm_T__Zdn_T__PgM__Zdn_T__1, + goOp: AZPMOV, + fixedBits: 0x52a3800, + args: Zn__Pd_B, }, - }, - // ZSLI - { - // ZSLI #, ., . + // ZPMOV .D, {[]} { - goOp: AZSLI, - fixedBits: 0x4500f400, - args: cconst__Zn_T__Zd_T__2, + goOp: AZPMOV, + fixedBits: 0x5a93800, + args: Pn_D__Zd_imm_, }, - }, - // ZSM4E - { - // ZSM4E .S, .S, .S + // ZPMOV .H, {[]} { - goOp: AZSM4E, - fixedBits: 0x4523e000, - args: Zm_S__Zdn_S__Zdn_S, + goOp: AZPMOV, + fixedBits: 0x52d3800, + args: Pn_H__Zd_imm_, + }, + // ZPMOV .S, {[]} + { + goOp: AZPMOV, + fixedBits: 0x5693800, + args: Pn_S__Zd_imm_, + }, + // ZPMOV {[]}, .D + { + goOp: AZPMOV, + fixedBits: 0x5a83800, + args: Zn_imm___Pd_D, + }, + // ZPMOV {[]}, .H + { + goOp: AZPMOV, + fixedBits: 0x52c3800, + args: Zn_imm___Pd_H, + }, + // ZPMOV {[]}, .S + { + goOp: AZPMOV, + fixedBits: 0x5683800, + args: Zn_imm___Pd_S, }, }, - // ZSM4EKEY + // ZPMUL { - // ZSM4EKEY .S, .S, .S + // ZPMUL .B, .B, .B { - goOp: AZSM4EKEY, - fixedBits: 0x4520f000, - args: Zm_S__Zn_S__Zd_S, + goOp: AZPMUL, + fixedBits: 0x4206400, + args: Zm_B__Zn_B__Zd_B, }, }, - // ZSMAX + // ZPMULLB { - // ZSMAX ., ., /M, . + // ZPMULLB .D, .D, .Q { - goOp: AZSMAX, - fixedBits: 0x4080000, - args: Zm_T__Zdn_T__PgM__Zdn_T__1, + goOp: AZPMULLB, + fixedBits: 0x45006800, + args: Zm_D__Zn_D__Zd_Q, }, - // ZSMAX #, ., . + // ZPMULLB ., ., . { - goOp: AZSMAX, - fixedBits: 0x2528c000, - args: cimm__Zdn_T__Zdn_T__1, + goOp: AZPMULLB, + fixedBits: 0x45006800, + args: Zm_Tb__Zn_Tb__Zd_T__3, }, }, - // ZSMAXP + // ZPMULLT { - // ZSMAXP ., ., /M, . + // ZPMULLT .D, .D, .Q { - goOp: AZSMAXP, - fixedBits: 0x4414a000, - args: Zm_T__Zdn_T__PgM__Zdn_T__1, + goOp: AZPMULLT, + fixedBits: 0x45006c00, + args: Zm_D__Zn_D__Zd_Q, + }, + // ZPMULLT ., ., . + { + goOp: AZPMULLT, + fixedBits: 0x45006c00, + args: Zm_Tb__Zn_Tb__Zd_T__3, }, }, - // ZSMAXQV + // ZRADDHNB { - // ZSMAXQV ., , . + // ZRADDHNB ., ., . { - goOp: AZSMAXQV, - fixedBits: 0x40c2000, - args: Zn_Tb__Pg__Vd_T__1, + goOp: AZRADDHNB, + fixedBits: 0x45206800, + args: Zm_Tb__Zn_Tb__Zd_T__2, }, }, - // ZSMAXVB + // ZRADDHNT { - // ZSMAXVB ., , + // ZRADDHNT ., ., . { - goOp: AZSMAXVB, - fixedBits: 0x4082000, - args: Zn_T__Pg__Vd__1, + goOp: AZRADDHNT, + fixedBits: 0x45206c00, + args: Zm_Tb__Zn_Tb__Zd_T__2, }, }, - // ZSMAXVD + // ZRAX1 { - // ZSMAXVD ., , + // ZRAX1 .D, .D, .D { - goOp: AZSMAXVD, - fixedBits: 0x4c82000, - args: Zn_T__Pg__Vd__1, + goOp: AZRAX1, + fixedBits: 0x4520f400, + args: Zm_D__Zn_D__Zd_D, }, }, - // ZSMAXVH + // ZRBIT { - // ZSMAXVH ., , + // ZRBIT ., /M, . { - goOp: AZSMAXVH, - fixedBits: 0x4482000, - args: Zn_T__Pg__Vd__1, + goOp: AZRBIT, + fixedBits: 0x5278000, + args: Zn_T__PgM__Zd_T__2, + }, + // ZRBIT ., /Z, . + { + goOp: AZRBIT, + fixedBits: 0x527a000, + args: Zn_T__PgZ__Zd_T__2, }, }, - // ZSMAXVS + // ZREV { - // ZSMAXVS ., , + // ZREV ., . { - goOp: AZSMAXVS, - fixedBits: 0x4882000, - args: Zn_T__Pg__Vd__1, + goOp: AZREV, + fixedBits: 0x5383800, + args: Zn_T__Zd_T__2, }, }, - // ZSMIN + // ZREVB { - // ZSMIN ., ., /M, . + // ZREVB ., /M, . { - goOp: AZSMIN, - fixedBits: 0x40a0000, - args: Zm_T__Zdn_T__PgM__Zdn_T__1, + goOp: AZREVB, + fixedBits: 0x5248000, + args: Zn_T__PgM__Zd_T__4, }, - // ZSMIN #, ., . + // ZREVB ., /Z, . { - goOp: AZSMIN, - fixedBits: 0x252ac000, - args: cimm__Zdn_T__Zdn_T__1, + goOp: AZREVB, + fixedBits: 0x524a000, + args: Zn_T__PgZ__Zd_T__4, }, }, - // ZSMINP + // ZREVD { - // ZSMINP ., ., /M, . + // ZREVD .Q, /M, .Q { - goOp: AZSMINP, - fixedBits: 0x4416a000, - args: Zm_T__Zdn_T__PgM__Zdn_T__1, + goOp: AZREVD, + fixedBits: 0x52e8000, + args: Zn_Q__PgM__Zd_Q, }, - }, - // ZSMINQV - { - // ZSMINQV ., , . + // ZREVD .Q, /Z, .Q { - goOp: AZSMINQV, - fixedBits: 0x40e2000, - args: Zn_Tb__Pg__Vd_T__1, + goOp: AZREVD, + fixedBits: 0x52ea000, + args: Zn_Q__PgZ__Zd_Q, }, }, - // ZSMINVB + // ZREVH { - // ZSMINVB ., , + // ZREVH ., /M, . { - goOp: AZSMINVB, - fixedBits: 0x40a2000, - args: Zn_T__Pg__Vd__1, + goOp: AZREVH, + fixedBits: 0x5a58000, + args: Zn_T__PgM__Zd_T__5, + }, + // ZREVH ., /Z, . + { + goOp: AZREVH, + fixedBits: 0x5a5a000, + args: Zn_T__PgZ__Zd_T__5, }, }, - // ZSMINVD + // ZREVW { - // ZSMINVD ., , + // ZREVW .D, /M, .D { - goOp: AZSMINVD, - fixedBits: 0x4ca2000, - args: Zn_T__Pg__Vd__1, + goOp: AZREVW, + fixedBits: 0x5e68000, + args: Zn_D__PgM__Zd_D, + }, + // ZREVW .D, /Z, .D + { + goOp: AZREVW, + fixedBits: 0x5e6a000, + args: Zn_D__PgZ__Zd_D, }, }, - // ZSMINVH + // ZRSHRNB { - // ZSMINVH ., , + // ZRSHRNB #, ., . { - goOp: AZSMINVH, - fixedBits: 0x44a2000, - args: Zn_T__Pg__Vd__1, + goOp: AZRSHRNB, + fixedBits: 0x45201800, + args: cconst__Zn_Tb__Zd_T__1, }, }, - // ZSMINVS + // ZRSHRNT { - // ZSMINVS ., , + // ZRSHRNT #, ., . { - goOp: AZSMINVS, - fixedBits: 0x48a2000, - args: Zn_T__Pg__Vd__1, + goOp: AZRSHRNT, + fixedBits: 0x45201c00, + args: cconst__Zn_Tb__Zd_T__1, }, }, - // ZSMLALB + // ZRSUBHNB { - // ZSMLALB ., ., . - { - goOp: AZSMLALB, - fixedBits: 0x44004000, - args: Zm_Tb__Zn_Tb__Zda_T__1, - }, - // ZSMLALB .H[], .H, .S - { - goOp: AZSMLALB, - fixedBits: 0x44a08000, - args: Zm_H_imm___Zn_H__Zda_S__1, - }, - // ZSMLALB .S[], .S, .D + // ZRSUBHNB ., ., . { - goOp: AZSMLALB, - fixedBits: 0x44e08000, - args: Zm_S_imm___Zn_S__Zda_D, + goOp: AZRSUBHNB, + fixedBits: 0x45207800, + args: Zm_Tb__Zn_Tb__Zd_T__2, }, }, - // ZSMLALT + // ZRSUBHNT { - // ZSMLALT ., ., . - { - goOp: AZSMLALT, - fixedBits: 0x44004400, - args: Zm_Tb__Zn_Tb__Zda_T__1, - }, - // ZSMLALT .H[], .H, .S + // ZRSUBHNT ., ., . { - goOp: AZSMLALT, - fixedBits: 0x44a08400, - args: Zm_H_imm___Zn_H__Zda_S__1, + goOp: AZRSUBHNT, + fixedBits: 0x45207c00, + args: Zm_Tb__Zn_Tb__Zd_T__2, }, - // ZSMLALT .S[], .S, .D + }, + // ZSABA + { + // ZSABA ., ., . { - goOp: AZSMLALT, - fixedBits: 0x44e08400, - args: Zm_S_imm___Zn_S__Zda_D, + goOp: AZSABA, + fixedBits: 0x4500f800, + args: Zm_T__Zn_T__Zda_T__2, }, }, - // ZSMLSLB + // ZSABAL { - // ZSMLSLB ., ., . + // ZSABAL ., ., . { - goOp: AZSMLSLB, - fixedBits: 0x44005000, + goOp: AZSABAL, + fixedBits: 0x4400d400, args: Zm_Tb__Zn_Tb__Zda_T__1, }, - // ZSMLSLB .H[], .H, .S - { - goOp: AZSMLSLB, - fixedBits: 0x44a0a000, - args: Zm_H_imm___Zn_H__Zda_S__1, - }, - // ZSMLSLB .S[], .S, .D - { - goOp: AZSMLSLB, - fixedBits: 0x44e0a000, - args: Zm_S_imm___Zn_S__Zda_D, - }, }, - // ZSMLSLT + // ZSABALB { - // ZSMLSLT ., ., . + // ZSABALB ., ., . { - goOp: AZSMLSLT, - fixedBits: 0x44005400, + goOp: AZSABALB, + fixedBits: 0x4500c000, args: Zm_Tb__Zn_Tb__Zda_T__1, }, - // ZSMLSLT .H[], .H, .S - { - goOp: AZSMLSLT, - fixedBits: 0x44a0a400, - args: Zm_H_imm___Zn_H__Zda_S__1, - }, - // ZSMLSLT .S[], .S, .D - { - goOp: AZSMLSLT, - fixedBits: 0x44e0a400, - args: Zm_S_imm___Zn_S__Zda_D, - }, }, - // ZSMMLA + // ZSABALT { - // ZSMMLA .B, .B, .S + // ZSABALT ., ., . { - goOp: AZSMMLA, - fixedBits: 0x45009800, - args: Zm_B__Zn_B__Zda_S, + goOp: AZSABALT, + fixedBits: 0x4500c400, + args: Zm_Tb__Zn_Tb__Zda_T__1, }, }, - // ZSMULH + // ZSABD { - // ZSMULH ., ., /M, . + // ZSABD ., ., /M, . { - goOp: AZSMULH, - fixedBits: 0x4120000, + goOp: AZSABD, + fixedBits: 0x40c0000, args: Zm_T__Zdn_T__PgM__Zdn_T__1, }, - // ZSMULH ., ., . - { - goOp: AZSMULH, - fixedBits: 0x4206800, - args: Zm_T__Zn_T__Zd_T__1, - }, }, - // ZSMULLB + // ZSABDLB { - // ZSMULLB ., ., . + // ZSABDLB ., ., . { - goOp: AZSMULLB, - fixedBits: 0x45007000, + goOp: AZSABDLB, + fixedBits: 0x45003000, args: Zm_Tb__Zn_Tb__Zd_T__1, }, - // ZSMULLB .H[], .H, .S - { - goOp: AZSMULLB, - fixedBits: 0x44a0c000, - args: Zm_H_imm___Zn_H__Zd_S, - }, - // ZSMULLB .S[], .S, .D - { - goOp: AZSMULLB, - fixedBits: 0x44e0c000, - args: Zm_S_imm___Zn_S__Zd_D, - }, }, - // ZSMULLT + // ZSABDLT { - // ZSMULLT ., ., . + // ZSABDLT ., ., . { - goOp: AZSMULLT, - fixedBits: 0x45007400, + goOp: AZSABDLT, + fixedBits: 0x45003400, args: Zm_Tb__Zn_Tb__Zd_T__1, }, - // ZSMULLT .H[], .H, .S - { - goOp: AZSMULLT, - fixedBits: 0x44a0c400, - args: Zm_H_imm___Zn_H__Zd_S, - }, - // ZSMULLT .S[], .S, .D + }, + // ZSADALP + { + // ZSADALP ., /M, . { - goOp: AZSMULLT, - fixedBits: 0x44e0c400, - args: Zm_S_imm___Zn_S__Zd_D, + goOp: AZSADALP, + fixedBits: 0x4404a000, + args: Zn_Tb__PgM__Zda_T, }, }, - // ZSPLICE + // ZSADDLB { - // ZSPLICE ., ., , . + // ZSADDLB ., ., . { - goOp: AZSPLICE, - fixedBits: 0x52c8000, - args: Zm_T__Zdn_T__Pv__Zdn_T, + goOp: AZSADDLB, + fixedBits: 0x45000000, + args: Zm_Tb__Zn_Tb__Zd_T__1, }, - // ZSPLICE { ., . }, , . + }, + // ZSADDLBT + { + // ZSADDLBT ., ., . { - goOp: AZSPLICE, - fixedBits: 0x52d8000, - args: _Zn1_T__Zn2_T___Pv__Zd_T, + goOp: AZSADDLBT, + fixedBits: 0x45008000, + args: Zm_Tb__Zn_Tb__Zd_T__1, }, }, - // ZSQABS + // ZSADDLT { - // ZSQABS ., /M, . + // ZSADDLT ., ., . { - goOp: AZSQABS, - fixedBits: 0x4408a000, - args: Zn_T__PgM__Zd_T__2, + goOp: AZSADDLT, + fixedBits: 0x45000400, + args: Zm_Tb__Zn_Tb__Zd_T__1, }, - // ZSQABS ., /Z, . + }, + // ZSADDVD + { + // ZSADDVD ., ,
{ - goOp: AZSQABS, - fixedBits: 0x440aa000, - args: Zn_T__PgZ__Zd_T__2, + goOp: AZSADDVD, + fixedBits: 0x4002000, + args: Zn_T__Pg__Dd__1, }, }, - // ZSQADD + // ZSADDWB { - // ZSQADD ., ., /M, . + // ZSADDWB ., ., . { - goOp: AZSQADD, - fixedBits: 0x44188000, - args: Zm_T__Zdn_T__PgM__Zdn_T__1, + goOp: AZSADDWB, + fixedBits: 0x45004000, + args: Zm_Tb__Zn_T__Zd_T, }, - // ZSQADD ., ., . + }, + // ZSADDWT + { + // ZSADDWT ., ., . { - goOp: AZSQADD, - fixedBits: 0x4201000, - args: Zm_T__Zn_T__Zd_T__1, + goOp: AZSADDWT, + fixedBits: 0x45004400, + args: Zm_Tb__Zn_T__Zd_T, }, - // ZSQADD #{, }, ., . + }, + // ZSBCLB + { + // ZSBCLB ., ., . { - goOp: AZSQADD, - fixedBits: 0x2524c000, - args: cimm__shift__Zdn_T__Zdn_T, + goOp: AZSBCLB, + fixedBits: 0x4580d000, + args: Zm_T__Zn_T__Zda_T__1, }, }, - // ZSQCADD + // ZSBCLT { - // ZSQCADD , ., ., . + // ZSBCLT ., ., . { - goOp: AZSQCADD, - fixedBits: 0x4501d800, - args: const__Zm_T__Zdn_T__Zdn_T, + goOp: AZSBCLT, + fixedBits: 0x4580d400, + args: Zm_T__Zn_T__Zda_T__1, }, }, - // ZSQDECP + // ZSCLAMP { - // ZSQDECP ., . + // ZSCLAMP ., ., . { - goOp: AZSQDECP, - fixedBits: 0x252a8000, - args: Pm_T__Zdn_T, + goOp: AZSCLAMP, + fixedBits: 0x4400c000, + args: Zm_T__Zn_T__Zd_T__1, }, }, - // ZSQDMLALB + // ZSCVTF { - // ZSQDMLALB ., ., . + // ZSCVTF .D, /M, .D { - goOp: AZSQDMLALB, - fixedBits: 0x44006000, - args: Zm_Tb__Zn_Tb__Zda_T__1, - }, - // ZSQDMLALB .H[], .H, .S + goOp: AZSCVTF, + fixedBits: 0x65d6a000, + args: Zn_D__PgM__Zd_D, + }, + // ZSCVTF .D, /M, .H { - goOp: AZSQDMLALB, - fixedBits: 0x44a02000, - args: Zm_H_imm___Zn_H__Zda_S__1, + goOp: AZSCVTF, + fixedBits: 0x6556a000, + args: Zn_D__PgM__Zd_H, }, - // ZSQDMLALB .S[], .S, .D + // ZSCVTF .D, /M, .S { - goOp: AZSQDMLALB, - fixedBits: 0x44e02000, - args: Zm_S_imm___Zn_S__Zda_D, + goOp: AZSCVTF, + fixedBits: 0x65d4a000, + args: Zn_D__PgM__Zd_S, }, - }, - // ZSQDMLALBT - { - // ZSQDMLALBT ., ., . + // ZSCVTF .D, /Z, .D { - goOp: AZSQDMLALBT, - fixedBits: 0x44000800, - args: Zm_Tb__Zn_Tb__Zda_T__1, + goOp: AZSCVTF, + fixedBits: 0x64ddc000, + args: Zn_D__PgZ__Zd_D, }, - }, - // ZSQDMLALT - { - // ZSQDMLALT ., ., . + // ZSCVTF .D, /Z, .H { - goOp: AZSQDMLALT, - fixedBits: 0x44006400, - args: Zm_Tb__Zn_Tb__Zda_T__1, + goOp: AZSCVTF, + fixedBits: 0x645dc000, + args: Zn_D__PgZ__Zd_H, }, - // ZSQDMLALT .H[], .H, .S + // ZSCVTF .D, /Z, .S { - goOp: AZSQDMLALT, - fixedBits: 0x44a02400, - args: Zm_H_imm___Zn_H__Zda_S__1, + goOp: AZSCVTF, + fixedBits: 0x64dd8000, + args: Zn_D__PgZ__Zd_S, }, - // ZSQDMLALT .S[], .S, .D + // ZSCVTF .H, /M, .H { - goOp: AZSQDMLALT, - fixedBits: 0x44e02400, - args: Zm_S_imm___Zn_S__Zda_D, + goOp: AZSCVTF, + fixedBits: 0x6552a000, + args: Zn_H__PgM__Zd_H, }, - }, - // ZSQDMLSLB - { - // ZSQDMLSLB ., ., . + // ZSCVTF .H, /Z, .H { - goOp: AZSQDMLSLB, - fixedBits: 0x44006800, - args: Zm_Tb__Zn_Tb__Zda_T__1, + goOp: AZSCVTF, + fixedBits: 0x645cc000, + args: Zn_H__PgZ__Zd_H, }, - // ZSQDMLSLB .H[], .H, .S + // ZSCVTF .S, /M, .D { - goOp: AZSQDMLSLB, - fixedBits: 0x44a03000, - args: Zm_H_imm___Zn_H__Zda_S__1, + goOp: AZSCVTF, + fixedBits: 0x65d0a000, + args: Zn_S__PgM__Zd_D, }, - // ZSQDMLSLB .S[], .S, .D + // ZSCVTF .S, /M, .H { - goOp: AZSQDMLSLB, - fixedBits: 0x44e03000, - args: Zm_S_imm___Zn_S__Zda_D, + goOp: AZSCVTF, + fixedBits: 0x6554a000, + args: Zn_S__PgM__Zd_H, }, - }, - // ZSQDMLSLBT - { - // ZSQDMLSLBT ., ., . + // ZSCVTF .S, /M, .S { - goOp: AZSQDMLSLBT, - fixedBits: 0x44000c00, - args: Zm_Tb__Zn_Tb__Zda_T__1, + goOp: AZSCVTF, + fixedBits: 0x6594a000, + args: Zn_S__PgM__Zd_S, }, - }, - // ZSQDMLSLT - { - // ZSQDMLSLT ., ., . + // ZSCVTF .S, /Z, .D { - goOp: AZSQDMLSLT, - fixedBits: 0x44006c00, - args: Zm_Tb__Zn_Tb__Zda_T__1, + goOp: AZSCVTF, + fixedBits: 0x64dc8000, + args: Zn_S__PgZ__Zd_D, }, - // ZSQDMLSLT .H[], .H, .S + // ZSCVTF .S, /Z, .H { - goOp: AZSQDMLSLT, - fixedBits: 0x44a03400, - args: Zm_H_imm___Zn_H__Zda_S__1, + goOp: AZSCVTF, + fixedBits: 0x645d8000, + args: Zn_S__PgZ__Zd_H, }, - // ZSQDMLSLT .S[], .S, .D + // ZSCVTF .S, /Z, .S { - goOp: AZSQDMLSLT, - fixedBits: 0x44e03400, - args: Zm_S_imm___Zn_S__Zda_D, + goOp: AZSCVTF, + fixedBits: 0x649d8000, + args: Zn_S__PgZ__Zd_S, }, - }, - // ZSQDMULH - { - // ZSQDMULH ., ., . + // ZSCVTF ., . { - goOp: AZSQDMULH, - fixedBits: 0x4207000, - args: Zm_T__Zn_T__Zd_T__1, + goOp: AZSCVTF, + fixedBits: 0x650c3000, + args: Zn_Tb__Zd_T__1, }, - // ZSQDMULH .D[], .D, .D + }, + // ZSCVTFLT + { + // ZSCVTFLT ., . { - goOp: AZSQDMULH, - fixedBits: 0x44e0f000, - args: Zm_D_imm___Zn_D__Zd_D__1, + goOp: AZSCVTFLT, + fixedBits: 0x650c3800, + args: Zn_Tb__Zd_T__1, }, - // ZSQDMULH .H[], .H, .H + }, + // ZSDIV + { + // ZSDIV ., ., /M, . { - goOp: AZSQDMULH, - fixedBits: 0x4420f000, - args: Zm_H_imm___Zn_H__Zd_H__1, + goOp: AZSDIV, + fixedBits: 0x4940000, + args: Zm_T__Zdn_T__PgM__Zdn_T__4, }, - // ZSQDMULH .S[], .S, .S + }, + // ZSDIVR + { + // ZSDIVR ., ., /M, . { - goOp: AZSQDMULH, - fixedBits: 0x44a0f000, - args: Zm_S_imm___Zn_S__Zd_S__1, + goOp: AZSDIVR, + fixedBits: 0x4960000, + args: Zm_T__Zdn_T__PgM__Zdn_T__4, }, }, - // ZSQDMULLB + // ZSDOT { - // ZSQDMULLB ., ., . + // ZSDOT .B, .B, .H { - goOp: AZSQDMULLB, - fixedBits: 0x45006000, - args: Zm_Tb__Zn_Tb__Zd_T__1, + goOp: AZSDOT, + fixedBits: 0x44400000, + args: Zm_B__Zn_B__Zda_H, }, - // ZSQDMULLB .H[], .H, .S + // ZSDOT .H, .H, .S { - goOp: AZSQDMULLB, - fixedBits: 0x44a0e000, - args: Zm_H_imm___Zn_H__Zd_S, + goOp: AZSDOT, + fixedBits: 0x4400c800, + args: Zm_H__Zn_H__Zda_S, }, - // ZSQDMULLB .S[], .S, .D + // ZSDOT ., ., . { - goOp: AZSQDMULLB, - fixedBits: 0x44e0e000, - args: Zm_S_imm___Zn_S__Zd_D, + goOp: AZSDOT, + fixedBits: 0x44800000, + args: Zm_Tb__Zn_Tb__Zda_T__2, }, - }, - // ZSQDMULLT - { - // ZSQDMULLT ., ., . + // ZSDOT .B[], .B, .H { - goOp: AZSQDMULLT, - fixedBits: 0x45006400, - args: Zm_Tb__Zn_Tb__Zd_T__1, + goOp: AZSDOT, + fixedBits: 0x44200000, + args: Zm_B_imm___Zn_B__Zda_H__2, }, - // ZSQDMULLT .H[], .H, .S + // ZSDOT .B[], .B, .S { - goOp: AZSQDMULLT, - fixedBits: 0x44a0e400, - args: Zm_H_imm___Zn_H__Zd_S, + goOp: AZSDOT, + fixedBits: 0x44a00000, + args: Zm_B_imm___Zn_B__Zda_S__3, }, - // ZSQDMULLT .S[], .S, .D + // ZSDOT .H[], .H, .D { - goOp: AZSQDMULLT, - fixedBits: 0x44e0e400, - args: Zm_S_imm___Zn_S__Zd_D, + goOp: AZSDOT, + fixedBits: 0x44e00000, + args: Zm_H_imm___Zn_H__Zda_D, }, - }, - // ZSQINCP - { - // ZSQINCP ., . + // ZSDOT .H[], .H, .S { - goOp: AZSQINCP, - fixedBits: 0x25288000, - args: Pm_T__Zdn_T, + goOp: AZSDOT, + fixedBits: 0x4480c800, + args: Zm_H_imm___Zn_H__Zda_S__4, }, }, - // ZSQNEG + // ZSEL { - // ZSQNEG ., /M, . + // ZSEL ., ., , . { - goOp: AZSQNEG, - fixedBits: 0x4409a000, - args: Zn_T__PgM__Zd_T__2, + goOp: AZSEL, + fixedBits: 0x520c000, + args: Zm_T__Zn_T__Pv__Zd_T, }, - // ZSQNEG ., /Z, . + }, + // ZSHADD + { + // ZSHADD ., ., /M, . { - goOp: AZSQNEG, - fixedBits: 0x440ba000, - args: Zn_T__PgZ__Zd_T__2, + goOp: AZSHADD, + fixedBits: 0x44108000, + args: Zm_T__Zdn_T__PgM__Zdn_T__1, }, }, - // ZSQRDCMLAH + // ZSHRNB { - // ZSQRDCMLAH , .H[], .H, .H + // ZSHRNB #, ., . { - goOp: AZSQRDCMLAH, - fixedBits: 0x44a07000, - args: const__Zm_H_imm___Zn_H__Zda_H__1, - }, - // ZSQRDCMLAH , .S[], .S, .S - { - goOp: AZSQRDCMLAH, - fixedBits: 0x44e07000, - args: const__Zm_S_imm___Zn_S__Zda_S__1, - }, - // ZSQRDCMLAH , ., ., . - { - goOp: AZSQRDCMLAH, - fixedBits: 0x44003000, - args: const__Zm_T__Zn_T__Zda_T, + goOp: AZSHRNB, + fixedBits: 0x45201000, + args: cconst__Zn_Tb__Zd_T__1, }, }, - // ZSQRDMLAH + // ZSHRNT { - // ZSQRDMLAH ., ., . - { - goOp: AZSQRDMLAH, - fixedBits: 0x44007000, - args: Zm_T__Zn_T__Zda_T__2, - }, - // ZSQRDMLAH .D[], .D, .D - { - goOp: AZSQRDMLAH, - fixedBits: 0x44e01000, - args: Zm_D_imm___Zn_D__Zda_D__1, - }, - // ZSQRDMLAH .H[], .H, .H - { - goOp: AZSQRDMLAH, - fixedBits: 0x44201000, - args: Zm_H_imm___Zn_H__Zda_H__1, - }, - // ZSQRDMLAH .S[], .S, .S + // ZSHRNT #, ., . { - goOp: AZSQRDMLAH, - fixedBits: 0x44a01000, - args: Zm_S_imm___Zn_S__Zda_S__1, + goOp: AZSHRNT, + fixedBits: 0x45201400, + args: cconst__Zn_Tb__Zd_T__1, }, }, - // ZSQRDMLSH + // ZSHSUB { - // ZSQRDMLSH ., ., . - { - goOp: AZSQRDMLSH, - fixedBits: 0x44007400, - args: Zm_T__Zn_T__Zda_T__2, - }, - // ZSQRDMLSH .D[], .D, .D + // ZSHSUB ., ., /M, . { - goOp: AZSQRDMLSH, - fixedBits: 0x44e01400, - args: Zm_D_imm___Zn_D__Zda_D__1, + goOp: AZSHSUB, + fixedBits: 0x44128000, + args: Zm_T__Zdn_T__PgM__Zdn_T__1, }, - // ZSQRDMLSH .H[], .H, .H + }, + // ZSHSUBR + { + // ZSHSUBR ., ., /M, . { - goOp: AZSQRDMLSH, - fixedBits: 0x44201400, - args: Zm_H_imm___Zn_H__Zda_H__1, + goOp: AZSHSUBR, + fixedBits: 0x44168000, + args: Zm_T__Zdn_T__PgM__Zdn_T__1, }, - // ZSQRDMLSH .S[], .S, .S + }, + // ZSLI + { + // ZSLI #, ., . { - goOp: AZSQRDMLSH, - fixedBits: 0x44a01400, - args: Zm_S_imm___Zn_S__Zda_S__1, + goOp: AZSLI, + fixedBits: 0x4500f400, + args: cconst__Zn_T__Zd_T__2, }, }, - // ZSQRDMULH + // ZSM4E { - // ZSQRDMULH ., ., . + // ZSM4E .S, .S, .S { - goOp: AZSQRDMULH, - fixedBits: 0x4207400, - args: Zm_T__Zn_T__Zd_T__1, + goOp: AZSM4E, + fixedBits: 0x4523e000, + args: Zm_S__Zdn_S__Zdn_S, }, - // ZSQRDMULH .D[], .D, .D + }, + // ZSM4EKEY + { + // ZSM4EKEY .S, .S, .S { - goOp: AZSQRDMULH, - fixedBits: 0x44e0f400, - args: Zm_D_imm___Zn_D__Zd_D__1, + goOp: AZSM4EKEY, + fixedBits: 0x4520f000, + args: Zm_S__Zn_S__Zd_S, }, - // ZSQRDMULH .H[], .H, .H + }, + // ZSMAX + { + // ZSMAX ., ., /M, . { - goOp: AZSQRDMULH, - fixedBits: 0x4420f400, - args: Zm_H_imm___Zn_H__Zd_H__1, + goOp: AZSMAX, + fixedBits: 0x4080000, + args: Zm_T__Zdn_T__PgM__Zdn_T__1, }, - // ZSQRDMULH .S[], .S, .S + // ZSMAX #, ., . { - goOp: AZSQRDMULH, - fixedBits: 0x44a0f400, - args: Zm_S_imm___Zn_S__Zd_S__1, + goOp: AZSMAX, + fixedBits: 0x2528c000, + args: cimm__Zdn_T__Zdn_T__1, }, }, - // ZSQRSHL + // ZSMAXP { - // ZSQRSHL ., ., /M, . + // ZSMAXP ., ., /M, . { - goOp: AZSQRSHL, - fixedBits: 0x440a8000, + goOp: AZSMAXP, + fixedBits: 0x4414a000, args: Zm_T__Zdn_T__PgM__Zdn_T__1, }, }, - // ZSQRSHLR + // ZSMAXQV { - // ZSQRSHLR ., ., /M, . + // ZSMAXQV ., , . { - goOp: AZSQRSHLR, - fixedBits: 0x440e8000, - args: Zm_T__Zdn_T__PgM__Zdn_T__1, + goOp: AZSMAXQV, + fixedBits: 0x40c2000, + args: Zn_Tb__Pg__Vd_T__1, }, }, - // ZSQRSHRNB + // ZSMAXVB { - // ZSQRSHRNB #, ., . + // ZSMAXVB ., , { - goOp: AZSQRSHRNB, - fixedBits: 0x45202800, - args: cconst__Zn_Tb__Zd_T__1, + goOp: AZSMAXVB, + fixedBits: 0x4082000, + args: Zn_T__Pg__Vd__1, }, }, - // ZSQRSHRNT + // ZSMAXVD { - // ZSQRSHRNT #, ., . + // ZSMAXVD ., , { - goOp: AZSQRSHRNT, - fixedBits: 0x45202c00, - args: cconst__Zn_Tb__Zd_T__1, + goOp: AZSMAXVD, + fixedBits: 0x4c82000, + args: Zn_T__Pg__Vd__1, }, }, - // ZSQRSHRUNB + // ZSMAXVH { - // ZSQRSHRUNB #, ., . + // ZSMAXVH ., , { - goOp: AZSQRSHRUNB, - fixedBits: 0x45200800, - args: cconst__Zn_Tb__Zd_T__1, + goOp: AZSMAXVH, + fixedBits: 0x4482000, + args: Zn_T__Pg__Vd__1, }, }, - // ZSQRSHRUNT + // ZSMAXVS { - // ZSQRSHRUNT #, ., . + // ZSMAXVS ., , { - goOp: AZSQRSHRUNT, - fixedBits: 0x45200c00, - args: cconst__Zn_Tb__Zd_T__1, + goOp: AZSMAXVS, + fixedBits: 0x4882000, + args: Zn_T__Pg__Vd__1, }, }, - // ZSQSHL + // ZSMIN { - // ZSQSHL ., ., /M, . + // ZSMIN ., ., /M, . { - goOp: AZSQSHL, - fixedBits: 0x44088000, + goOp: AZSMIN, + fixedBits: 0x40a0000, args: Zm_T__Zdn_T__PgM__Zdn_T__1, }, - // ZSQSHL #, ., /M, . + // ZSMIN #, ., . { - goOp: AZSQSHL, - fixedBits: 0x4068000, - args: cconst__Zdn_T__PgM__Zdn_T__2, + goOp: AZSMIN, + fixedBits: 0x252ac000, + args: cimm__Zdn_T__Zdn_T__1, }, }, - // ZSQSHLR + // ZSMINP { - // ZSQSHLR ., ., /M, . + // ZSMINP ., ., /M, . { - goOp: AZSQSHLR, - fixedBits: 0x440c8000, + goOp: AZSMINP, + fixedBits: 0x4416a000, args: Zm_T__Zdn_T__PgM__Zdn_T__1, }, }, - // ZSQSHLU + // ZSMINQV { - // ZSQSHLU #, ., /M, . + // ZSMINQV ., , . { - goOp: AZSQSHLU, - fixedBits: 0x40f8000, - args: cconst__Zdn_T__PgM__Zdn_T__2, + goOp: AZSMINQV, + fixedBits: 0x40e2000, + args: Zn_Tb__Pg__Vd_T__1, }, }, - // ZSQSHRNB + // ZSMINVB { - // ZSQSHRNB #, ., . + // ZSMINVB ., , { - goOp: AZSQSHRNB, - fixedBits: 0x45202000, - args: cconst__Zn_Tb__Zd_T__1, + goOp: AZSMINVB, + fixedBits: 0x40a2000, + args: Zn_T__Pg__Vd__1, }, }, - // ZSQSHRNT + // ZSMINVD { - // ZSQSHRNT #, ., . + // ZSMINVD ., , { - goOp: AZSQSHRNT, - fixedBits: 0x45202400, - args: cconst__Zn_Tb__Zd_T__1, + goOp: AZSMINVD, + fixedBits: 0x4ca2000, + args: Zn_T__Pg__Vd__1, }, }, - // ZSQSHRUNB + // ZSMINVH { - // ZSQSHRUNB #, ., . + // ZSMINVH ., , { - goOp: AZSQSHRUNB, - fixedBits: 0x45200000, - args: cconst__Zn_Tb__Zd_T__1, + goOp: AZSMINVH, + fixedBits: 0x44a2000, + args: Zn_T__Pg__Vd__1, }, }, - // ZSQSHRUNT + // ZSMINVS { - // ZSQSHRUNT #, ., . + // ZSMINVS ., , { - goOp: AZSQSHRUNT, - fixedBits: 0x45200400, - args: cconst__Zn_Tb__Zd_T__1, + goOp: AZSMINVS, + fixedBits: 0x48a2000, + args: Zn_T__Pg__Vd__1, }, }, - // ZSQSUB + // ZSMLALB { - // ZSQSUB ., ., /M, . + // ZSMLALB ., ., . { - goOp: AZSQSUB, - fixedBits: 0x441a8000, - args: Zm_T__Zdn_T__PgM__Zdn_T__1, + goOp: AZSMLALB, + fixedBits: 0x44004000, + args: Zm_Tb__Zn_Tb__Zda_T__1, }, - // ZSQSUB ., ., . + // ZSMLALB .H[], .H, .S { - goOp: AZSQSUB, - fixedBits: 0x4201800, - args: Zm_T__Zn_T__Zd_T__1, + goOp: AZSMLALB, + fixedBits: 0x44a08000, + args: Zm_H_imm___Zn_H__Zda_S__1, }, - // ZSQSUB #{, }, ., . + // ZSMLALB .S[], .S, .D { - goOp: AZSQSUB, - fixedBits: 0x2526c000, - args: cimm__shift__Zdn_T__Zdn_T, + goOp: AZSMLALB, + fixedBits: 0x44e08000, + args: Zm_S_imm___Zn_S__Zda_D, }, }, - // ZSQSUBR + // ZSMLALT { - // ZSQSUBR ., ., /M, . + // ZSMLALT ., ., . { - goOp: AZSQSUBR, - fixedBits: 0x441e8000, - args: Zm_T__Zdn_T__PgM__Zdn_T__1, + goOp: AZSMLALT, + fixedBits: 0x44004400, + args: Zm_Tb__Zn_Tb__Zda_T__1, }, - }, - // ZSQXTNB - { - // ZSQXTNB ., . + // ZSMLALT .H[], .H, .S { - goOp: AZSQXTNB, - fixedBits: 0x45204000, - args: Zn_Tb__Zd_T__2, + goOp: AZSMLALT, + fixedBits: 0x44a08400, + args: Zm_H_imm___Zn_H__Zda_S__1, }, - }, - // ZSQXTNT - { - // ZSQXTNT ., . + // ZSMLALT .S[], .S, .D { - goOp: AZSQXTNT, - fixedBits: 0x45204400, - args: Zn_Tb__Zd_T__2, + goOp: AZSMLALT, + fixedBits: 0x44e08400, + args: Zm_S_imm___Zn_S__Zda_D, }, }, - // ZSQXTUNB + // ZSMLSLB { - // ZSQXTUNB ., . + // ZSMLSLB ., ., . { - goOp: AZSQXTUNB, - fixedBits: 0x45205000, - args: Zn_Tb__Zd_T__2, + goOp: AZSMLSLB, + fixedBits: 0x44005000, + args: Zm_Tb__Zn_Tb__Zda_T__1, }, - }, - // ZSQXTUNT - { - // ZSQXTUNT ., . + // ZSMLSLB .H[], .H, .S { - goOp: AZSQXTUNT, - fixedBits: 0x45205400, - args: Zn_Tb__Zd_T__2, + goOp: AZSMLSLB, + fixedBits: 0x44a0a000, + args: Zm_H_imm___Zn_H__Zda_S__1, }, - }, - // ZSRHADD - { - // ZSRHADD ., ., /M, . + // ZSMLSLB .S[], .S, .D { - goOp: AZSRHADD, - fixedBits: 0x44148000, - args: Zm_T__Zdn_T__PgM__Zdn_T__1, + goOp: AZSMLSLB, + fixedBits: 0x44e0a000, + args: Zm_S_imm___Zn_S__Zda_D, }, }, - // ZSRI + // ZSMLSLT { - // ZSRI #, ., . + // ZSMLSLT ., ., . { - goOp: AZSRI, - fixedBits: 0x4500f000, - args: cconst__Zn_T__Zd_T__1, + goOp: AZSMLSLT, + fixedBits: 0x44005400, + args: Zm_Tb__Zn_Tb__Zda_T__1, }, - }, - // ZSRSHL - { - // ZSRSHL ., ., /M, . + // ZSMLSLT .H[], .H, .S { - goOp: AZSRSHL, - fixedBits: 0x44028000, - args: Zm_T__Zdn_T__PgM__Zdn_T__1, + goOp: AZSMLSLT, + fixedBits: 0x44a0a400, + args: Zm_H_imm___Zn_H__Zda_S__1, }, - }, - // ZSRSHLR - { - // ZSRSHLR ., ., /M, . + // ZSMLSLT .S[], .S, .D { - goOp: AZSRSHLR, - fixedBits: 0x44068000, - args: Zm_T__Zdn_T__PgM__Zdn_T__1, + goOp: AZSMLSLT, + fixedBits: 0x44e0a400, + args: Zm_S_imm___Zn_S__Zda_D, }, }, - // ZSRSHR + // ZSMMLA { - // ZSRSHR #, ., /M, . + // ZSMMLA .B, .B, .S { - goOp: AZSRSHR, - fixedBits: 0x40c8000, - args: cconst__Zdn_T__PgM__Zdn_T__1, + goOp: AZSMMLA, + fixedBits: 0x45009800, + args: Zm_B__Zn_B__Zda_S, }, }, - // ZSRSRA + // ZSMULH { - // ZSRSRA #, ., . + // ZSMULH ., ., /M, . { - goOp: AZSRSRA, - fixedBits: 0x4500e800, - args: cconst__Zn_T__Zda_T, + goOp: AZSMULH, + fixedBits: 0x4120000, + args: Zm_T__Zdn_T__PgM__Zdn_T__1, }, - }, - // ZSSHLLB - { - // ZSSHLLB #, ., . + // ZSMULH ., ., . { - goOp: AZSSHLLB, - fixedBits: 0x4500a000, - args: cconst__Zn_Tb__Zd_T__2, + goOp: AZSMULH, + fixedBits: 0x4206800, + args: Zm_T__Zn_T__Zd_T__1, }, }, - // ZSSHLLT + // ZSMULLB { - // ZSSHLLT #, ., . + // ZSMULLB ., ., . { - goOp: AZSSHLLT, - fixedBits: 0x4500a400, - args: cconst__Zn_Tb__Zd_T__2, + goOp: AZSMULLB, + fixedBits: 0x45007000, + args: Zm_Tb__Zn_Tb__Zd_T__1, }, - }, - // ZSSRA - { - // ZSSRA #, ., . + // ZSMULLB .H[], .H, .S { - goOp: AZSSRA, - fixedBits: 0x4500e000, - args: cconst__Zn_T__Zda_T, + goOp: AZSMULLB, + fixedBits: 0x44a0c000, + args: Zm_H_imm___Zn_H__Zd_S, }, - }, - // ZSSUBLB - { - // ZSSUBLB ., ., . + // ZSMULLB .S[], .S, .D { - goOp: AZSSUBLB, - fixedBits: 0x45001000, - args: Zm_Tb__Zn_Tb__Zd_T__1, + goOp: AZSMULLB, + fixedBits: 0x44e0c000, + args: Zm_S_imm___Zn_S__Zd_D, }, }, - // ZSSUBLBT + // ZSMULLT { - // ZSSUBLBT ., ., . + // ZSMULLT ., ., . { - goOp: AZSSUBLBT, - fixedBits: 0x45008800, + goOp: AZSMULLT, + fixedBits: 0x45007400, args: Zm_Tb__Zn_Tb__Zd_T__1, }, - }, - // ZSSUBLT - { - // ZSSUBLT ., ., . + // ZSMULLT .H[], .H, .S { - goOp: AZSSUBLT, - fixedBits: 0x45001400, - args: Zm_Tb__Zn_Tb__Zd_T__1, + goOp: AZSMULLT, + fixedBits: 0x44a0c400, + args: Zm_H_imm___Zn_H__Zd_S, }, - }, - // ZSSUBLTB - { - // ZSSUBLTB ., ., . + // ZSMULLT .S[], .S, .D { - goOp: AZSSUBLTB, - fixedBits: 0x45008c00, - args: Zm_Tb__Zn_Tb__Zd_T__1, + goOp: AZSMULLT, + fixedBits: 0x44e0c400, + args: Zm_S_imm___Zn_S__Zd_D, }, }, - // ZSSUBWB + // ZSPLICE { - // ZSSUBWB ., ., . + // ZSPLICE ., ., , . { - goOp: AZSSUBWB, - fixedBits: 0x45005000, - args: Zm_Tb__Zn_T__Zd_T, + goOp: AZSPLICE, + fixedBits: 0x52c8000, + args: Zm_T__Zdn_T__Pv__Zdn_T, + }, + // ZSPLICE { ., . }, , . + { + goOp: AZSPLICE, + fixedBits: 0x52d8000, + args: Zn1_T__Zn2_T___Pv__Zd_T, }, }, - // ZSSUBWT + // ZSQABS { - // ZSSUBWT ., ., . + // ZSQABS ., /M, . { - goOp: AZSSUBWT, - fixedBits: 0x45005400, - args: Zm_Tb__Zn_T__Zd_T, + goOp: AZSQABS, + fixedBits: 0x4408a000, + args: Zn_T__PgM__Zd_T__2, + }, + // ZSQABS ., /Z, . + { + goOp: AZSQABS, + fixedBits: 0x440aa000, + args: Zn_T__PgZ__Zd_T__2, }, }, - // ZSUB + // ZSQADD { - // ZSUB ., ., /M, . + // ZSQADD ., ., /M, . { - goOp: AZSUB, - fixedBits: 0x4010000, + goOp: AZSQADD, + fixedBits: 0x44188000, args: Zm_T__Zdn_T__PgM__Zdn_T__1, }, - // ZSUB ., ., . + // ZSQADD ., ., . { - goOp: AZSUB, - fixedBits: 0x4200400, + goOp: AZSQADD, + fixedBits: 0x4201000, args: Zm_T__Zn_T__Zd_T__1, }, - // ZSUB #{, }, ., . + // ZSQADD #{, }, ., . { - goOp: AZSUB, - fixedBits: 0x2521c000, + goOp: AZSQADD, + fixedBits: 0x2524c000, args: cimm__shift__Zdn_T__Zdn_T, }, }, - // ZSUBHNB + // ZSQCADD { - // ZSUBHNB ., ., . + // ZSQCADD , ., ., . { - goOp: AZSUBHNB, - fixedBits: 0x45207000, - args: Zm_Tb__Zn_Tb__Zd_T__2, + goOp: AZSQCADD, + fixedBits: 0x4501d800, + args: const__Zm_T__Zdn_T__Zdn_T, }, }, - // ZSUBHNT + // ZSQDECP { - // ZSUBHNT ., ., . + // ZSQDECP ., . { - goOp: AZSUBHNT, - fixedBits: 0x45207400, - args: Zm_Tb__Zn_Tb__Zd_T__2, + goOp: AZSQDECP, + fixedBits: 0x252a8000, + args: Pm_T__Zdn_T, }, }, - // ZSUBP + // ZSQDMLALB { - // ZSUBP ., ., /M, . + // ZSQDMLALB ., ., . { - goOp: AZSUBP, - fixedBits: 0x4410a000, - args: Zm_T__Zdn_T__PgM__Zdn_T__1, + goOp: AZSQDMLALB, + fixedBits: 0x44006000, + args: Zm_Tb__Zn_Tb__Zda_T__1, }, - }, - // ZSUBPT - { - // ZSUBPT .D, .D, /M, .D + // ZSQDMLALB .H[], .H, .S { - goOp: AZSUBPT, - fixedBits: 0x4c50000, - args: Zm_D__Zdn_D__PgM__Zdn_D, + goOp: AZSQDMLALB, + fixedBits: 0x44a02000, + args: Zm_H_imm___Zn_H__Zda_S__1, }, - // ZSUBPT .D, .D, .D + // ZSQDMLALB .S[], .S, .D { - goOp: AZSUBPT, - fixedBits: 0x4e00c00, - args: Zm_D__Zn_D__Zd_D, + goOp: AZSQDMLALB, + fixedBits: 0x44e02000, + args: Zm_S_imm___Zn_S__Zda_D, }, }, - // ZSUBR + // ZSQDMLALBT { - // ZSUBR ., ., /M, . - { - goOp: AZSUBR, - fixedBits: 0x4030000, - args: Zm_T__Zdn_T__PgM__Zdn_T__1, - }, - // ZSUBR #{, }, ., . + // ZSQDMLALBT ., ., . { - goOp: AZSUBR, - fixedBits: 0x2523c000, - args: cimm__shift__Zdn_T__Zdn_T, + goOp: AZSQDMLALBT, + fixedBits: 0x44000800, + args: Zm_Tb__Zn_Tb__Zda_T__1, }, }, - // ZSUDOT + // ZSQDMLALT { - // ZSUDOT .B[], .B, .S + // ZSQDMLALT ., ., . { - goOp: AZSUDOT, - fixedBits: 0x44a01c00, - args: Zm_B_imm___Zn_B__Zda_S__2, + goOp: AZSQDMLALT, + fixedBits: 0x44006400, + args: Zm_Tb__Zn_Tb__Zda_T__1, }, - }, - // ZSUNPKHI - { - // ZSUNPKHI ., . + // ZSQDMLALT .H[], .H, .S { - goOp: AZSUNPKHI, - fixedBits: 0x5313800, - args: Zn_Tb__Zd_T__1, + goOp: AZSQDMLALT, + fixedBits: 0x44a02400, + args: Zm_H_imm___Zn_H__Zda_S__1, }, - }, - // ZSUNPKLO - { - // ZSUNPKLO ., . + // ZSQDMLALT .S[], .S, .D { - goOp: AZSUNPKLO, - fixedBits: 0x5303800, - args: Zn_Tb__Zd_T__1, + goOp: AZSQDMLALT, + fixedBits: 0x44e02400, + args: Zm_S_imm___Zn_S__Zda_D, }, }, - // ZSUQADD + // ZSQDMLSLB { - // ZSUQADD ., ., /M, . + // ZSQDMLSLB ., ., . { - goOp: AZSUQADD, - fixedBits: 0x441c8000, - args: Zm_T__Zdn_T__PgM__Zdn_T__1, + goOp: AZSQDMLSLB, + fixedBits: 0x44006800, + args: Zm_Tb__Zn_Tb__Zda_T__1, }, - }, - // ZSXTB - { - // ZSXTB ., /M, . + // ZSQDMLSLB .H[], .H, .S { - goOp: AZSXTB, - fixedBits: 0x410a000, - args: Zn_T__PgM__Zd_T__4, + goOp: AZSQDMLSLB, + fixedBits: 0x44a03000, + args: Zm_H_imm___Zn_H__Zda_S__1, }, - // ZSXTB ., /Z, . + // ZSQDMLSLB .S[], .S, .D { - goOp: AZSXTB, - fixedBits: 0x400a000, - args: Zn_T__PgZ__Zd_T__4, + goOp: AZSQDMLSLB, + fixedBits: 0x44e03000, + args: Zm_S_imm___Zn_S__Zda_D, }, }, - // ZSXTH + // ZSQDMLSLBT { - // ZSXTH ., /M, . - { - goOp: AZSXTH, - fixedBits: 0x492a000, - args: Zn_T__PgM__Zd_T__5, - }, - // ZSXTH ., /Z, . + // ZSQDMLSLBT ., ., . { - goOp: AZSXTH, - fixedBits: 0x482a000, - args: Zn_T__PgZ__Zd_T__5, + goOp: AZSQDMLSLBT, + fixedBits: 0x44000c00, + args: Zm_Tb__Zn_Tb__Zda_T__1, }, }, - // ZSXTW + // ZSQDMLSLT { - // ZSXTW .D, /M, .D + // ZSQDMLSLT ., ., . { - goOp: AZSXTW, - fixedBits: 0x4d4a000, - args: Zn_D__PgM__Zd_D, + goOp: AZSQDMLSLT, + fixedBits: 0x44006c00, + args: Zm_Tb__Zn_Tb__Zda_T__1, }, - // ZSXTW .D, /Z, .D + // ZSQDMLSLT .H[], .H, .S { - goOp: AZSXTW, - fixedBits: 0x4c4a000, - args: Zn_D__PgZ__Zd_D, + goOp: AZSQDMLSLT, + fixedBits: 0x44a03400, + args: Zm_H_imm___Zn_H__Zda_S__1, }, - }, - // ZTBLQ - { - // ZTBLQ ., { . }, . + // ZSQDMLSLT .S[], .S, .D { - goOp: AZTBLQ, - fixedBits: 0x4400f800, - args: Zm_T___Zn_T___Zd_T, + goOp: AZSQDMLSLT, + fixedBits: 0x44e03400, + args: Zm_S_imm___Zn_S__Zda_D, }, }, - // ZTBX + // ZSQDMULH { - // ZTBX ., ., . + // ZSQDMULH ., ., . { - goOp: AZTBX, - fixedBits: 0x5202c00, + goOp: AZSQDMULH, + fixedBits: 0x4207000, args: Zm_T__Zn_T__Zd_T__1, }, - }, - // ZTBXQ - { - // ZTBXQ ., ., . + // ZSQDMULH .D[], .D, .D { - goOp: AZTBXQ, - fixedBits: 0x5203400, - args: Zm_T__Zn_T__Zd_T__1, + goOp: AZSQDMULH, + fixedBits: 0x44e0f000, + args: Zm_D_imm___Zn_D__Zd_D__1, }, - }, - // ZTRN1 - { - // ZTRN1 .Q, .Q, .Q + // ZSQDMULH .H[], .H, .H { - goOp: AZTRN1, - fixedBits: 0x5a01800, - args: Zm_Q__Zn_Q__Zd_Q, + goOp: AZSQDMULH, + fixedBits: 0x4420f000, + args: Zm_H_imm___Zn_H__Zd_H__1, }, - // ZTRN1 ., ., . + // ZSQDMULH .S[], .S, .S { - goOp: AZTRN1, - fixedBits: 0x5207000, - args: Zm_T__Zn_T__Zd_T__1, + goOp: AZSQDMULH, + fixedBits: 0x44a0f000, + args: Zm_S_imm___Zn_S__Zd_S__1, }, }, - // ZTRN2 + // ZSQDMULLB { - // ZTRN2 .Q, .Q, .Q + // ZSQDMULLB ., ., . { - goOp: AZTRN2, - fixedBits: 0x5a01c00, - args: Zm_Q__Zn_Q__Zd_Q, + goOp: AZSQDMULLB, + fixedBits: 0x45006000, + args: Zm_Tb__Zn_Tb__Zd_T__1, }, - // ZTRN2 ., ., . + // ZSQDMULLB .H[], .H, .S { - goOp: AZTRN2, - fixedBits: 0x5207400, - args: Zm_T__Zn_T__Zd_T__1, + goOp: AZSQDMULLB, + fixedBits: 0x44a0e000, + args: Zm_H_imm___Zn_H__Zd_S, }, - }, - // ZUABA - { - // ZUABA ., ., . + // ZSQDMULLB .S[], .S, .D { - goOp: AZUABA, - fixedBits: 0x4500fc00, - args: Zm_T__Zn_T__Zda_T__2, + goOp: AZSQDMULLB, + fixedBits: 0x44e0e000, + args: Zm_S_imm___Zn_S__Zd_D, }, }, - // ZUABAL + // ZSQDMULLT { - // ZUABAL ., ., . + // ZSQDMULLT ., ., . { - goOp: AZUABAL, - fixedBits: 0x4400dc00, - args: Zm_Tb__Zn_Tb__Zda_T__1, - }, - }, - // ZUABALB - { - // ZUABALB ., ., . + goOp: AZSQDMULLT, + fixedBits: 0x45006400, + args: Zm_Tb__Zn_Tb__Zd_T__1, + }, + // ZSQDMULLT .H[], .H, .S { - goOp: AZUABALB, - fixedBits: 0x4500c800, - args: Zm_Tb__Zn_Tb__Zda_T__1, + goOp: AZSQDMULLT, + fixedBits: 0x44a0e400, + args: Zm_H_imm___Zn_H__Zd_S, }, - }, - // ZUABALT - { - // ZUABALT ., ., . + // ZSQDMULLT .S[], .S, .D { - goOp: AZUABALT, - fixedBits: 0x4500cc00, - args: Zm_Tb__Zn_Tb__Zda_T__1, + goOp: AZSQDMULLT, + fixedBits: 0x44e0e400, + args: Zm_S_imm___Zn_S__Zd_D, }, }, - // ZUABD + // ZSQINCP { - // ZUABD ., ., /M, . + // ZSQINCP ., . { - goOp: AZUABD, - fixedBits: 0x40d0000, - args: Zm_T__Zdn_T__PgM__Zdn_T__1, + goOp: AZSQINCP, + fixedBits: 0x25288000, + args: Pm_T__Zdn_T, }, }, - // ZUABDLB + // ZSQNEG { - // ZUABDLB ., ., . + // ZSQNEG ., /M, . { - goOp: AZUABDLB, - fixedBits: 0x45003800, - args: Zm_Tb__Zn_Tb__Zd_T__1, + goOp: AZSQNEG, + fixedBits: 0x4409a000, + args: Zn_T__PgM__Zd_T__2, }, - }, - // ZUABDLT - { - // ZUABDLT ., ., . + // ZSQNEG ., /Z, . { - goOp: AZUABDLT, - fixedBits: 0x45003c00, - args: Zm_Tb__Zn_Tb__Zd_T__1, + goOp: AZSQNEG, + fixedBits: 0x440ba000, + args: Zn_T__PgZ__Zd_T__2, }, }, - // ZUADALP + // ZSQRDCMLAH { - // ZUADALP ., /M, . + // ZSQRDCMLAH , .H[], .H, .H { - goOp: AZUADALP, - fixedBits: 0x4405a000, - args: Zn_Tb__PgM__Zda_T, + goOp: AZSQRDCMLAH, + fixedBits: 0x44a07000, + args: const__Zm_H_imm___Zn_H__Zda_H__1, }, - }, - // ZUADDLB - { - // ZUADDLB ., ., . + // ZSQRDCMLAH , .S[], .S, .S { - goOp: AZUADDLB, - fixedBits: 0x45000800, - args: Zm_Tb__Zn_Tb__Zd_T__1, + goOp: AZSQRDCMLAH, + fixedBits: 0x44e07000, + args: const__Zm_S_imm___Zn_S__Zda_S__1, }, - }, - // ZUADDLT - { - // ZUADDLT ., ., . + // ZSQRDCMLAH , ., ., . { - goOp: AZUADDLT, - fixedBits: 0x45000c00, - args: Zm_Tb__Zn_Tb__Zd_T__1, + goOp: AZSQRDCMLAH, + fixedBits: 0x44003000, + args: const__Zm_T__Zn_T__Zda_T, }, }, - // ZUADDVD + // ZSQRDMLAH { - // ZUADDVD ., ,
+ // ZSQRDMLAH ., ., . { - goOp: AZUADDVD, - fixedBits: 0x4012000, - args: Zn_T__Pg__Dd__2, + goOp: AZSQRDMLAH, + fixedBits: 0x44007000, + args: Zm_T__Zn_T__Zda_T__2, }, - }, - // ZUADDWB - { - // ZUADDWB ., ., . + // ZSQRDMLAH .D[], .D, .D { - goOp: AZUADDWB, - fixedBits: 0x45004800, - args: Zm_Tb__Zn_T__Zd_T, + goOp: AZSQRDMLAH, + fixedBits: 0x44e01000, + args: Zm_D_imm___Zn_D__Zda_D__1, }, - }, - // ZUADDWT - { - // ZUADDWT ., ., . + // ZSQRDMLAH .H[], .H, .H { - goOp: AZUADDWT, - fixedBits: 0x45004c00, - args: Zm_Tb__Zn_T__Zd_T, + goOp: AZSQRDMLAH, + fixedBits: 0x44201000, + args: Zm_H_imm___Zn_H__Zda_H__1, }, - }, - // ZUCLAMP - { - // ZUCLAMP ., ., . + // ZSQRDMLAH .S[], .S, .S { - goOp: AZUCLAMP, - fixedBits: 0x4400c400, - args: Zm_T__Zn_T__Zd_T__1, + goOp: AZSQRDMLAH, + fixedBits: 0x44a01000, + args: Zm_S_imm___Zn_S__Zda_S__1, }, }, - // ZUCVTF + // ZSQRDMLSH { - // ZUCVTF .D, /M, .D + // ZSQRDMLSH ., ., . { - goOp: AZUCVTF, - fixedBits: 0x65d7a000, - args: Zn_D__PgM__Zd_D, + goOp: AZSQRDMLSH, + fixedBits: 0x44007400, + args: Zm_T__Zn_T__Zda_T__2, }, - // ZUCVTF .D, /M, .H + // ZSQRDMLSH .D[], .D, .D { - goOp: AZUCVTF, - fixedBits: 0x6557a000, - args: Zn_D__PgM__Zd_H, + goOp: AZSQRDMLSH, + fixedBits: 0x44e01400, + args: Zm_D_imm___Zn_D__Zda_D__1, }, - // ZUCVTF .D, /M, .S + // ZSQRDMLSH .H[], .H, .H { - goOp: AZUCVTF, - fixedBits: 0x65d5a000, - args: Zn_D__PgM__Zd_S, + goOp: AZSQRDMLSH, + fixedBits: 0x44201400, + args: Zm_H_imm___Zn_H__Zda_H__1, }, - // ZUCVTF .D, /Z, .D + // ZSQRDMLSH .S[], .S, .S { - goOp: AZUCVTF, - fixedBits: 0x64dde000, - args: Zn_D__PgZ__Zd_D, + goOp: AZSQRDMLSH, + fixedBits: 0x44a01400, + args: Zm_S_imm___Zn_S__Zda_S__1, }, - // ZUCVTF .D, /Z, .H + }, + // ZSQRDMULH + { + // ZSQRDMULH ., ., . { - goOp: AZUCVTF, - fixedBits: 0x645de000, - args: Zn_D__PgZ__Zd_H, + goOp: AZSQRDMULH, + fixedBits: 0x4207400, + args: Zm_T__Zn_T__Zd_T__1, }, - // ZUCVTF .D, /Z, .S + // ZSQRDMULH .D[], .D, .D { - goOp: AZUCVTF, - fixedBits: 0x64dda000, - args: Zn_D__PgZ__Zd_S, + goOp: AZSQRDMULH, + fixedBits: 0x44e0f400, + args: Zm_D_imm___Zn_D__Zd_D__1, }, - // ZUCVTF .H, /M, .H + // ZSQRDMULH .H[], .H, .H { - goOp: AZUCVTF, - fixedBits: 0x6553a000, - args: Zn_H__PgM__Zd_H, + goOp: AZSQRDMULH, + fixedBits: 0x4420f400, + args: Zm_H_imm___Zn_H__Zd_H__1, }, - // ZUCVTF .H, /Z, .H + // ZSQRDMULH .S[], .S, .S { - goOp: AZUCVTF, - fixedBits: 0x645ce000, - args: Zn_H__PgZ__Zd_H, + goOp: AZSQRDMULH, + fixedBits: 0x44a0f400, + args: Zm_S_imm___Zn_S__Zd_S__1, }, - // ZUCVTF .S, /M, .D + }, + // ZSQRSHL + { + // ZSQRSHL ., ., /M, . { - goOp: AZUCVTF, - fixedBits: 0x65d1a000, - args: Zn_S__PgM__Zd_D, + goOp: AZSQRSHL, + fixedBits: 0x440a8000, + args: Zm_T__Zdn_T__PgM__Zdn_T__1, }, - // ZUCVTF .S, /M, .H + }, + // ZSQRSHLR + { + // ZSQRSHLR ., ., /M, . { - goOp: AZUCVTF, - fixedBits: 0x6555a000, - args: Zn_S__PgM__Zd_H, + goOp: AZSQRSHLR, + fixedBits: 0x440e8000, + args: Zm_T__Zdn_T__PgM__Zdn_T__1, }, - // ZUCVTF .S, /M, .S + }, + // ZSQRSHRNB + { + // ZSQRSHRNB #, ., . { - goOp: AZUCVTF, - fixedBits: 0x6595a000, - args: Zn_S__PgM__Zd_S, + goOp: AZSQRSHRNB, + fixedBits: 0x45202800, + args: cconst__Zn_Tb__Zd_T__1, }, - // ZUCVTF .S, /Z, .D + }, + // ZSQRSHRNT + { + // ZSQRSHRNT #, ., . { - goOp: AZUCVTF, - fixedBits: 0x64dca000, - args: Zn_S__PgZ__Zd_D, + goOp: AZSQRSHRNT, + fixedBits: 0x45202c00, + args: cconst__Zn_Tb__Zd_T__1, }, - // ZUCVTF .S, /Z, .H + }, + // ZSQRSHRUNB + { + // ZSQRSHRUNB #, ., . { - goOp: AZUCVTF, - fixedBits: 0x645da000, - args: Zn_S__PgZ__Zd_H, + goOp: AZSQRSHRUNB, + fixedBits: 0x45200800, + args: cconst__Zn_Tb__Zd_T__1, }, - // ZUCVTF .S, /Z, .S - { - goOp: AZUCVTF, - fixedBits: 0x649da000, - args: Zn_S__PgZ__Zd_S, - }, - // ZUCVTF ., . + }, + // ZSQRSHRUNT + { + // ZSQRSHRUNT #, ., . { - goOp: AZUCVTF, - fixedBits: 0x650c3400, - args: Zn_Tb__Zd_T__1, + goOp: AZSQRSHRUNT, + fixedBits: 0x45200c00, + args: cconst__Zn_Tb__Zd_T__1, }, }, - // ZUCVTFLT + // ZSQSHL { - // ZUCVTFLT ., . + // ZSQSHL ., ., /M, . { - goOp: AZUCVTFLT, - fixedBits: 0x650c3c00, - args: Zn_Tb__Zd_T__1, + goOp: AZSQSHL, + fixedBits: 0x44088000, + args: Zm_T__Zdn_T__PgM__Zdn_T__1, + }, + // ZSQSHL #, ., /M, . + { + goOp: AZSQSHL, + fixedBits: 0x4068000, + args: cconst__Zdn_T__PgM__Zdn_T__2, }, }, - // ZUDIV + // ZSQSHLR { - // ZUDIV ., ., /M, . + // ZSQSHLR ., ., /M, . { - goOp: AZUDIV, - fixedBits: 0x4950000, - args: Zm_T__Zdn_T__PgM__Zdn_T__4, + goOp: AZSQSHLR, + fixedBits: 0x440c8000, + args: Zm_T__Zdn_T__PgM__Zdn_T__1, }, }, - // ZUDIVR + // ZSQSHLU { - // ZUDIVR ., ., /M, . + // ZSQSHLU #, ., /M, . { - goOp: AZUDIVR, - fixedBits: 0x4970000, - args: Zm_T__Zdn_T__PgM__Zdn_T__4, + goOp: AZSQSHLU, + fixedBits: 0x40f8000, + args: cconst__Zdn_T__PgM__Zdn_T__2, }, }, - // ZUDOT + // ZSQSHRNB { - // ZUDOT .B, .B, .H + // ZSQSHRNB #, ., . { - goOp: AZUDOT, - fixedBits: 0x44400400, - args: Zm_B__Zn_B__Zda_H, + goOp: AZSQSHRNB, + fixedBits: 0x45202000, + args: cconst__Zn_Tb__Zd_T__1, }, - // ZUDOT .H, .H, .S + }, + // ZSQSHRNT + { + // ZSQSHRNT #, ., . { - goOp: AZUDOT, - fixedBits: 0x4400cc00, - args: Zm_H__Zn_H__Zda_S, + goOp: AZSQSHRNT, + fixedBits: 0x45202400, + args: cconst__Zn_Tb__Zd_T__1, }, - // ZUDOT ., ., . + }, + // ZSQSHRUNB + { + // ZSQSHRUNB #, ., . { - goOp: AZUDOT, - fixedBits: 0x44800400, - args: Zm_Tb__Zn_Tb__Zda_T__2, + goOp: AZSQSHRUNB, + fixedBits: 0x45200000, + args: cconst__Zn_Tb__Zd_T__1, }, - // ZUDOT .B[], .B, .H + }, + // ZSQSHRUNT + { + // ZSQSHRUNT #, ., . { - goOp: AZUDOT, - fixedBits: 0x44200400, - args: Zm_B_imm___Zn_B__Zda_H__2, + goOp: AZSQSHRUNT, + fixedBits: 0x45200400, + args: cconst__Zn_Tb__Zd_T__1, }, - // ZUDOT .B[], .B, .S + }, + // ZSQSUB + { + // ZSQSUB ., ., /M, . { - goOp: AZUDOT, - fixedBits: 0x44a00400, - args: Zm_B_imm___Zn_B__Zda_S__3, + goOp: AZSQSUB, + fixedBits: 0x441a8000, + args: Zm_T__Zdn_T__PgM__Zdn_T__1, }, - // ZUDOT .H[], .H, .D + // ZSQSUB ., ., . { - goOp: AZUDOT, - fixedBits: 0x44e00400, - args: Zm_H_imm___Zn_H__Zda_D, + goOp: AZSQSUB, + fixedBits: 0x4201800, + args: Zm_T__Zn_T__Zd_T__1, }, - // ZUDOT .H[], .H, .S + // ZSQSUB #{, }, ., . { - goOp: AZUDOT, - fixedBits: 0x4480cc00, - args: Zm_H_imm___Zn_H__Zda_S__4, + goOp: AZSQSUB, + fixedBits: 0x2526c000, + args: cimm__shift__Zdn_T__Zdn_T, }, }, - // ZUHADD + // ZSQSUBR { - // ZUHADD ., ., /M, . + // ZSQSUBR ., ., /M, . { - goOp: AZUHADD, - fixedBits: 0x44118000, + goOp: AZSQSUBR, + fixedBits: 0x441e8000, args: Zm_T__Zdn_T__PgM__Zdn_T__1, }, }, - // ZUHSUB + // ZSQXTNB { - // ZUHSUB ., ., /M, . + // ZSQXTNB ., . { - goOp: AZUHSUB, - fixedBits: 0x44138000, - args: Zm_T__Zdn_T__PgM__Zdn_T__1, + goOp: AZSQXTNB, + fixedBits: 0x45204000, + args: Zn_Tb__Zd_T__2, }, }, - // ZUHSUBR + // ZSQXTNT { - // ZUHSUBR ., ., /M, . + // ZSQXTNT ., . { - goOp: AZUHSUBR, - fixedBits: 0x44178000, - args: Zm_T__Zdn_T__PgM__Zdn_T__1, + goOp: AZSQXTNT, + fixedBits: 0x45204400, + args: Zn_Tb__Zd_T__2, }, }, - // ZUMAX + // ZSQXTUNB { - // ZUMAX ., ., /M, . + // ZSQXTUNB ., . { - goOp: AZUMAX, - fixedBits: 0x4090000, - args: Zm_T__Zdn_T__PgM__Zdn_T__1, + goOp: AZSQXTUNB, + fixedBits: 0x45205000, + args: Zn_Tb__Zd_T__2, }, - // ZUMAX #, ., . + }, + // ZSQXTUNT + { + // ZSQXTUNT ., . { - goOp: AZUMAX, - fixedBits: 0x2529c000, - args: cimm__Zdn_T__Zdn_T__2, + goOp: AZSQXTUNT, + fixedBits: 0x45205400, + args: Zn_Tb__Zd_T__2, }, }, - // ZUMAXP + // ZSRHADD { - // ZUMAXP ., ., /M, . + // ZSRHADD ., ., /M, . { - goOp: AZUMAXP, - fixedBits: 0x4415a000, + goOp: AZSRHADD, + fixedBits: 0x44148000, args: Zm_T__Zdn_T__PgM__Zdn_T__1, }, }, - // ZUMAXQV + // ZSRI { - // ZUMAXQV ., , . + // ZSRI #, ., . { - goOp: AZUMAXQV, - fixedBits: 0x40d2000, - args: Zn_Tb__Pg__Vd_T__1, + goOp: AZSRI, + fixedBits: 0x4500f000, + args: cconst__Zn_T__Zd_T__1, }, }, - // ZUMAXVB + // ZSRSHL { - // ZUMAXVB ., , + // ZSRSHL ., ., /M, . { - goOp: AZUMAXVB, - fixedBits: 0x4092000, - args: Zn_T__Pg__Vd__1, + goOp: AZSRSHL, + fixedBits: 0x44028000, + args: Zm_T__Zdn_T__PgM__Zdn_T__1, }, }, - // ZUMAXVD + // ZSRSHLR { - // ZUMAXVD ., , + // ZSRSHLR ., ., /M, . { - goOp: AZUMAXVD, - fixedBits: 0x4c92000, - args: Zn_T__Pg__Vd__1, + goOp: AZSRSHLR, + fixedBits: 0x44068000, + args: Zm_T__Zdn_T__PgM__Zdn_T__1, }, }, - // ZUMAXVH + // ZSRSHR { - // ZUMAXVH ., , + // ZSRSHR #, ., /M, . { - goOp: AZUMAXVH, - fixedBits: 0x4492000, - args: Zn_T__Pg__Vd__1, + goOp: AZSRSHR, + fixedBits: 0x40c8000, + args: cconst__Zdn_T__PgM__Zdn_T__1, }, }, - // ZUMAXVS + // ZSRSRA { - // ZUMAXVS ., , + // ZSRSRA #, ., . { - goOp: AZUMAXVS, - fixedBits: 0x4892000, - args: Zn_T__Pg__Vd__1, + goOp: AZSRSRA, + fixedBits: 0x4500e800, + args: cconst__Zn_T__Zda_T, }, }, - // ZUMIN + // ZSSHLLB { - // ZUMIN ., ., /M, . - { - goOp: AZUMIN, - fixedBits: 0x40b0000, - args: Zm_T__Zdn_T__PgM__Zdn_T__1, - }, - // ZUMIN #, ., . + // ZSSHLLB #, ., . { - goOp: AZUMIN, - fixedBits: 0x252bc000, - args: cimm__Zdn_T__Zdn_T__2, + goOp: AZSSHLLB, + fixedBits: 0x4500a000, + args: cconst__Zn_Tb__Zd_T__2, }, }, - // ZUMINP + // ZSSHLLT { - // ZUMINP ., ., /M, . + // ZSSHLLT #, ., . { - goOp: AZUMINP, - fixedBits: 0x4417a000, - args: Zm_T__Zdn_T__PgM__Zdn_T__1, + goOp: AZSSHLLT, + fixedBits: 0x4500a400, + args: cconst__Zn_Tb__Zd_T__2, }, }, - // ZUMINQV + // ZSSRA { - // ZUMINQV ., , . + // ZSSRA #, ., . { - goOp: AZUMINQV, - fixedBits: 0x40f2000, - args: Zn_Tb__Pg__Vd_T__1, + goOp: AZSSRA, + fixedBits: 0x4500e000, + args: cconst__Zn_T__Zda_T, }, }, - // ZUMINVB + // ZSSUBLB { - // ZUMINVB ., , + // ZSSUBLB ., ., . { - goOp: AZUMINVB, - fixedBits: 0x40b2000, - args: Zn_T__Pg__Vd__1, + goOp: AZSSUBLB, + fixedBits: 0x45001000, + args: Zm_Tb__Zn_Tb__Zd_T__1, }, }, - // ZUMINVD + // ZSSUBLBT { - // ZUMINVD ., , + // ZSSUBLBT ., ., . { - goOp: AZUMINVD, - fixedBits: 0x4cb2000, - args: Zn_T__Pg__Vd__1, + goOp: AZSSUBLBT, + fixedBits: 0x45008800, + args: Zm_Tb__Zn_Tb__Zd_T__1, }, }, - // ZUMINVH + // ZSSUBLT { - // ZUMINVH ., , + // ZSSUBLT ., ., . { - goOp: AZUMINVH, - fixedBits: 0x44b2000, - args: Zn_T__Pg__Vd__1, + goOp: AZSSUBLT, + fixedBits: 0x45001400, + args: Zm_Tb__Zn_Tb__Zd_T__1, }, }, - // ZUMINVS + // ZSSUBLTB { - // ZUMINVS ., , + // ZSSUBLTB ., ., . { - goOp: AZUMINVS, - fixedBits: 0x48b2000, - args: Zn_T__Pg__Vd__1, + goOp: AZSSUBLTB, + fixedBits: 0x45008c00, + args: Zm_Tb__Zn_Tb__Zd_T__1, }, }, - // ZUMLALB + // ZSSUBWB { - // ZUMLALB ., ., . - { - goOp: AZUMLALB, - fixedBits: 0x44004800, - args: Zm_Tb__Zn_Tb__Zda_T__1, - }, - // ZUMLALB .H[], .H, .S + // ZSSUBWB ., ., . { - goOp: AZUMLALB, - fixedBits: 0x44a09000, - args: Zm_H_imm___Zn_H__Zda_S__1, + goOp: AZSSUBWB, + fixedBits: 0x45005000, + args: Zm_Tb__Zn_T__Zd_T, }, - // ZUMLALB .S[], .S, .D + }, + // ZSSUBWT + { + // ZSSUBWT ., ., . { - goOp: AZUMLALB, - fixedBits: 0x44e09000, - args: Zm_S_imm___Zn_S__Zda_D, + goOp: AZSSUBWT, + fixedBits: 0x45005400, + args: Zm_Tb__Zn_T__Zd_T, }, }, - // ZUMLALT + // ZST1B { - // ZUMLALT ., ., . + // ZST1B [, ], , { . } { - goOp: AZUMLALT, - fixedBits: 0x44004c00, - args: Zm_Tb__Zn_Tb__Zda_T__1, + goOp: AZST1B, + fixedBits: 0xe4004000, + args: XnSP__Xm___Pg___Zt_T_, }, - // ZUMLALT .H[], .H, .S + // ZST1B [, .D], , { .D } { - goOp: AZUMLALT, - fixedBits: 0x44a09400, - args: Zm_H_imm___Zn_H__Zda_S__1, + goOp: AZST1B, + fixedBits: 0xe400a000, + args: XnSP__Zm_D___Pg___Zt_D_, }, - // ZUMLALT .S[], .S, .D + // ZST1B [, .D, ], , { .D } { - goOp: AZUMLALT, - fixedBits: 0x44e09400, - args: Zm_S_imm___Zn_S__Zda_D, + goOp: AZST1B, + fixedBits: 0xe4008000, + args: XnSP__Zm_D__mod___Pg___Zt_D_, + }, + // ZST1B [, .S, ], , { .S } + { + goOp: AZST1B, + fixedBits: 0xe4408000, + args: XnSP__Zm_S__mod___Pg___Zt_S_, }, }, - // ZUMLSLB + // ZST1D { - // ZUMLSLB ., ., . + // ZST1D [, .D, LSL #3], , { .D } { - goOp: AZUMLSLB, - fixedBits: 0x44005800, - args: Zm_Tb__Zn_Tb__Zda_T__1, + goOp: AZST1D, + fixedBits: 0xe5a0a000, + args: XnSP__Zm_D__LSL_c3___Pg___Zt_D_, }, - // ZUMLSLB .H[], .H, .S + // ZST1D [, .D], , { .D } { - goOp: AZUMLSLB, - fixedBits: 0x44a0b000, - args: Zm_H_imm___Zn_H__Zda_S__1, + goOp: AZST1D, + fixedBits: 0xe580a000, + args: XnSP__Zm_D___Pg___Zt_D_, }, - // ZUMLSLB .S[], .S, .D + // ZST1D [, .D, ], , { .D } { - goOp: AZUMLSLB, - fixedBits: 0x44e0b000, - args: Zm_S_imm___Zn_S__Zda_D, + goOp: AZST1D, + fixedBits: 0xe5808000, + args: XnSP__Zm_D__mod___Pg___Zt_D_, + }, + // ZST1D [, .D, #3], , { .D } + { + goOp: AZST1D, + fixedBits: 0xe5a08000, + args: XnSP__Zm_D__mod_c3___Pg___Zt_D_, }, }, - // ZUMLSLT + // ZST1H { - // ZUMLSLT ., ., . + // ZST1H [, , LSL #1], , { . } { - goOp: AZUMLSLT, - fixedBits: 0x44005c00, - args: Zm_Tb__Zn_Tb__Zda_T__1, + goOp: AZST1H, + fixedBits: 0xe4804000, + args: XnSP__Xm__LSL_c1___Pg___Zt_T_, }, - // ZUMLSLT .H[], .H, .S + // ZST1H [, .D, LSL #1], , { .D } { - goOp: AZUMLSLT, - fixedBits: 0x44a0b400, - args: Zm_H_imm___Zn_H__Zda_S__1, + goOp: AZST1H, + fixedBits: 0xe4a0a000, + args: XnSP__Zm_D__LSL_c1___Pg___Zt_D_, }, - // ZUMLSLT .S[], .S, .D + // ZST1H [, .D], , { .D } { - goOp: AZUMLSLT, - fixedBits: 0x44e0b400, - args: Zm_S_imm___Zn_S__Zda_D, + goOp: AZST1H, + fixedBits: 0xe480a000, + args: XnSP__Zm_D___Pg___Zt_D_, }, - }, - // ZUMMLA - { - // ZUMMLA .B, .B, .S + // ZST1H [, .D, ], , { .D } { - goOp: AZUMMLA, - fixedBits: 0x45c09800, - args: Zm_B__Zn_B__Zda_S, + goOp: AZST1H, + fixedBits: 0xe4808000, + args: XnSP__Zm_D__mod___Pg___Zt_D_, }, - }, - // ZUMULH - { - // ZUMULH ., ., /M, . + // ZST1H [, .D, #1], , { .D } { - goOp: AZUMULH, - fixedBits: 0x4130000, - args: Zm_T__Zdn_T__PgM__Zdn_T__1, + goOp: AZST1H, + fixedBits: 0xe4a08000, + args: XnSP__Zm_D__mod_c1___Pg___Zt_D_, }, - // ZUMULH ., ., . + // ZST1H [, .S, ], , { .S } { - goOp: AZUMULH, - fixedBits: 0x4206c00, - args: Zm_T__Zn_T__Zd_T__1, + goOp: AZST1H, + fixedBits: 0xe4c08000, + args: XnSP__Zm_S__mod___Pg___Zt_S_, + }, + // ZST1H [, .S, #1], , { .S } + { + goOp: AZST1H, + fixedBits: 0xe4e08000, + args: XnSP__Zm_S__mod_c1___Pg___Zt_S_, }, }, - // ZUMULLB + // ZST1Q { - // ZUMULLB ., ., . + // ZST1Q [.D{, }], , { .Q } { - goOp: AZUMULLB, - fixedBits: 0x45007800, - args: Zm_Tb__Zn_Tb__Zd_T__1, + goOp: AZST1Q, + fixedBits: 0xe4202000, + args: Zn_D__Xm___Pg___Zt_Q_, }, - // ZUMULLB .H[], .H, .S + }, + // ZST1W + { + // ZST1W [, .D, LSL #2], , { .D } { - goOp: AZUMULLB, - fixedBits: 0x44a0d000, - args: Zm_H_imm___Zn_H__Zd_S, + goOp: AZST1W, + fixedBits: 0xe520a000, + args: XnSP__Zm_D__LSL_c2___Pg___Zt_D_, }, - // ZUMULLB .S[], .S, .D + // ZST1W [, .D], , { .D } { - goOp: AZUMULLB, - fixedBits: 0x44e0d000, - args: Zm_S_imm___Zn_S__Zd_D, + goOp: AZST1W, + fixedBits: 0xe500a000, + args: XnSP__Zm_D___Pg___Zt_D_, }, - }, - // ZUMULLT - { - // ZUMULLT ., ., . + // ZST1W [, .D, ], , { .D } { - goOp: AZUMULLT, - fixedBits: 0x45007c00, - args: Zm_Tb__Zn_Tb__Zd_T__1, + goOp: AZST1W, + fixedBits: 0xe5008000, + args: XnSP__Zm_D__mod___Pg___Zt_D_, }, - // ZUMULLT .H[], .H, .S + // ZST1W [, .D, #2], , { .D } { - goOp: AZUMULLT, - fixedBits: 0x44a0d400, - args: Zm_H_imm___Zn_H__Zd_S, + goOp: AZST1W, + fixedBits: 0xe5208000, + args: XnSP__Zm_D__mod_c2___Pg___Zt_D_, }, - // ZUMULLT .S[], .S, .D + // ZST1W [, .S, ], , { .S } { - goOp: AZUMULLT, - fixedBits: 0x44e0d400, - args: Zm_S_imm___Zn_S__Zd_D, + goOp: AZST1W, + fixedBits: 0xe5408000, + args: XnSP__Zm_S__mod___Pg___Zt_S_, + }, + // ZST1W [, .S, #2], , { .S } + { + goOp: AZST1W, + fixedBits: 0xe5608000, + args: XnSP__Zm_S__mod_c2___Pg___Zt_S_, }, }, - // ZUQADD + // ZST2B { - // ZUQADD ., ., /M, . + // ZST2B [, ], , { .B, .B } { - goOp: AZUQADD, - fixedBits: 0x44198000, - args: Zm_T__Zdn_T__PgM__Zdn_T__1, + goOp: AZST2B, + fixedBits: 0xe4206000, + args: XnSP__Xm___Pg___Zt1_B__Zt2_B_, }, - // ZUQADD ., ., . + }, + // ZST2D + { + // ZST2D [, , LSL #3], , { .D, .D } { - goOp: AZUQADD, - fixedBits: 0x4201400, - args: Zm_T__Zn_T__Zd_T__1, + goOp: AZST2D, + fixedBits: 0xe5a06000, + args: XnSP__Xm__LSL_c3___Pg___Zt1_D__Zt2_D_, }, - // ZUQADD #{, }, ., . + }, + // ZST2H + { + // ZST2H [, , LSL #1], , { .H, .H } { - goOp: AZUQADD, - fixedBits: 0x2525c000, - args: cimm__shift__Zdn_T__Zdn_T, + goOp: AZST2H, + fixedBits: 0xe4a06000, + args: XnSP__Xm__LSL_c1___Pg___Zt1_H__Zt2_H_, }, }, - // ZUQDECP + // ZST2Q { - // ZUQDECP ., . + // ZST2Q [, , LSL #4], , { .Q, .Q } { - goOp: AZUQDECP, - fixedBits: 0x252b8000, - args: Pm_T__Zdn_T, + goOp: AZST2Q, + fixedBits: 0xe4600000, + args: XnSP__Xm__LSL_c4___Pg___Zt1_Q__Zt2_Q_, }, }, - // ZUQINCP + // ZST2W { - // ZUQINCP ., . + // ZST2W [, , LSL #2], , { .S, .S } { - goOp: AZUQINCP, - fixedBits: 0x25298000, - args: Pm_T__Zdn_T, + goOp: AZST2W, + fixedBits: 0xe5206000, + args: XnSP__Xm__LSL_c2___Pg___Zt1_S__Zt2_S_, }, }, - // ZUQRSHL + // ZST3B { - // ZUQRSHL ., ., /M, . + // ZST3B [, ], , { .B, .B, .B } { - goOp: AZUQRSHL, - fixedBits: 0x440b8000, - args: Zm_T__Zdn_T__PgM__Zdn_T__1, + goOp: AZST3B, + fixedBits: 0xe4406000, + args: XnSP__Xm___Pg___Zt1_B__Zt2_B__Zt3_B_, }, }, - // ZUQRSHLR + // ZST3D { - // ZUQRSHLR ., ., /M, . + // ZST3D [, , LSL #3], , { .D, .D, .D } { - goOp: AZUQRSHLR, - fixedBits: 0x440f8000, - args: Zm_T__Zdn_T__PgM__Zdn_T__1, + goOp: AZST3D, + fixedBits: 0xe5c06000, + args: XnSP__Xm__LSL_c3___Pg___Zt1_D__Zt2_D__Zt3_D_, }, }, - // ZUQRSHRNB + // ZST3H { - // ZUQRSHRNB #, ., . + // ZST3H [, , LSL #1], , { .H, .H, .H } { - goOp: AZUQRSHRNB, - fixedBits: 0x45203800, - args: cconst__Zn_Tb__Zd_T__1, + goOp: AZST3H, + fixedBits: 0xe4c06000, + args: XnSP__Xm__LSL_c1___Pg___Zt1_H__Zt2_H__Zt3_H_, }, }, - // ZUQRSHRNT + // ZST3Q { - // ZUQRSHRNT #, ., . + // ZST3Q [, , LSL #4], , { .Q, .Q, .Q } { - goOp: AZUQRSHRNT, - fixedBits: 0x45203c00, - args: cconst__Zn_Tb__Zd_T__1, + goOp: AZST3Q, + fixedBits: 0xe4a00000, + args: XnSP__Xm__LSL_c4___Pg___Zt1_Q__Zt2_Q__Zt3_Q_, }, }, - // ZUQSHL + // ZST3W { - // ZUQSHL ., ., /M, . + // ZST3W [, , LSL #2], , { .S, .S, .S } { - goOp: AZUQSHL, - fixedBits: 0x44098000, - args: Zm_T__Zdn_T__PgM__Zdn_T__1, + goOp: AZST3W, + fixedBits: 0xe5406000, + args: XnSP__Xm__LSL_c2___Pg___Zt1_S__Zt2_S__Zt3_S_, }, - // ZUQSHL #, ., /M, . + }, + // ZST4B + { + // ZST4B [, ], , { .B, .B, .B, .B } { - goOp: AZUQSHL, - fixedBits: 0x4078000, - args: cconst__Zdn_T__PgM__Zdn_T__2, + goOp: AZST4B, + fixedBits: 0xe4606000, + args: XnSP__Xm___Pg___Zt1_B__Zt2_B__Zt3_B__Zt4_B_, }, }, - // ZUQSHLR + // ZST4D { - // ZUQSHLR ., ., /M, . + // ZST4D [, , LSL #3], , { .D, .D, .D, .D } { - goOp: AZUQSHLR, - fixedBits: 0x440d8000, - args: Zm_T__Zdn_T__PgM__Zdn_T__1, + goOp: AZST4D, + fixedBits: 0xe5e06000, + args: XnSP__Xm__LSL_c3___Pg___Zt1_D__Zt2_D__Zt3_D__Zt4_D_, }, }, - // ZUQSHRNB + // ZST4H { - // ZUQSHRNB #, ., . + // ZST4H [, , LSL #1], , { .H, .H, .H, .H } { - goOp: AZUQSHRNB, - fixedBits: 0x45203000, - args: cconst__Zn_Tb__Zd_T__1, + goOp: AZST4H, + fixedBits: 0xe4e06000, + args: XnSP__Xm__LSL_c1___Pg___Zt1_H__Zt2_H__Zt3_H__Zt4_H_, }, }, - // ZUQSHRNT + // ZST4Q { - // ZUQSHRNT #, ., . + // ZST4Q [, , LSL #4], , { .Q, .Q, .Q, .Q } { - goOp: AZUQSHRNT, - fixedBits: 0x45203400, - args: cconst__Zn_Tb__Zd_T__1, + goOp: AZST4Q, + fixedBits: 0xe4e00000, + args: XnSP__Xm__LSL_c4___Pg___Zt1_Q__Zt2_Q__Zt3_Q__Zt4_Q_, }, }, - // ZUQSUB + // ZST4W { - // ZUQSUB ., ., /M, . + // ZST4W [, , LSL #2], , { .S, .S, .S, .S } { - goOp: AZUQSUB, - fixedBits: 0x441b8000, - args: Zm_T__Zdn_T__PgM__Zdn_T__1, + goOp: AZST4W, + fixedBits: 0xe5606000, + args: XnSP__Xm__LSL_c2___Pg___Zt1_S__Zt2_S__Zt3_S__Zt4_S_, }, - // ZUQSUB ., ., . + }, + // ZSTNT1B + { + // ZSTNT1B [, ], , { .B } { - goOp: AZUQSUB, - fixedBits: 0x4201c00, - args: Zm_T__Zn_T__Zd_T__1, + goOp: AZSTNT1B, + fixedBits: 0xe4006000, + args: XnSP__Xm___Pg___Zt_B_, }, - // ZUQSUB #{, }, ., . - { - goOp: AZUQSUB, - fixedBits: 0x2527c000, - args: cimm__shift__Zdn_T__Zdn_T, - }, - }, - // ZUQSUBR - { - // ZUQSUBR ., ., /M, . - { - goOp: AZUQSUBR, - fixedBits: 0x441f8000, - args: Zm_T__Zdn_T__PgM__Zdn_T__1, - }, - }, - // ZUQXTNB - { - // ZUQXTNB ., . + // ZSTNT1B [.D{, }], , { .D } { - goOp: AZUQXTNB, - fixedBits: 0x45204800, - args: Zn_Tb__Zd_T__2, + goOp: AZSTNT1B, + fixedBits: 0xe4002000, + args: Zn_D__Xm___Pg___Zt_D_, }, - }, - // ZUQXTNT - { - // ZUQXTNT ., . + // ZSTNT1B [.S{, }], , { .S } { - goOp: AZUQXTNT, - fixedBits: 0x45204c00, - args: Zn_Tb__Zd_T__2, + goOp: AZSTNT1B, + fixedBits: 0xe4402000, + args: Zn_S__Xm___Pg___Zt_S_, }, }, - // ZURECPE + // ZSTNT1D { - // ZURECPE .S, /M, .S + // ZSTNT1D [, , LSL #3], , { .D } { - goOp: AZURECPE, - fixedBits: 0x4480a000, - args: Zn_S__PgM__Zd_S, + goOp: AZSTNT1D, + fixedBits: 0xe5806000, + args: XnSP__Xm__LSL_c3___Pg___Zt_D_, }, - // ZURECPE .S, /Z, .S + // ZSTNT1D [.D{, }], , { .D } { - goOp: AZURECPE, - fixedBits: 0x4482a000, - args: Zn_S__PgZ__Zd_S, + goOp: AZSTNT1D, + fixedBits: 0xe5802000, + args: Zn_D__Xm___Pg___Zt_D_, }, }, - // ZURHADD + // ZSTNT1H { - // ZURHADD ., ., /M, . + // ZSTNT1H [, , LSL #1], , { .H } { - goOp: AZURHADD, - fixedBits: 0x44158000, - args: Zm_T__Zdn_T__PgM__Zdn_T__1, + goOp: AZSTNT1H, + fixedBits: 0xe4806000, + args: XnSP__Xm__LSL_c1___Pg___Zt_H_, }, - }, - // ZURSHL - { - // ZURSHL ., ., /M, . + // ZSTNT1H [.D{, }], , { .D } { - goOp: AZURSHL, - fixedBits: 0x44038000, - args: Zm_T__Zdn_T__PgM__Zdn_T__1, + goOp: AZSTNT1H, + fixedBits: 0xe4802000, + args: Zn_D__Xm___Pg___Zt_D_, }, - }, - // ZURSHLR - { - // ZURSHLR ., ., /M, . + // ZSTNT1H [.S{, }], , { .S } { - goOp: AZURSHLR, - fixedBits: 0x44078000, - args: Zm_T__Zdn_T__PgM__Zdn_T__1, + goOp: AZSTNT1H, + fixedBits: 0xe4c02000, + args: Zn_S__Xm___Pg___Zt_S_, }, }, - // ZURSHR + // ZSTNT1W { - // ZURSHR #, ., /M, . + // ZSTNT1W [, , LSL #2], , { .S } { - goOp: AZURSHR, - fixedBits: 0x40d8000, - args: cconst__Zdn_T__PgM__Zdn_T__1, + goOp: AZSTNT1W, + fixedBits: 0xe5006000, + args: XnSP__Xm__LSL_c2___Pg___Zt_S_, }, - }, - // ZURSQRTE - { - // ZURSQRTE .S, /M, .S + // ZSTNT1W [.D{, }], , { .D } { - goOp: AZURSQRTE, - fixedBits: 0x4481a000, - args: Zn_S__PgM__Zd_S, + goOp: AZSTNT1W, + fixedBits: 0xe5002000, + args: Zn_D__Xm___Pg___Zt_D_, }, - // ZURSQRTE .S, /Z, .S + // ZSTNT1W [.S{, }], , { .S } { - goOp: AZURSQRTE, - fixedBits: 0x4483a000, - args: Zn_S__PgZ__Zd_S, + goOp: AZSTNT1W, + fixedBits: 0xe5402000, + args: Zn_S__Xm___Pg___Zt_S_, }, }, - // ZURSRA + // ZSUB { - // ZURSRA #, ., . + // ZSUB ., ., /M, . { - goOp: AZURSRA, - fixedBits: 0x4500ec00, - args: cconst__Zn_T__Zda_T, + goOp: AZSUB, + fixedBits: 0x4010000, + args: Zm_T__Zdn_T__PgM__Zdn_T__1, }, - }, - // ZUSDOT - { - // ZUSDOT .B, .B, .S + // ZSUB ., ., . { - goOp: AZUSDOT, - fixedBits: 0x44807800, - args: Zm_B__Zn_B__Zda_S, + goOp: AZSUB, + fixedBits: 0x4200400, + args: Zm_T__Zn_T__Zd_T__1, }, - // ZUSDOT .B[], .B, .S + // ZSUB #{, }, ., . { - goOp: AZUSDOT, - fixedBits: 0x44a01800, - args: Zm_B_imm___Zn_B__Zda_S__2, + goOp: AZSUB, + fixedBits: 0x2521c000, + args: cimm__shift__Zdn_T__Zdn_T, }, }, - // ZUSHLLB + // ZSUBHNB { - // ZUSHLLB #, ., . + // ZSUBHNB ., ., . { - goOp: AZUSHLLB, - fixedBits: 0x4500a800, - args: cconst__Zn_Tb__Zd_T__2, + goOp: AZSUBHNB, + fixedBits: 0x45207000, + args: Zm_Tb__Zn_Tb__Zd_T__2, }, }, - // ZUSHLLT + // ZSUBHNT { - // ZUSHLLT #, ., . + // ZSUBHNT ., ., . { - goOp: AZUSHLLT, - fixedBits: 0x4500ac00, - args: cconst__Zn_Tb__Zd_T__2, + goOp: AZSUBHNT, + fixedBits: 0x45207400, + args: Zm_Tb__Zn_Tb__Zd_T__2, }, }, - // ZUSMMLA + // ZSUBP { - // ZUSMMLA .B, .B, .S + // ZSUBP ., ., /M, . { - goOp: AZUSMMLA, - fixedBits: 0x45809800, - args: Zm_B__Zn_B__Zda_S, + goOp: AZSUBP, + fixedBits: 0x4410a000, + args: Zm_T__Zdn_T__PgM__Zdn_T__1, }, }, - // ZUSQADD + // ZSUBPT { - // ZUSQADD ., ., /M, . + // ZSUBPT .D, .D, /M, .D { - goOp: AZUSQADD, - fixedBits: 0x441d8000, - args: Zm_T__Zdn_T__PgM__Zdn_T__1, + goOp: AZSUBPT, + fixedBits: 0x4c50000, + args: Zm_D__Zdn_D__PgM__Zdn_D, }, - }, - // ZUSRA - { - // ZUSRA #, ., . + // ZSUBPT .D, .D, .D { - goOp: AZUSRA, - fixedBits: 0x4500e400, - args: cconst__Zn_T__Zda_T, + goOp: AZSUBPT, + fixedBits: 0x4e00c00, + args: Zm_D__Zn_D__Zd_D, }, }, - // ZUSUBLB + // ZSUBR { - // ZUSUBLB ., ., . + // ZSUBR ., ., /M, . { - goOp: AZUSUBLB, - fixedBits: 0x45001800, - args: Zm_Tb__Zn_Tb__Zd_T__1, + goOp: AZSUBR, + fixedBits: 0x4030000, + args: Zm_T__Zdn_T__PgM__Zdn_T__1, }, - }, - // ZUSUBLT - { - // ZUSUBLT ., ., . + // ZSUBR #{, }, ., . { - goOp: AZUSUBLT, - fixedBits: 0x45001c00, - args: Zm_Tb__Zn_Tb__Zd_T__1, + goOp: AZSUBR, + fixedBits: 0x2523c000, + args: cimm__shift__Zdn_T__Zdn_T, }, }, - // ZUSUBWB + // ZSUDOT { - // ZUSUBWB ., ., . + // ZSUDOT .B[], .B, .S { - goOp: AZUSUBWB, - fixedBits: 0x45005800, - args: Zm_Tb__Zn_T__Zd_T, + goOp: AZSUDOT, + fixedBits: 0x44a01c00, + args: Zm_B_imm___Zn_B__Zda_S__2, }, }, - // ZUSUBWT + // ZSUNPKHI { - // ZUSUBWT ., ., . + // ZSUNPKHI ., . { - goOp: AZUSUBWT, - fixedBits: 0x45005c00, - args: Zm_Tb__Zn_T__Zd_T, + goOp: AZSUNPKHI, + fixedBits: 0x5313800, + args: Zn_Tb__Zd_T__1, }, }, - // ZUUNPKHI + // ZSUNPKLO { - // ZUUNPKHI ., . + // ZSUNPKLO ., . { - goOp: AZUUNPKHI, - fixedBits: 0x5333800, + goOp: AZSUNPKLO, + fixedBits: 0x5303800, args: Zn_Tb__Zd_T__1, }, }, - // ZUUNPKLO + // ZSUQADD { - // ZUUNPKLO ., . + // ZSUQADD ., ., /M, . { - goOp: AZUUNPKLO, - fixedBits: 0x5323800, - args: Zn_Tb__Zd_T__1, + goOp: AZSUQADD, + fixedBits: 0x441c8000, + args: Zm_T__Zdn_T__PgM__Zdn_T__1, }, }, - // ZUXTB + // ZSXTB { - // ZUXTB ., /M, . + // ZSXTB ., /M, . { - goOp: AZUXTB, - fixedBits: 0x411a000, + goOp: AZSXTB, + fixedBits: 0x410a000, args: Zn_T__PgM__Zd_T__4, }, - // ZUXTB ., /Z, . + // ZSXTB ., /Z, . { - goOp: AZUXTB, - fixedBits: 0x401a000, + goOp: AZSXTB, + fixedBits: 0x400a000, args: Zn_T__PgZ__Zd_T__4, }, }, - // ZUXTH + // ZSXTH { - // ZUXTH ., /M, . + // ZSXTH ., /M, . { - goOp: AZUXTH, - fixedBits: 0x493a000, + goOp: AZSXTH, + fixedBits: 0x492a000, args: Zn_T__PgM__Zd_T__5, }, - // ZUXTH ., /Z, . + // ZSXTH ., /Z, . { - goOp: AZUXTH, - fixedBits: 0x483a000, + goOp: AZSXTH, + fixedBits: 0x482a000, args: Zn_T__PgZ__Zd_T__5, }, }, - // ZUXTW + // ZSXTW { - // ZUXTW .D, /M, .D + // ZSXTW .D, /M, .D { - goOp: AZUXTW, - fixedBits: 0x4d5a000, + goOp: AZSXTW, + fixedBits: 0x4d4a000, args: Zn_D__PgM__Zd_D, }, - // ZUXTW .D, /Z, .D + // ZSXTW .D, /Z, .D { - goOp: AZUXTW, - fixedBits: 0x4c5a000, + goOp: AZSXTW, + fixedBits: 0x4c4a000, args: Zn_D__PgZ__Zd_D, }, }, - // ZUZP1 + // ZTBLQ { - // ZUZP1 .Q, .Q, .Q + // ZTBLQ ., { . }, . { - goOp: AZUZP1, - fixedBits: 0x5a00800, - args: Zm_Q__Zn_Q__Zd_Q, + goOp: AZTBLQ, + fixedBits: 0x4400f800, + args: Zm_T___Zn_T___Zd_T, }, - // ZUZP1 ., ., . + }, + // ZTBX + { + // ZTBX ., ., . { - goOp: AZUZP1, - fixedBits: 0x5206800, + goOp: AZTBX, + fixedBits: 0x5202c00, args: Zm_T__Zn_T__Zd_T__1, }, }, - // ZUZP2 + // ZTBXQ { - // ZUZP2 .Q, .Q, .Q + // ZTBXQ ., ., . { - goOp: AZUZP2, - fixedBits: 0x5a00c00, + goOp: AZTBXQ, + fixedBits: 0x5203400, + args: Zm_T__Zn_T__Zd_T__1, + }, + }, + // ZTRN1 + { + // ZTRN1 .Q, .Q, .Q + { + goOp: AZTRN1, + fixedBits: 0x5a01800, args: Zm_Q__Zn_Q__Zd_Q, }, - // ZUZP2 ., ., . + // ZTRN1 ., ., . { - goOp: AZUZP2, - fixedBits: 0x5206c00, + goOp: AZTRN1, + fixedBits: 0x5207000, args: Zm_T__Zn_T__Zd_T__1, }, }, - // ZUZPQ1 + // ZTRN2 { - // ZUZPQ1 ., ., . + // ZTRN2 .Q, .Q, .Q { - goOp: AZUZPQ1, - fixedBits: 0x4400e800, + goOp: AZTRN2, + fixedBits: 0x5a01c00, + args: Zm_Q__Zn_Q__Zd_Q, + }, + // ZTRN2 ., ., . + { + goOp: AZTRN2, + fixedBits: 0x5207400, args: Zm_T__Zn_T__Zd_T__1, }, }, - // ZUZPQ2 + // ZUABA { - // ZUZPQ2 ., ., . + // ZUABA ., ., . { - goOp: AZUZPQ2, - fixedBits: 0x4400ec00, - args: Zm_T__Zn_T__Zd_T__1, + goOp: AZUABA, + fixedBits: 0x4500fc00, + args: Zm_T__Zn_T__Zda_T__2, }, }, - // ZXAR + // ZUABAL { - // ZXAR #, ., ., . + // ZUABAL ., ., . { - goOp: AZXAR, - fixedBits: 0x4203400, - args: cconst__Zm_T__Zdn_T__Zdn_T, + goOp: AZUABAL, + fixedBits: 0x4400dc00, + args: Zm_Tb__Zn_Tb__Zda_T__1, }, }, - // ZZIP1 + // ZUABALB { - // ZZIP1 .Q, .Q, .Q + // ZUABALB ., ., . { - goOp: AZZIP1, - fixedBits: 0x5a00000, - args: Zm_Q__Zn_Q__Zd_Q, + goOp: AZUABALB, + fixedBits: 0x4500c800, + args: Zm_Tb__Zn_Tb__Zda_T__1, }, - // ZZIP1 ., ., . + }, + // ZUABALT + { + // ZUABALT ., ., . { - goOp: AZZIP1, - fixedBits: 0x5206000, - args: Zm_T__Zn_T__Zd_T__1, + goOp: AZUABALT, + fixedBits: 0x4500cc00, + args: Zm_Tb__Zn_Tb__Zda_T__1, }, }, - // ZZIP2 + // ZUABD { - // ZZIP2 .Q, .Q, .Q + // ZUABD ., ., /M, . { - goOp: AZZIP2, - fixedBits: 0x5a00400, - args: Zm_Q__Zn_Q__Zd_Q, + goOp: AZUABD, + fixedBits: 0x40d0000, + args: Zm_T__Zdn_T__PgM__Zdn_T__1, }, - // ZZIP2 ., ., . + }, + // ZUABDLB + { + // ZUABDLB ., ., . { - goOp: AZZIP2, - fixedBits: 0x5206400, - args: Zm_T__Zn_T__Zd_T__1, + goOp: AZUABDLB, + fixedBits: 0x45003800, + args: Zm_Tb__Zn_Tb__Zd_T__1, }, }, - // ZZIPQ1 + // ZUABDLT { - // ZZIPQ1 ., ., . + // ZUABDLT ., ., . { - goOp: AZZIPQ1, - fixedBits: 0x4400e000, - args: Zm_T__Zn_T__Zd_T__1, + goOp: AZUABDLT, + fixedBits: 0x45003c00, + args: Zm_Tb__Zn_Tb__Zd_T__1, }, }, - // ZZIPQ2 + // ZUADALP { - // ZZIPQ2 ., ., . + // ZUADALP ., /M, . { - goOp: AZZIPQ2, - fixedBits: 0x4400e400, + goOp: AZUADALP, + fixedBits: 0x4405a000, + args: Zn_Tb__PgM__Zda_T, + }, + }, + // ZUADDLB + { + // ZUADDLB ., ., . + { + goOp: AZUADDLB, + fixedBits: 0x45000800, + args: Zm_Tb__Zn_Tb__Zd_T__1, + }, + }, + // ZUADDLT + { + // ZUADDLT ., ., . + { + goOp: AZUADDLT, + fixedBits: 0x45000c00, + args: Zm_Tb__Zn_Tb__Zd_T__1, + }, + }, + // ZUADDVD + { + // ZUADDVD ., ,
+ { + goOp: AZUADDVD, + fixedBits: 0x4012000, + args: Zn_T__Pg__Dd__2, + }, + }, + // ZUADDWB + { + // ZUADDWB ., ., . + { + goOp: AZUADDWB, + fixedBits: 0x45004800, + args: Zm_Tb__Zn_T__Zd_T, + }, + }, + // ZUADDWT + { + // ZUADDWT ., ., . + { + goOp: AZUADDWT, + fixedBits: 0x45004c00, + args: Zm_Tb__Zn_T__Zd_T, + }, + }, + // ZUCLAMP + { + // ZUCLAMP ., ., . + { + goOp: AZUCLAMP, + fixedBits: 0x4400c400, args: Zm_T__Zn_T__Zd_T__1, }, }, + // ZUCVTF + { + // ZUCVTF .D, /M, .D + { + goOp: AZUCVTF, + fixedBits: 0x65d7a000, + args: Zn_D__PgM__Zd_D, + }, + // ZUCVTF .D, /M, .H + { + goOp: AZUCVTF, + fixedBits: 0x6557a000, + args: Zn_D__PgM__Zd_H, + }, + // ZUCVTF .D, /M, .S + { + goOp: AZUCVTF, + fixedBits: 0x65d5a000, + args: Zn_D__PgM__Zd_S, + }, + // ZUCVTF .D, /Z, .D + { + goOp: AZUCVTF, + fixedBits: 0x64dde000, + args: Zn_D__PgZ__Zd_D, + }, + // ZUCVTF .D, /Z, .H + { + goOp: AZUCVTF, + fixedBits: 0x645de000, + args: Zn_D__PgZ__Zd_H, + }, + // ZUCVTF .D, /Z, .S + { + goOp: AZUCVTF, + fixedBits: 0x64dda000, + args: Zn_D__PgZ__Zd_S, + }, + // ZUCVTF .H, /M, .H + { + goOp: AZUCVTF, + fixedBits: 0x6553a000, + args: Zn_H__PgM__Zd_H, + }, + // ZUCVTF .H, /Z, .H + { + goOp: AZUCVTF, + fixedBits: 0x645ce000, + args: Zn_H__PgZ__Zd_H, + }, + // ZUCVTF .S, /M, .D + { + goOp: AZUCVTF, + fixedBits: 0x65d1a000, + args: Zn_S__PgM__Zd_D, + }, + // ZUCVTF .S, /M, .H + { + goOp: AZUCVTF, + fixedBits: 0x6555a000, + args: Zn_S__PgM__Zd_H, + }, + // ZUCVTF .S, /M, .S + { + goOp: AZUCVTF, + fixedBits: 0x6595a000, + args: Zn_S__PgM__Zd_S, + }, + // ZUCVTF .S, /Z, .D + { + goOp: AZUCVTF, + fixedBits: 0x64dca000, + args: Zn_S__PgZ__Zd_D, + }, + // ZUCVTF .S, /Z, .H + { + goOp: AZUCVTF, + fixedBits: 0x645da000, + args: Zn_S__PgZ__Zd_H, + }, + // ZUCVTF .S, /Z, .S + { + goOp: AZUCVTF, + fixedBits: 0x649da000, + args: Zn_S__PgZ__Zd_S, + }, + // ZUCVTF ., . + { + goOp: AZUCVTF, + fixedBits: 0x650c3400, + args: Zn_Tb__Zd_T__1, + }, + }, + // ZUCVTFLT + { + // ZUCVTFLT ., . + { + goOp: AZUCVTFLT, + fixedBits: 0x650c3c00, + args: Zn_Tb__Zd_T__1, + }, + }, + // ZUDIV + { + // ZUDIV ., ., /M, . + { + goOp: AZUDIV, + fixedBits: 0x4950000, + args: Zm_T__Zdn_T__PgM__Zdn_T__4, + }, + }, + // ZUDIVR + { + // ZUDIVR ., ., /M, . + { + goOp: AZUDIVR, + fixedBits: 0x4970000, + args: Zm_T__Zdn_T__PgM__Zdn_T__4, + }, + }, + // ZUDOT + { + // ZUDOT .B, .B, .H + { + goOp: AZUDOT, + fixedBits: 0x44400400, + args: Zm_B__Zn_B__Zda_H, + }, + // ZUDOT .H, .H, .S + { + goOp: AZUDOT, + fixedBits: 0x4400cc00, + args: Zm_H__Zn_H__Zda_S, + }, + // ZUDOT ., ., . + { + goOp: AZUDOT, + fixedBits: 0x44800400, + args: Zm_Tb__Zn_Tb__Zda_T__2, + }, + // ZUDOT .B[], .B, .H + { + goOp: AZUDOT, + fixedBits: 0x44200400, + args: Zm_B_imm___Zn_B__Zda_H__2, + }, + // ZUDOT .B[], .B, .S + { + goOp: AZUDOT, + fixedBits: 0x44a00400, + args: Zm_B_imm___Zn_B__Zda_S__3, + }, + // ZUDOT .H[], .H, .D + { + goOp: AZUDOT, + fixedBits: 0x44e00400, + args: Zm_H_imm___Zn_H__Zda_D, + }, + // ZUDOT .H[], .H, .S + { + goOp: AZUDOT, + fixedBits: 0x4480cc00, + args: Zm_H_imm___Zn_H__Zda_S__4, + }, + }, + // ZUHADD + { + // ZUHADD ., ., /M, . + { + goOp: AZUHADD, + fixedBits: 0x44118000, + args: Zm_T__Zdn_T__PgM__Zdn_T__1, + }, + }, + // ZUHSUB + { + // ZUHSUB ., ., /M, . + { + goOp: AZUHSUB, + fixedBits: 0x44138000, + args: Zm_T__Zdn_T__PgM__Zdn_T__1, + }, + }, + // ZUHSUBR + { + // ZUHSUBR ., ., /M, . + { + goOp: AZUHSUBR, + fixedBits: 0x44178000, + args: Zm_T__Zdn_T__PgM__Zdn_T__1, + }, + }, + // ZUMAX + { + // ZUMAX ., ., /M, . + { + goOp: AZUMAX, + fixedBits: 0x4090000, + args: Zm_T__Zdn_T__PgM__Zdn_T__1, + }, + // ZUMAX #, ., . + { + goOp: AZUMAX, + fixedBits: 0x2529c000, + args: cimm__Zdn_T__Zdn_T__2, + }, + }, + // ZUMAXP + { + // ZUMAXP ., ., /M, . + { + goOp: AZUMAXP, + fixedBits: 0x4415a000, + args: Zm_T__Zdn_T__PgM__Zdn_T__1, + }, + }, + // ZUMAXQV + { + // ZUMAXQV ., , . + { + goOp: AZUMAXQV, + fixedBits: 0x40d2000, + args: Zn_Tb__Pg__Vd_T__1, + }, + }, + // ZUMAXVB + { + // ZUMAXVB ., , + { + goOp: AZUMAXVB, + fixedBits: 0x4092000, + args: Zn_T__Pg__Vd__1, + }, + }, + // ZUMAXVD + { + // ZUMAXVD ., , + { + goOp: AZUMAXVD, + fixedBits: 0x4c92000, + args: Zn_T__Pg__Vd__1, + }, + }, + // ZUMAXVH + { + // ZUMAXVH ., , + { + goOp: AZUMAXVH, + fixedBits: 0x4492000, + args: Zn_T__Pg__Vd__1, + }, + }, + // ZUMAXVS + { + // ZUMAXVS ., , + { + goOp: AZUMAXVS, + fixedBits: 0x4892000, + args: Zn_T__Pg__Vd__1, + }, + }, + // ZUMIN + { + // ZUMIN ., ., /M, . + { + goOp: AZUMIN, + fixedBits: 0x40b0000, + args: Zm_T__Zdn_T__PgM__Zdn_T__1, + }, + // ZUMIN #, ., . + { + goOp: AZUMIN, + fixedBits: 0x252bc000, + args: cimm__Zdn_T__Zdn_T__2, + }, + }, + // ZUMINP + { + // ZUMINP ., ., /M, . + { + goOp: AZUMINP, + fixedBits: 0x4417a000, + args: Zm_T__Zdn_T__PgM__Zdn_T__1, + }, + }, + // ZUMINQV + { + // ZUMINQV ., , . + { + goOp: AZUMINQV, + fixedBits: 0x40f2000, + args: Zn_Tb__Pg__Vd_T__1, + }, + }, + // ZUMINVB + { + // ZUMINVB ., , + { + goOp: AZUMINVB, + fixedBits: 0x40b2000, + args: Zn_T__Pg__Vd__1, + }, + }, + // ZUMINVD + { + // ZUMINVD ., , + { + goOp: AZUMINVD, + fixedBits: 0x4cb2000, + args: Zn_T__Pg__Vd__1, + }, + }, + // ZUMINVH + { + // ZUMINVH ., , + { + goOp: AZUMINVH, + fixedBits: 0x44b2000, + args: Zn_T__Pg__Vd__1, + }, + }, + // ZUMINVS + { + // ZUMINVS ., , + { + goOp: AZUMINVS, + fixedBits: 0x48b2000, + args: Zn_T__Pg__Vd__1, + }, + }, + // ZUMLALB + { + // ZUMLALB ., ., . + { + goOp: AZUMLALB, + fixedBits: 0x44004800, + args: Zm_Tb__Zn_Tb__Zda_T__1, + }, + // ZUMLALB .H[], .H, .S + { + goOp: AZUMLALB, + fixedBits: 0x44a09000, + args: Zm_H_imm___Zn_H__Zda_S__1, + }, + // ZUMLALB .S[], .S, .D + { + goOp: AZUMLALB, + fixedBits: 0x44e09000, + args: Zm_S_imm___Zn_S__Zda_D, + }, + }, + // ZUMLALT + { + // ZUMLALT ., ., . + { + goOp: AZUMLALT, + fixedBits: 0x44004c00, + args: Zm_Tb__Zn_Tb__Zda_T__1, + }, + // ZUMLALT .H[], .H, .S + { + goOp: AZUMLALT, + fixedBits: 0x44a09400, + args: Zm_H_imm___Zn_H__Zda_S__1, + }, + // ZUMLALT .S[], .S, .D + { + goOp: AZUMLALT, + fixedBits: 0x44e09400, + args: Zm_S_imm___Zn_S__Zda_D, + }, + }, + // ZUMLSLB + { + // ZUMLSLB ., ., . + { + goOp: AZUMLSLB, + fixedBits: 0x44005800, + args: Zm_Tb__Zn_Tb__Zda_T__1, + }, + // ZUMLSLB .H[], .H, .S + { + goOp: AZUMLSLB, + fixedBits: 0x44a0b000, + args: Zm_H_imm___Zn_H__Zda_S__1, + }, + // ZUMLSLB .S[], .S, .D + { + goOp: AZUMLSLB, + fixedBits: 0x44e0b000, + args: Zm_S_imm___Zn_S__Zda_D, + }, + }, + // ZUMLSLT + { + // ZUMLSLT ., ., . + { + goOp: AZUMLSLT, + fixedBits: 0x44005c00, + args: Zm_Tb__Zn_Tb__Zda_T__1, + }, + // ZUMLSLT .H[], .H, .S + { + goOp: AZUMLSLT, + fixedBits: 0x44a0b400, + args: Zm_H_imm___Zn_H__Zda_S__1, + }, + // ZUMLSLT .S[], .S, .D + { + goOp: AZUMLSLT, + fixedBits: 0x44e0b400, + args: Zm_S_imm___Zn_S__Zda_D, + }, + }, + // ZUMMLA + { + // ZUMMLA .B, .B, .S + { + goOp: AZUMMLA, + fixedBits: 0x45c09800, + args: Zm_B__Zn_B__Zda_S, + }, + }, + // ZUMULH + { + // ZUMULH ., ., /M, . + { + goOp: AZUMULH, + fixedBits: 0x4130000, + args: Zm_T__Zdn_T__PgM__Zdn_T__1, + }, + // ZUMULH ., ., . + { + goOp: AZUMULH, + fixedBits: 0x4206c00, + args: Zm_T__Zn_T__Zd_T__1, + }, + }, + // ZUMULLB + { + // ZUMULLB ., ., . + { + goOp: AZUMULLB, + fixedBits: 0x45007800, + args: Zm_Tb__Zn_Tb__Zd_T__1, + }, + // ZUMULLB .H[], .H, .S + { + goOp: AZUMULLB, + fixedBits: 0x44a0d000, + args: Zm_H_imm___Zn_H__Zd_S, + }, + // ZUMULLB .S[], .S, .D + { + goOp: AZUMULLB, + fixedBits: 0x44e0d000, + args: Zm_S_imm___Zn_S__Zd_D, + }, + }, + // ZUMULLT + { + // ZUMULLT ., ., . + { + goOp: AZUMULLT, + fixedBits: 0x45007c00, + args: Zm_Tb__Zn_Tb__Zd_T__1, + }, + // ZUMULLT .H[], .H, .S + { + goOp: AZUMULLT, + fixedBits: 0x44a0d400, + args: Zm_H_imm___Zn_H__Zd_S, + }, + // ZUMULLT .S[], .S, .D + { + goOp: AZUMULLT, + fixedBits: 0x44e0d400, + args: Zm_S_imm___Zn_S__Zd_D, + }, + }, + // ZUQADD + { + // ZUQADD ., ., /M, . + { + goOp: AZUQADD, + fixedBits: 0x44198000, + args: Zm_T__Zdn_T__PgM__Zdn_T__1, + }, + // ZUQADD ., ., . + { + goOp: AZUQADD, + fixedBits: 0x4201400, + args: Zm_T__Zn_T__Zd_T__1, + }, + // ZUQADD #{, }, ., . + { + goOp: AZUQADD, + fixedBits: 0x2525c000, + args: cimm__shift__Zdn_T__Zdn_T, + }, + }, + // ZUQDECP + { + // ZUQDECP ., . + { + goOp: AZUQDECP, + fixedBits: 0x252b8000, + args: Pm_T__Zdn_T, + }, + }, + // ZUQINCP + { + // ZUQINCP ., . + { + goOp: AZUQINCP, + fixedBits: 0x25298000, + args: Pm_T__Zdn_T, + }, + }, + // ZUQRSHL + { + // ZUQRSHL ., ., /M, . + { + goOp: AZUQRSHL, + fixedBits: 0x440b8000, + args: Zm_T__Zdn_T__PgM__Zdn_T__1, + }, + }, + // ZUQRSHLR + { + // ZUQRSHLR ., ., /M, . + { + goOp: AZUQRSHLR, + fixedBits: 0x440f8000, + args: Zm_T__Zdn_T__PgM__Zdn_T__1, + }, + }, + // ZUQRSHRNB + { + // ZUQRSHRNB #, ., . + { + goOp: AZUQRSHRNB, + fixedBits: 0x45203800, + args: cconst__Zn_Tb__Zd_T__1, + }, + }, + // ZUQRSHRNT + { + // ZUQRSHRNT #, ., . + { + goOp: AZUQRSHRNT, + fixedBits: 0x45203c00, + args: cconst__Zn_Tb__Zd_T__1, + }, + }, + // ZUQSHL + { + // ZUQSHL ., ., /M, . + { + goOp: AZUQSHL, + fixedBits: 0x44098000, + args: Zm_T__Zdn_T__PgM__Zdn_T__1, + }, + // ZUQSHL #, ., /M, . + { + goOp: AZUQSHL, + fixedBits: 0x4078000, + args: cconst__Zdn_T__PgM__Zdn_T__2, + }, + }, + // ZUQSHLR + { + // ZUQSHLR ., ., /M, . + { + goOp: AZUQSHLR, + fixedBits: 0x440d8000, + args: Zm_T__Zdn_T__PgM__Zdn_T__1, + }, + }, + // ZUQSHRNB + { + // ZUQSHRNB #, ., . + { + goOp: AZUQSHRNB, + fixedBits: 0x45203000, + args: cconst__Zn_Tb__Zd_T__1, + }, + }, + // ZUQSHRNT + { + // ZUQSHRNT #, ., . + { + goOp: AZUQSHRNT, + fixedBits: 0x45203400, + args: cconst__Zn_Tb__Zd_T__1, + }, + }, + // ZUQSUB + { + // ZUQSUB ., ., /M, . + { + goOp: AZUQSUB, + fixedBits: 0x441b8000, + args: Zm_T__Zdn_T__PgM__Zdn_T__1, + }, + // ZUQSUB ., ., . + { + goOp: AZUQSUB, + fixedBits: 0x4201c00, + args: Zm_T__Zn_T__Zd_T__1, + }, + // ZUQSUB #{, }, ., . + { + goOp: AZUQSUB, + fixedBits: 0x2527c000, + args: cimm__shift__Zdn_T__Zdn_T, + }, + }, + // ZUQSUBR + { + // ZUQSUBR ., ., /M, . + { + goOp: AZUQSUBR, + fixedBits: 0x441f8000, + args: Zm_T__Zdn_T__PgM__Zdn_T__1, + }, + }, + // ZUQXTNB + { + // ZUQXTNB ., . + { + goOp: AZUQXTNB, + fixedBits: 0x45204800, + args: Zn_Tb__Zd_T__2, + }, + }, + // ZUQXTNT + { + // ZUQXTNT ., . + { + goOp: AZUQXTNT, + fixedBits: 0x45204c00, + args: Zn_Tb__Zd_T__2, + }, + }, + // ZURECPE + { + // ZURECPE .S, /M, .S + { + goOp: AZURECPE, + fixedBits: 0x4480a000, + args: Zn_S__PgM__Zd_S, + }, + // ZURECPE .S, /Z, .S + { + goOp: AZURECPE, + fixedBits: 0x4482a000, + args: Zn_S__PgZ__Zd_S, + }, + }, + // ZURHADD + { + // ZURHADD ., ., /M, . + { + goOp: AZURHADD, + fixedBits: 0x44158000, + args: Zm_T__Zdn_T__PgM__Zdn_T__1, + }, + }, + // ZURSHL + { + // ZURSHL ., ., /M, . + { + goOp: AZURSHL, + fixedBits: 0x44038000, + args: Zm_T__Zdn_T__PgM__Zdn_T__1, + }, + }, + // ZURSHLR + { + // ZURSHLR ., ., /M, . + { + goOp: AZURSHLR, + fixedBits: 0x44078000, + args: Zm_T__Zdn_T__PgM__Zdn_T__1, + }, + }, + // ZURSHR + { + // ZURSHR #, ., /M, . + { + goOp: AZURSHR, + fixedBits: 0x40d8000, + args: cconst__Zdn_T__PgM__Zdn_T__1, + }, + }, + // ZURSQRTE + { + // ZURSQRTE .S, /M, .S + { + goOp: AZURSQRTE, + fixedBits: 0x4481a000, + args: Zn_S__PgM__Zd_S, + }, + // ZURSQRTE .S, /Z, .S + { + goOp: AZURSQRTE, + fixedBits: 0x4483a000, + args: Zn_S__PgZ__Zd_S, + }, + }, + // ZURSRA + { + // ZURSRA #, ., . + { + goOp: AZURSRA, + fixedBits: 0x4500ec00, + args: cconst__Zn_T__Zda_T, + }, + }, + // ZUSDOT + { + // ZUSDOT .B, .B, .S + { + goOp: AZUSDOT, + fixedBits: 0x44807800, + args: Zm_B__Zn_B__Zda_S, + }, + // ZUSDOT .B[], .B, .S + { + goOp: AZUSDOT, + fixedBits: 0x44a01800, + args: Zm_B_imm___Zn_B__Zda_S__2, + }, + }, + // ZUSHLLB + { + // ZUSHLLB #, ., . + { + goOp: AZUSHLLB, + fixedBits: 0x4500a800, + args: cconst__Zn_Tb__Zd_T__2, + }, + }, + // ZUSHLLT + { + // ZUSHLLT #, ., . + { + goOp: AZUSHLLT, + fixedBits: 0x4500ac00, + args: cconst__Zn_Tb__Zd_T__2, + }, + }, + // ZUSMMLA + { + // ZUSMMLA .B, .B, .S + { + goOp: AZUSMMLA, + fixedBits: 0x45809800, + args: Zm_B__Zn_B__Zda_S, + }, + }, + // ZUSQADD + { + // ZUSQADD ., ., /M, . + { + goOp: AZUSQADD, + fixedBits: 0x441d8000, + args: Zm_T__Zdn_T__PgM__Zdn_T__1, + }, + }, + // ZUSRA + { + // ZUSRA #, ., . + { + goOp: AZUSRA, + fixedBits: 0x4500e400, + args: cconst__Zn_T__Zda_T, + }, + }, + // ZUSUBLB + { + // ZUSUBLB ., ., . + { + goOp: AZUSUBLB, + fixedBits: 0x45001800, + args: Zm_Tb__Zn_Tb__Zd_T__1, + }, + }, + // ZUSUBLT + { + // ZUSUBLT ., ., . + { + goOp: AZUSUBLT, + fixedBits: 0x45001c00, + args: Zm_Tb__Zn_Tb__Zd_T__1, + }, + }, + // ZUSUBWB + { + // ZUSUBWB ., ., . + { + goOp: AZUSUBWB, + fixedBits: 0x45005800, + args: Zm_Tb__Zn_T__Zd_T, + }, + }, + // ZUSUBWT + { + // ZUSUBWT ., ., . + { + goOp: AZUSUBWT, + fixedBits: 0x45005c00, + args: Zm_Tb__Zn_T__Zd_T, + }, + }, + // ZUUNPKHI + { + // ZUUNPKHI ., . + { + goOp: AZUUNPKHI, + fixedBits: 0x5333800, + args: Zn_Tb__Zd_T__1, + }, + }, + // ZUUNPKLO + { + // ZUUNPKLO ., . + { + goOp: AZUUNPKLO, + fixedBits: 0x5323800, + args: Zn_Tb__Zd_T__1, + }, + }, + // ZUXTB + { + // ZUXTB ., /M, . + { + goOp: AZUXTB, + fixedBits: 0x411a000, + args: Zn_T__PgM__Zd_T__4, + }, + // ZUXTB ., /Z, . + { + goOp: AZUXTB, + fixedBits: 0x401a000, + args: Zn_T__PgZ__Zd_T__4, + }, + }, + // ZUXTH + { + // ZUXTH ., /M, . + { + goOp: AZUXTH, + fixedBits: 0x493a000, + args: Zn_T__PgM__Zd_T__5, + }, + // ZUXTH ., /Z, . + { + goOp: AZUXTH, + fixedBits: 0x483a000, + args: Zn_T__PgZ__Zd_T__5, + }, + }, + // ZUXTW + { + // ZUXTW .D, /M, .D + { + goOp: AZUXTW, + fixedBits: 0x4d5a000, + args: Zn_D__PgM__Zd_D, + }, + // ZUXTW .D, /Z, .D + { + goOp: AZUXTW, + fixedBits: 0x4c5a000, + args: Zn_D__PgZ__Zd_D, + }, + }, + // ZUZP1 + { + // ZUZP1 .Q, .Q, .Q + { + goOp: AZUZP1, + fixedBits: 0x5a00800, + args: Zm_Q__Zn_Q__Zd_Q, + }, + // ZUZP1 ., ., . + { + goOp: AZUZP1, + fixedBits: 0x5206800, + args: Zm_T__Zn_T__Zd_T__1, + }, + }, + // ZUZP2 + { + // ZUZP2 .Q, .Q, .Q + { + goOp: AZUZP2, + fixedBits: 0x5a00c00, + args: Zm_Q__Zn_Q__Zd_Q, + }, + // ZUZP2 ., ., . + { + goOp: AZUZP2, + fixedBits: 0x5206c00, + args: Zm_T__Zn_T__Zd_T__1, + }, + }, + // ZUZPQ1 + { + // ZUZPQ1 ., ., . + { + goOp: AZUZPQ1, + fixedBits: 0x4400e800, + args: Zm_T__Zn_T__Zd_T__1, + }, + }, + // ZUZPQ2 + { + // ZUZPQ2 ., ., . + { + goOp: AZUZPQ2, + fixedBits: 0x4400ec00, + args: Zm_T__Zn_T__Zd_T__1, + }, + }, + // ZXAR + { + // ZXAR #, ., ., . + { + goOp: AZXAR, + fixedBits: 0x4203400, + args: cconst__Zm_T__Zdn_T__Zdn_T, + }, + }, + // ZZIP1 + { + // ZZIP1 .Q, .Q, .Q + { + goOp: AZZIP1, + fixedBits: 0x5a00000, + args: Zm_Q__Zn_Q__Zd_Q, + }, + // ZZIP1 ., ., . + { + goOp: AZZIP1, + fixedBits: 0x5206000, + args: Zm_T__Zn_T__Zd_T__1, + }, + }, + // ZZIP2 + { + // ZZIP2 .Q, .Q, .Q + { + goOp: AZZIP2, + fixedBits: 0x5a00400, + args: Zm_Q__Zn_Q__Zd_Q, + }, + // ZZIP2 ., ., . + { + goOp: AZZIP2, + fixedBits: 0x5206400, + args: Zm_T__Zn_T__Zd_T__1, + }, + }, + // ZZIPQ1 + { + // ZZIPQ1 ., ., . + { + goOp: AZZIPQ1, + fixedBits: 0x4400e000, + args: Zm_T__Zn_T__Zd_T__1, + }, + }, + // ZZIPQ2 + { + // ZZIPQ2 ., ., . + { + goOp: AZZIPQ2, + fixedBits: 0x4400e400, + args: Zm_T__Zn_T__Zd_T__1, + }, + }, +} + +var a_ARNGIDX_Zm1619_16Bit32Bit_ArngHCheck_I3hI3l_1923_16Bit = operand{ + class: AC_ARNGIDX, elemEncoders: []elemEncoder{ + {encodeZm1619_16Bit32Bit, enc_Zm}, + {encodeArngHCheck, enc_NIL}, + {encodeI3hI3l_1923_16Bit, enc_i3h_i3l}, + }, +} + +var a_ARNGIDX_Zm1619_16Bit32Bit_ArngSCheck_I2_1921_32Bit = operand{ + class: AC_ARNGIDX, elemEncoders: []elemEncoder{ + {encodeZm1619_16Bit32Bit, enc_Zm}, + {encodeArngSCheck, enc_NIL}, + {encodeI2_1921_32Bit, enc_i2}, + }, +} + +var a_ARNGIDX_Zm1619_32Bit_ArngHCheck_I3hI3l_1119_32Bit = operand{ + class: AC_ARNGIDX, elemEncoders: []elemEncoder{ + {encodeZm1619_32Bit, enc_Zm}, + {encodeArngHCheck, enc_NIL}, + {encodeI3hI3l_1119_32Bit, enc_i3h_i3l}, + }, +} + +var a_ARNGIDX_Zm1619_8To32Bit_ArngBCheck_I2_1921_8To32Bit = operand{ + class: AC_ARNGIDX, elemEncoders: []elemEncoder{ + {encodeZm1619_8To32Bit, enc_Zm}, + {encodeArngBCheck, enc_NIL}, + {encodeI2_1921_8To32Bit, enc_i2}, + }, +} + +var a_ARNGIDX_Zm1619_HalfSinglePrecision_ArngHCheck_I3hI3l_1923_HalfPrecision = operand{ + class: AC_ARNGIDX, elemEncoders: []elemEncoder{ + {encodeZm1619_HalfSinglePrecision, enc_Zm}, + {encodeArngHCheck, enc_NIL}, + {encodeI3hI3l_1923_HalfPrecision, enc_i3h_i3l}, + }, +} + +var a_ARNGIDX_Zm1619_HalfSinglePrecision_ArngSCheck_I2_1921_SinglePrecision = operand{ + class: AC_ARNGIDX, elemEncoders: []elemEncoder{ + {encodeZm1619_HalfSinglePrecision, enc_Zm}, + {encodeArngSCheck, enc_NIL}, + {encodeI2_1921_SinglePrecision, enc_i2}, + }, +} + +var a_ARNGIDX_Zm1620_16To64Bit_ArngHCheck_I1_2021_16To64Bit = operand{ + class: AC_ARNGIDX, elemEncoders: []elemEncoder{ + {encodeZm1620_16To64Bit, enc_Zm}, + {encodeArngHCheck, enc_NIL}, + {encodeI1_2021_16To64Bit, enc_i1}, + }, +} + +var a_ARNGIDX_Zm1620_64Bit_ArngDCheck_I1_2021_64Bit = operand{ + class: AC_ARNGIDX, elemEncoders: []elemEncoder{ + {encodeZm1620_64Bit, enc_Zm}, + {encodeArngDCheck, enc_NIL}, + {encodeI1_2021_64Bit, enc_i1}, + }, +} + +var a_ARNGIDX_Zm1620_64Bit_ArngSCheck_I2hI2l_1120_64Bit = operand{ + class: AC_ARNGIDX, elemEncoders: []elemEncoder{ + {encodeZm1620_64Bit, enc_Zm}, + {encodeArngSCheck, enc_NIL}, + {encodeI2hI2l_1120_64Bit, enc_i2h_i2l}, + }, +} + +var a_ARNGIDX_Zm1620_DoublePrecision_ArngDCheck_I1_2021_DoublePrecision = operand{ + class: AC_ARNGIDX, elemEncoders: []elemEncoder{ + {encodeZm1620_DoublePrecision, enc_Zm}, + {encodeArngDCheck, enc_NIL}, + {encodeI1_2021_DoublePrecision, enc_i1}, + }, +} + +var a_ARNGIDX_Zm_1619_Half_ArngHCheck_I2_1921_Half = operand{ + class: AC_ARNGIDX, elemEncoders: []elemEncoder{ + {encodeZm_1619_Half, enc_Zm}, + {encodeArngHCheck, enc_NIL}, + {encodeI2_1921_Half, enc_i2}, + }, +} + +var a_ARNGIDX_Zm_1619_Range0_7V1_ArngHCheck_I2_1921_16bit = operand{ + class: AC_ARNGIDX, elemEncoders: []elemEncoder{ + {encodeZm_1619_Range0_7V1, enc_Zm}, + {encodeArngHCheck, enc_NIL}, + {encodeI2_1921_16bit, enc_i2}, + }, +} + +var a_ARNGIDX_Zm_1619_Range0_7V2_ArngBCheck_I2_1921_8BitGroup = operand{ + class: AC_ARNGIDX, elemEncoders: []elemEncoder{ + {encodeZm_1619_Range0_7V2, enc_Zm}, + {encodeArngBCheck, enc_NIL}, + {encodeI2_1921_8BitGroup, enc_i2}, + }, +} + +var a_ARNGIDX_Zm_1619_Range0_7V2_ArngBCheck_I3hI3l_1119_Pair8Bit = operand{ + class: AC_ARNGIDX, elemEncoders: []elemEncoder{ + {encodeZm_1619_Range0_7V2, enc_Zm}, + {encodeArngBCheck, enc_NIL}, + {encodeI3hI3l_1119_Pair8Bit, enc_i3h_i3l}, + }, +} + +var a_ARNGIDX_Zm_1619_Range0_7V2_ArngBCheck_I3hI3l_1923_8To16Bit = operand{ + class: AC_ARNGIDX, elemEncoders: []elemEncoder{ + {encodeZm_1619_Range0_7V2, enc_Zm}, + {encodeArngBCheck, enc_NIL}, + {encodeI3hI3l_1923_8To16Bit, enc_i3h_i3l}, + }, +} + +var a_ARNGIDX_Zm_1619_Range0_7V2_ArngBCheck_I4hI4l_1019 = operand{ + class: AC_ARNGIDX, elemEncoders: []elemEncoder{ + {encodeZm_1619_Range0_7V2, enc_Zm}, + {encodeArngBCheck, enc_NIL}, + {encodeI4hI4l_1019, enc_i4h_i4l}, + }, +} + +var a_ARNGIDX_Zm_1619_Range0_7V2_ArngHCheck_I2_1921_16To32Bit = operand{ + class: AC_ARNGIDX, elemEncoders: []elemEncoder{ + {encodeZm_1619_Range0_7V2, enc_Zm}, + {encodeArngHCheck, enc_NIL}, + {encodeI2_1921_16To32Bit, enc_i2}, + }, +} + +var a_ARNGIDX_Zm_1619_Range0_7V2_ArngHCheck_I2_1921_Pair16Bit = operand{ + class: AC_ARNGIDX, elemEncoders: []elemEncoder{ + {encodeZm_1619_Range0_7V2, enc_Zm}, + {encodeArngHCheck, enc_NIL}, + {encodeI2_1921_Pair16Bit, enc_i2}, + }, +} + +var a_ARNGIDX_Zm_1619_Range0_7V2_ArngHCheck_I3hI3l_1119 = operand{ + class: AC_ARNGIDX, elemEncoders: []elemEncoder{ + {encodeZm_1619_Range0_7V2, enc_Zm}, + {encodeArngHCheck, enc_NIL}, + {encodeI3hI3l_1119, enc_i3h_i3l}, + }, +} + +var a_ARNGIDX_Zm_1619_Range0_7V2_ArngHCheck_I3hI3l_1922 = operand{ + class: AC_ARNGIDX, elemEncoders: []elemEncoder{ + {encodeZm_1619_Range0_7V2, enc_Zm}, + {encodeArngHCheck, enc_NIL}, + {encodeI3hI3l_1922, enc_i3h_i3l}, + }, +} + +var a_ARNGIDX_Zm_1620_Range0_15_ArngSCheck_I1_2021_32bit = operand{ + class: AC_ARNGIDX, elemEncoders: []elemEncoder{ + {encodeZm_1620_Range0_15, enc_Zm}, + {encodeArngSCheck, enc_NIL}, + {encodeI1_2021_32bit, enc_i1}, + }, +} + +var a_ARNGIDX_Zm_1620_Single_ArngSCheck_I1_2021_Single = operand{ + class: AC_ARNGIDX, elemEncoders: []elemEncoder{ + {encodeZm_1620_Single, enc_Zm}, + {encodeArngSCheck, enc_NIL}, + {encodeI1_2021_Single, enc_i1}, + }, +} + +var a_ARNGIDX_Zn510Src_Tsz_1620_SizeSpecifier4_I1Tsz_Delegate = operand{ + class: AC_ARNGIDX, elemEncoders: []elemEncoder{ + {encodeZn510Src, enc_Zn}, + {encodeTsz_1620_SizeSpecifier4, enc_tsz}, + {encodeI1Tsz_Delegate, enc_i1_tsz}, + }, +} + +var a_ARNGIDX_Zn510Src_Tsz_1621_SizeSpecifier5_Imm2Tsz_Delegate = operand{ + class: AC_ARNGIDX, elemEncoders: []elemEncoder{ + {encodeZn510Src, enc_Zn}, + {encodeTsz_1621_SizeSpecifier5, enc_tsz}, + {encodeImm2Tsz_Delegate, enc_imm2_tsz}, + }, +} + +var a_ARNG_PNd_SizeBHSD2224 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodePNd, enc_PNd}, + {encodeSizeBHSD2224, enc_size}, + }, +} + +var a_ARNG_Pd_ArngBCheck = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodePd, enc_Pd}, + {encodeArngBCheck, enc_NIL}, + }, +} + +var a_ARNG_Pd_ArngDCheck = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodePd, enc_Pd}, + {encodeArngDCheck, enc_NIL}, + }, +} + +var a_ARNG_Pd_ArngHCheck = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodePd, enc_Pd}, + {encodeArngHCheck, enc_NIL}, + }, +} + +var a_ARNG_Pd_ArngSCheck = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodePd, enc_Pd}, + {encodeArngSCheck, enc_NIL}, + }, +} + +var a_ARNG_Pd_Size0BH2223 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodePd, enc_Pd}, + {encodeSize0BH2223, enc_size0}, + }, +} + +var a_ARNG_Pd_SizeBHS2224 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodePd, enc_Pd}, + {encodeSizeBHS2224, enc_size}, + }, +} + +var a_ARNG_Pd_SizeBHSD2224 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodePd, enc_Pd}, + {encodeSizeBHSD2224, enc_size}, + }, +} + +var a_ARNG_Pd_SizeHSD2224 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodePd, enc_Pd}, + {encodeSizeHSD2224, enc_size}, + }, +} + +var a_ARNG_PdmDest_ArngBCheck = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodePdmDest, enc_Pdm}, + {encodeArngBCheck, enc_NIL}, + }, +} + +var a_ARNG_PdnDest_SizeBHSD2224 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodePdnDest, enc_Pdn}, + {encodeSizeBHSD2224, enc_size}, + }, +} + +var a_ARNG_PdnSrcDst_ArngBCheck = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodePdnSrcDst, enc_Pdn}, + {encodeArngBCheck, enc_NIL}, + }, +} + +var a_ARNG_Pm1620_ArngBCheck = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodePm1620, enc_Pm}, + {encodeArngBCheck, enc_NIL}, + }, +} + +var a_ARNG_Pm1620_SizeBHSD2224 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodePm1620, enc_Pm}, + {encodeSizeBHSD2224, enc_size}, + }, +} + +var a_ARNG_Pm59v1_SizeBHSD2224 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodePm59v1, enc_Pm}, + {encodeSizeBHSD2224, enc_size}, + }, +} + +var a_ARNG_Pm59v1_SizeHSD2224 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodePm59v1, enc_Pm}, + {encodeSizeHSD2224, enc_size}, + }, +} + +var a_ARNG_Pn59_ArngBCheck = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodePn59, enc_Pn}, + {encodeArngBCheck, enc_NIL}, + }, +} + +var a_ARNG_Pn59_SizeBHSD2224 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodePn59, enc_Pn}, + {encodeSizeBHSD2224, enc_size}, + }, +} + +var a_ARNG_Pn59v2_ArngBCheck = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodePn59v2, enc_Pn}, + {encodeArngBCheck, enc_NIL}, + }, +} + +var a_ARNG_Pn59v2_ArngDCheck = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodePn59v2, enc_Pn}, + {encodeArngDCheck, enc_NIL}, + }, +} + +var a_ARNG_Pn59v2_ArngHCheck = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodePn59v2, enc_Pn}, + {encodeArngHCheck, enc_NIL}, + }, +} + +var a_ARNG_Pn59v2_ArngSCheck = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodePn59v2, enc_Pn}, + {encodeArngSCheck, enc_NIL}, + }, +} + +var a_ARNG_Pn59v2_SizeBHSD2224 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodePn59v2, enc_Pn}, + {encodeSizeBHSD2224, enc_size}, + }, +} + +var a_ARNG_Vd_Size16B8H4S2D = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeVd, enc_Vd}, + {encodeSize16B8H4S2D, enc_size}, + }, +} + +var a_ARNG_Vd_Size8H4S2D = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeVd, enc_Vd}, + {encodeSize8H4S2D, enc_size}, + }, +} + +var a_ARNG_Za16213Rd_SizeHSD2224 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZa16213Rd, enc_Za}, + {encodeSizeHSD2224, enc_size}, + }, +} + +var a_ARNG_Za5103Rd_ArngDCheck = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZa5103Rd, enc_Za}, + {encodeArngDCheck, enc_NIL}, + }, +} + +var a_ARNG_Za5103Rd_SizeBHSD2224 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZa5103Rd, enc_Za}, + {encodeSizeBHSD2224, enc_size}, + }, +} + +var a_ARNG_Zd_ArngBCheck = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZd, enc_Zd}, + {encodeArngBCheck, enc_NIL}, + }, +} + +var a_ARNG_Zd_ArngDCheck = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZd, enc_Zd}, + {encodeArngDCheck, enc_NIL}, + }, +} + +var a_ARNG_Zd_ArngHCheck = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZd, enc_Zd}, + {encodeArngHCheck, enc_NIL}, + }, +} + +var a_ARNG_Zd_ArngQCheck = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZd, enc_Zd}, + {encodeArngQCheck, enc_NIL}, + }, +} + +var a_ARNG_Zd_ArngSCheck = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZd, enc_Zd}, + {encodeArngSCheck, enc_NIL}, + }, +} + +var a_ARNG_Zd_Size0HalfwordMergeZero = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZd, enc_Zd}, + {encodeSize0HalfwordMergeZero, enc_size0}, + }, +} + +var a_ARNG_Zd_Size0SD2223 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZd, enc_Zd}, + {encodeSize0SD2223, enc_size0}, + }, +} + +var a_ARNG_Zd_SizeBHS2224 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZd, enc_Zd}, + {encodeSizeBHS2224, enc_size}, + }, +} + +var a_ARNG_Zd_SizeBHS2224Offset1 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZd, enc_Zd}, + {encodeSizeBHS2224Offset1, enc_size}, + }, +} + +var a_ARNG_Zd_SizeBHSD2224 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZd, enc_Zd}, + {encodeSizeBHSD2224, enc_size}, + }, +} + +var a_ARNG_Zd_SizeBhsTsz1921 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZd, enc_Zd}, + {encodeSizeBhsTsz1921, enc_tszh_tszl}, + }, +} + +var a_ARNG_Zd_SizeBhsdTsz1921 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZd, enc_Zd}, + {encodeSizeBhsdTsz1921, enc_tszh_tszl}, + }, +} + +var a_ARNG_Zd_SizeByteMergeZero = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZd, enc_Zd}, + {encodeSizeByteMergeZero, enc_size}, + }, +} + +var a_ARNG_Zd_SizeHD2224 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZd, enc_Zd}, + {encodeSizeHD2224, enc_size}, + }, +} + +var a_ARNG_Zd_SizeHSD1315 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZd, enc_Zd}, + {encodeSizeHSD1315, enc_size}, + }, +} + +var a_ARNG_Zd_SizeHSD1719 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZd, enc_Zd}, + {encodeSizeHSD1719, enc_size}, + }, +} + +var a_ARNG_Zd_SizeHSD2224 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZd, enc_Zd}, + {encodeSizeHSD2224, enc_size}, + }, +} + +var a_ARNG_Zd_SizeHSD2224No00 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZd, enc_Zd}, + {encodeSizeHSD2224No00, enc_size}, + }, +} + +var a_ARNG_Zd_SizeHsdTsz1921 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZd, enc_Zd}, + {encodeSizeHsdTsz1921, enc_tszh_tszl}, + }, +} + +var a_ARNG_Zd_SizeImm13NoOp = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZd, enc_Zd}, + {encodeSizeImm13NoOp, enc_imm13}, + }, +} + +var a_ARNG_Zd_SzByteHalfword = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZd, enc_Zd}, + {encodeSzByteHalfword, enc_sz}, + }, +} + +var a_ARNG_Zd_SzSD1415 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZd, enc_Zd}, + {encodeSzSD1415, enc_sz}, + }, +} + +var a_ARNG_Zd_SzSD1718 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZd, enc_Zd}, + {encodeSzSD1718, enc_sz}, + }, +} + +var a_ARNG_Zd_SzSD2223 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZd, enc_Zd}, + {encodeSzSD2223, enc_sz}, + }, +} + +var a_ARNG_Zd_SzWordDoubleword = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZd, enc_Zd}, + {encodeSzWordDoubleword, enc_sz}, + }, +} + +var a_ARNG_Zd_Tsz_1620_SizeSpecifier4 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZd, enc_Zd}, + {encodeTsz_1620_SizeSpecifier4, enc_tsz}, + }, +} + +var a_ARNG_Zd_Tsz_1621_SizeSpecifier5 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZd, enc_Zd}, + {encodeTsz_1621_SizeSpecifier5, enc_tsz}, + }, +} + +var a_ARNG_Zd_TszhTszlBHS = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZd, enc_Zd}, + {encodeTszhTszlBHS, enc_tszh_tszl}, + }, +} + +var a_ARNG_Zda3RdSrcDst_ArngDCheck = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZda3RdSrcDst, enc_Zda}, + {encodeArngDCheck, enc_NIL}, + }, +} + +var a_ARNG_Zda3RdSrcDst_ArngHCheck = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZda3RdSrcDst, enc_Zda}, + {encodeArngHCheck, enc_NIL}, + }, +} + +var a_ARNG_Zda3RdSrcDst_ArngSCheck = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZda3RdSrcDst, enc_Zda}, + {encodeArngSCheck, enc_NIL}, + }, +} + +var a_ARNG_Zda3RdSrcDst_Size0SD2223 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZda3RdSrcDst, enc_Zda}, + {encodeSize0SD2223, enc_size0}, + }, +} + +var a_ARNG_Zda3RdSrcDst_SizeBHSD2224 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZda3RdSrcDst, enc_Zda}, + {encodeSizeBHSD2224, enc_size}, + }, +} + +var a_ARNG_Zda3RdSrcDst_SizeBhsdTsz1921 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZda3RdSrcDst, enc_Zda}, + {encodeSizeBhsdTsz1921, enc_tszh_tszl}, + }, +} + +var a_ARNG_Zda3RdSrcDst_SizeHSD2224 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZda3RdSrcDst, enc_Zda}, + {encodeSizeHSD2224, enc_size}, + }, +} + +var a_ARNG_Zda3RdSrcDst_SizeHSD2224No00 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZda3RdSrcDst, enc_Zda}, + {encodeSizeHSD2224No00, enc_size}, + }, +} + +var a_ARNG_Zda3RdSrcDst_SzSD2223 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZda3RdSrcDst, enc_Zda}, + {encodeSzSD2223, enc_sz}, + }, +} + +var a_ARNG_ZdaDest_SizeHSD2224 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZdaDest, enc_Zda}, + {encodeSizeHSD2224, enc_size}, + }, +} + +var a_ARNG_ZdnDest_ArngBCheck = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZdnDest, enc_Zdn}, + {encodeArngBCheck, enc_NIL}, + }, +} + +var a_ARNG_ZdnDest_ArngDCheck = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZdnDest, enc_Zdn}, + {encodeArngDCheck, enc_NIL}, + }, +} + +var a_ARNG_ZdnDest_ArngHCheck = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZdnDest, enc_Zdn}, + {encodeArngHCheck, enc_NIL}, + }, +} + +var a_ARNG_ZdnDest_ArngSCheck = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZdnDest, enc_Zdn}, + {encodeArngSCheck, enc_NIL}, + }, +} + +var a_ARNG_ZdnDest_Size0SD2223 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZdnDest, enc_Zdn}, + {encodeSize0SD2223, enc_size0}, + }, +} + +var a_ARNG_ZdnDest_SizeBHS2224 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZdnDest, enc_Zdn}, + {encodeSizeBHS2224, enc_size}, + }, +} + +var a_ARNG_ZdnDest_SizeBHSD2224 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZdnDest, enc_Zdn}, + {encodeSizeBHSD2224, enc_size}, + }, +} + +var a_ARNG_ZdnDest_SizeBhsdTsz1921 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZdnDest, enc_Zdn}, + {encodeSizeBhsdTsz1921, enc_tszh_tszl}, + }, +} + +var a_ARNG_ZdnDest_SizeHSD2224 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZdnDest, enc_Zdn}, + {encodeSizeHSD2224, enc_size}, + }, +} + +var a_ARNG_ZdnDest_SizeHSD2224No00 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZdnDest, enc_Zdn}, + {encodeSizeHSD2224No00, enc_size}, + }, +} + +var a_ARNG_ZdnSrcDst_ArngBCheck = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZdnSrcDst, enc_Zdn}, + {encodeArngBCheck, enc_NIL}, + }, +} + +var a_ARNG_ZdnSrcDst_SizeBHSD2224 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZdnSrcDst, enc_Zdn}, + {encodeSizeBHSD2224, enc_size}, + }, +} + +var a_ARNG_ZdnSrcDst_SizeBhsdTsz810 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZdnSrcDst, enc_Zdn}, + {encodeSizeBhsdTsz810, enc_tszh_tszl}, + }, +} + +var a_ARNG_ZdnSrcDst_SizeHSD2224 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZdnSrcDst, enc_Zdn}, + {encodeSizeHSD2224, enc_size}, + }, +} + +var a_ARNG_ZdnSrcDst_SizeImm13NoOp = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZdnSrcDst, enc_Zdn}, + {encodeSizeImm13NoOp, enc_imm13}, + }, +} + +var a_ARNG_Zk5103Rd_ArngDCheck = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZk5103Rd, enc_Zk}, + {encodeArngDCheck, enc_NIL}, + }, +} + +var a_ARNG_Zm1621V2_ArngBCheck = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZm1621V2, enc_Zm}, + {encodeArngBCheck, enc_NIL}, + }, +} + +var a_ARNG_Zm1621V2_ArngDCheck = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZm1621V2, enc_Zm}, + {encodeArngDCheck, enc_NIL}, + }, +} + +var a_ARNG_Zm1621V2_ArngHCheck = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZm1621V2, enc_Zm}, + {encodeArngHCheck, enc_NIL}, + }, +} + +var a_ARNG_Zm1621V2_ArngQCheck = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZm1621V2, enc_Zm}, + {encodeArngQCheck, enc_NIL}, + }, +} + +var a_ARNG_Zm1621V2_ArngSCheck = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZm1621V2, enc_Zm}, + {encodeArngSCheck, enc_NIL}, + }, +} + +var a_ARNG_Zm1621V2_Size0BH2223 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZm1621V2, enc_Zm}, + {encodeSize0BH2223, enc_size0}, + }, +} + +var a_ARNG_Zm1621V2_Size0SD2223 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZm1621V2, enc_Zm}, + {encodeSize0SD2223, enc_size0}, + }, +} + +var a_ARNG_Zm1621V2_Size0TbBH2223 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZm1621V2, enc_Zm}, + {encodeSize0TbBH2223, enc_size0}, + }, +} + +var a_ARNG_Zm1621V2_SizeBHSD2224 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZm1621V2, enc_Zm}, + {encodeSizeBHSD2224, enc_size}, + }, +} + +var a_ARNG_Zm1621V2_SizeHSD2224 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZm1621V2, enc_Zm}, + {encodeSizeHSD2224, enc_size}, + }, +} + +var a_ARNG_Zm1621V2_SizeHSD2224No00 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZm1621V2, enc_Zm}, + {encodeSizeHSD2224No00, enc_size}, + }, +} + +var a_ARNG_Zm1621V2_SizeTbBHS2224 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZm1621V2, enc_Zm}, + {encodeSizeTbBHS2224, enc_size}, + }, +} + +var a_ARNG_Zm1621V2_SizeTbBS2224 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZm1621V2, enc_Zm}, + {encodeSizeTbBS2224, enc_size}, + }, +} + +var a_ARNG_Zm1621V2_SizeTbHSD2224Offset1 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZm1621V2, enc_Zm}, + {encodeSizeTbHSD2224Offset1, enc_size}, + }, +} + +var a_ARNG_Zm1621V2_SzSD2223 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZm1621V2, enc_Zm}, + {encodeSzSD2223, enc_sz}, + }, +} + +var a_ARNG_Zm510V1_ArngBCheck = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZm510V1, enc_Zm}, + {encodeArngBCheck, enc_NIL}, + }, +} + +var a_ARNG_Zm510V1_ArngDCheck = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZm510V1, enc_Zm}, + {encodeArngDCheck, enc_NIL}, + }, } -var a_ARNGIDX_Zm1619_16Bit32Bit_ArngHCheck_I3hI3l_1923_16Bit = operand{ - class: AC_ARNGIDX, elemEncoders: []elemEncoder{ - {encodeZm1619_16Bit32Bit, enc_Zm}, +var a_ARNG_Zm510V1_ArngHCheck = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZm510V1, enc_Zm}, {encodeArngHCheck, enc_NIL}, - {encodeI3hI3l_1923_16Bit, enc_i3h_i3l}, }, } -var a_ARNGIDX_Zm1619_16Bit32Bit_ArngSCheck_I2_1921_32Bit = operand{ - class: AC_ARNGIDX, elemEncoders: []elemEncoder{ - {encodeZm1619_16Bit32Bit, enc_Zm}, +var a_ARNG_Zm510V1_ArngSCheck = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZm510V1, enc_Zm}, {encodeArngSCheck, enc_NIL}, - {encodeI2_1921_32Bit, enc_i2}, }, } -var a_ARNGIDX_Zm1619_32Bit_ArngHCheck_I3hI3l_1119_32Bit = operand{ - class: AC_ARNGIDX, elemEncoders: []elemEncoder{ - {encodeZm1619_32Bit, enc_Zm}, - {encodeArngHCheck, enc_NIL}, - {encodeI3hI3l_1119_32Bit, enc_i3h_i3l}, +var a_ARNG_Zm510V1_Size0SD2223 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZm510V1, enc_Zm}, + {encodeSize0SD2223, enc_size0}, }, } -var a_ARNGIDX_Zm1619_8To32Bit_ArngBCheck_I2_1921_8To32Bit = operand{ - class: AC_ARNGIDX, elemEncoders: []elemEncoder{ - {encodeZm1619_8To32Bit, enc_Zm}, - {encodeArngBCheck, enc_NIL}, - {encodeI2_1921_8To32Bit, enc_i2}, +var a_ARNG_Zm510V1_SizeBHSD2224 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZm510V1, enc_Zm}, + {encodeSizeBHSD2224, enc_size}, }, } -var a_ARNGIDX_Zm1619_HalfSinglePrecision_ArngHCheck_I3hI3l_1923_HalfPrecision = operand{ - class: AC_ARNGIDX, elemEncoders: []elemEncoder{ - {encodeZm1619_HalfSinglePrecision, enc_Zm}, - {encodeArngHCheck, enc_NIL}, - {encodeI3hI3l_1923_HalfPrecision, enc_i3h_i3l}, +var a_ARNG_Zm510V1_SizeBhsdTsz1921 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZm510V1, enc_Zm}, + {encodeSizeBhsdTsz1921, enc_tszh_tszl}, }, } -var a_ARNGIDX_Zm1619_HalfSinglePrecision_ArngSCheck_I2_1921_SinglePrecision = operand{ - class: AC_ARNGIDX, elemEncoders: []elemEncoder{ - {encodeZm1619_HalfSinglePrecision, enc_Zm}, - {encodeArngSCheck, enc_NIL}, - {encodeI2_1921_SinglePrecision, enc_i2}, +var a_ARNG_Zm510V1_SizeHSD2224 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZm510V1, enc_Zm}, + {encodeSizeHSD2224, enc_size}, }, } -var a_ARNGIDX_Zm1620_16To64Bit_ArngHCheck_I1_2021_16To64Bit = operand{ - class: AC_ARNGIDX, elemEncoders: []elemEncoder{ - {encodeZm1620_16To64Bit, enc_Zm}, - {encodeArngHCheck, enc_NIL}, - {encodeI1_2021_16To64Bit, enc_i1}, +var a_ARNG_Zm510V1_SizeHSD2224No00 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZm510V1, enc_Zm}, + {encodeSizeHSD2224No00, enc_size}, }, } -var a_ARNGIDX_Zm1620_64Bit_ArngDCheck_I1_2021_64Bit = operand{ - class: AC_ARNGIDX, elemEncoders: []elemEncoder{ - {encodeZm1620_64Bit, enc_Zm}, - {encodeArngDCheck, enc_NIL}, - {encodeI1_2021_64Bit, enc_i1}, +var a_ARNG_Zm510V2_SizeBHSD2224 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZm510V2, enc_Zm}, + {encodeSizeBHSD2224, enc_size}, }, } -var a_ARNGIDX_Zm1620_64Bit_ArngSCheck_I2hI2l_1120_64Bit = operand{ - class: AC_ARNGIDX, elemEncoders: []elemEncoder{ - {encodeZm1620_64Bit, enc_Zm}, - {encodeArngSCheck, enc_NIL}, - {encodeI2hI2l_1120_64Bit, enc_i2h_i2l}, +var a_ARNG_Zm510V2_SizeHSD2224 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZm510V2, enc_Zm}, + {encodeSizeHSD2224, enc_size}, }, } -var a_ARNGIDX_Zm1620_DoublePrecision_ArngDCheck_I1_2021_DoublePrecision = operand{ - class: AC_ARNGIDX, elemEncoders: []elemEncoder{ - {encodeZm1620_DoublePrecision, enc_Zm}, +var a_ARNG_Zn510Src_ArngBCheck = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZn510Src, enc_Zn}, + {encodeArngBCheck, enc_NIL}, + }, +} + +var a_ARNG_Zn510Src_ArngDCheck = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZn510Src, enc_Zn}, {encodeArngDCheck, enc_NIL}, - {encodeI1_2021_DoublePrecision, enc_i1}, }, } -var a_ARNGIDX_Zm_1619_Half_ArngHCheck_I2_1921_Half = operand{ - class: AC_ARNGIDX, elemEncoders: []elemEncoder{ - {encodeZm_1619_Half, enc_Zm}, +var a_ARNG_Zn510Src_ArngHCheck = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZn510Src, enc_Zn}, {encodeArngHCheck, enc_NIL}, - {encodeI2_1921_Half, enc_i2}, }, } -var a_ARNGIDX_Zm_1619_Range0_7V1_ArngHCheck_I2_1921_16bit = operand{ - class: AC_ARNGIDX, elemEncoders: []elemEncoder{ - {encodeZm_1619_Range0_7V1, enc_Zm}, - {encodeArngHCheck, enc_NIL}, - {encodeI2_1921_16bit, enc_i2}, +var a_ARNG_Zn510Src_ArngQCheck = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZn510Src, enc_Zn}, + {encodeArngQCheck, enc_NIL}, }, } -var a_ARNGIDX_Zm_1619_Range0_7V2_ArngBCheck_I2_1921_8BitGroup = operand{ - class: AC_ARNGIDX, elemEncoders: []elemEncoder{ - {encodeZm_1619_Range0_7V2, enc_Zm}, - {encodeArngBCheck, enc_NIL}, - {encodeI2_1921_8BitGroup, enc_i2}, +var a_ARNG_Zn510Src_ArngSCheck = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZn510Src, enc_Zn}, + {encodeArngSCheck, enc_NIL}, }, } -var a_ARNGIDX_Zm_1619_Range0_7V2_ArngBCheck_I3hI3l_1119_Pair8Bit = operand{ - class: AC_ARNGIDX, elemEncoders: []elemEncoder{ - {encodeZm_1619_Range0_7V2, enc_Zm}, - {encodeArngBCheck, enc_NIL}, - {encodeI3hI3l_1119_Pair8Bit, enc_i3h_i3l}, +var a_ARNG_Zn510Src_Size0HalfwordMergeZero = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZn510Src, enc_Zn}, + {encodeSize0HalfwordMergeZero, enc_size0}, }, } -var a_ARNGIDX_Zm_1619_Range0_7V2_ArngBCheck_I3hI3l_1923_8To16Bit = operand{ - class: AC_ARNGIDX, elemEncoders: []elemEncoder{ - {encodeZm_1619_Range0_7V2, enc_Zm}, - {encodeArngBCheck, enc_NIL}, - {encodeI3hI3l_1923_8To16Bit, enc_i3h_i3l}, +var a_ARNG_Zn510Src_SizeBHS2224 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZn510Src, enc_Zn}, + {encodeSizeBHS2224, enc_size}, }, } -var a_ARNGIDX_Zm_1619_Range0_7V2_ArngBCheck_I4hI4l_1019 = operand{ - class: AC_ARNGIDX, elemEncoders: []elemEncoder{ - {encodeZm_1619_Range0_7V2, enc_Zm}, - {encodeArngBCheck, enc_NIL}, - {encodeI4hI4l_1019, enc_i4h_i4l}, +var a_ARNG_Zn510Src_SizeBHSD2224 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZn510Src, enc_Zn}, + {encodeSizeBHSD2224, enc_size}, }, } -var a_ARNGIDX_Zm_1619_Range0_7V2_ArngHCheck_I2_1921_16To32Bit = operand{ - class: AC_ARNGIDX, elemEncoders: []elemEncoder{ - {encodeZm_1619_Range0_7V2, enc_Zm}, - {encodeArngHCheck, enc_NIL}, - {encodeI2_1921_16To32Bit, enc_i2}, +var a_ARNG_Zn510Src_SizeBhsTsz1921Unique = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZn510Src, enc_Zn}, + {encodeSizeBhsTsz1921Unique, enc_tszh_tszl}, }, } -var a_ARNGIDX_Zm_1619_Range0_7V2_ArngHCheck_I2_1921_Pair16Bit = operand{ - class: AC_ARNGIDX, elemEncoders: []elemEncoder{ - {encodeZm_1619_Range0_7V2, enc_Zm}, - {encodeArngHCheck, enc_NIL}, - {encodeI2_1921_Pair16Bit, enc_i2}, +var a_ARNG_Zn510Src_SizeBhsdTsz1921 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZn510Src, enc_Zn}, + {encodeSizeBhsdTsz1921, enc_tszh_tszl}, }, } -var a_ARNGIDX_Zm_1619_Range0_7V2_ArngHCheck_I3hI3l_1119 = operand{ - class: AC_ARNGIDX, elemEncoders: []elemEncoder{ - {encodeZm_1619_Range0_7V2, enc_Zm}, - {encodeArngHCheck, enc_NIL}, - {encodeI3hI3l_1119, enc_i3h_i3l}, +var a_ARNG_Zn510Src_SizeByteMergeZero = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZn510Src, enc_Zn}, + {encodeSizeByteMergeZero, enc_size}, }, } -var a_ARNGIDX_Zm_1619_Range0_7V2_ArngHCheck_I3hI3l_1922 = operand{ - class: AC_ARNGIDX, elemEncoders: []elemEncoder{ - {encodeZm_1619_Range0_7V2, enc_Zm}, - {encodeArngHCheck, enc_NIL}, - {encodeI3hI3l_1922, enc_i3h_i3l}, +var a_ARNG_Zn510Src_SizeHSD1315 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZn510Src, enc_Zn}, + {encodeSizeHSD1315, enc_size}, }, } -var a_ARNGIDX_Zm_1620_Range0_15_ArngSCheck_I1_2021_32bit = operand{ - class: AC_ARNGIDX, elemEncoders: []elemEncoder{ - {encodeZm_1620_Range0_15, enc_Zm}, - {encodeArngSCheck, enc_NIL}, - {encodeI1_2021_32bit, enc_i1}, +var a_ARNG_Zn510Src_SizeHSD1719 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZn510Src, enc_Zn}, + {encodeSizeHSD1719, enc_size}, }, } -var a_ARNGIDX_Zm_1620_Single_ArngSCheck_I1_2021_Single = operand{ - class: AC_ARNGIDX, elemEncoders: []elemEncoder{ - {encodeZm_1620_Single, enc_Zm}, - {encodeArngSCheck, enc_NIL}, - {encodeI1_2021_Single, enc_i1}, +var a_ARNG_Zn510Src_SizeHSD2224 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZn510Src, enc_Zn}, + {encodeSizeHSD2224, enc_size}, }, } -var a_ARNGIDX_Zn510Src_Tsz_1620_SizeSpecifier4_I1Tsz_Delegate = operand{ - class: AC_ARNGIDX, elemEncoders: []elemEncoder{ +var a_ARNG_Zn510Src_SizeHsdTsz1921Unique = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ {encodeZn510Src, enc_Zn}, - {encodeTsz_1620_SizeSpecifier4, enc_tsz}, - {encodeI1Tsz_Delegate, enc_i1_tsz}, + {encodeSizeHsdTsz1921Unique, enc_tszh_tszl}, }, } -var a_ARNGIDX_Zn510Src_Tsz_1621_SizeSpecifier5_Imm2Tsz_Delegate = operand{ - class: AC_ARNGIDX, elemEncoders: []elemEncoder{ +var a_ARNG_Zn510Src_SizeTbBHS2224 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ {encodeZn510Src, enc_Zn}, - {encodeTsz_1621_SizeSpecifier5, enc_tsz}, - {encodeImm2Tsz_Delegate, enc_imm2_tsz}, + {encodeSizeTbBHS2224, enc_size}, }, } -var a_ARNG_PNd_SizeBHSD2224 = operand{ +var a_ARNG_Zn510Src_SizeTbBHSD2224 = operand{ class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodePNd, enc_PNd}, - {encodeSizeBHSD2224, enc_size}, + {encodeZn510Src, enc_Zn}, + {encodeSizeTbBHSD2224, enc_size}, + }, +} + +var a_ARNG_Zn510Src_SizeTbHSD2224Offset1 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZn510Src, enc_Zn}, + {encodeSizeTbHSD2224Offset1, enc_size}, + }, +} + +var a_ARNG_Zn510Src_SzByteHalfword = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZn510Src, enc_Zn}, + {encodeSzByteHalfword, enc_sz}, + }, +} + +var a_ARNG_Zn510Src_SzSD1415 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZn510Src, enc_Zn}, + {encodeSzSD1415, enc_sz}, + }, +} + +var a_ARNG_Zn510Src_SzSD1718 = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZn510Src, enc_Zn}, + {encodeSzSD1718, enc_sz}, + }, +} + +var a_ARNG_Zn510Src_SzWordDoubleword = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZn510Src, enc_Zn}, + {encodeSzWordDoubleword, enc_sz}, + }, +} + +var a_ARNG_Zn510Src_TszhTszlTbHSD = operand{ + class: AC_ARNG, elemEncoders: []elemEncoder{ + {encodeZn510Src, enc_Zn}, + {encodeTszhTszlTbHSD, enc_tszh_tszl}, }, } -var a_ARNG_Pd_ArngBCheck = operand{ +var a_ARNG_Zn510V1_ArngBCheck = operand{ class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodePd, enc_Pd}, + {encodeZn510V1, enc_Zn}, {encodeArngBCheck, enc_NIL}, }, } -var a_ARNG_Pd_ArngDCheck = operand{ +var a_ARNG_Zn510V1_ArngDCheck = operand{ class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodePd, enc_Pd}, + {encodeZn510V1, enc_Zn}, {encodeArngDCheck, enc_NIL}, }, } -var a_ARNG_Pd_ArngHCheck = operand{ +var a_ARNG_Zn510V1_ArngHCheck = operand{ class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodePd, enc_Pd}, + {encodeZn510V1, enc_Zn}, {encodeArngHCheck, enc_NIL}, }, } -var a_ARNG_Pd_ArngSCheck = operand{ +var a_ARNG_Zn510V1_ArngQCheck = operand{ class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodePd, enc_Pd}, - {encodeArngSCheck, enc_NIL}, + {encodeZn510V1, enc_Zn}, + {encodeArngQCheck, enc_NIL}, }, } -var a_ARNG_Pd_Size0BH2223 = operand{ +var a_ARNG_Zn510V1_ArngSCheck = operand{ class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodePd, enc_Pd}, - {encodeSize0BH2223, enc_size0}, + {encodeZn510V1, enc_Zn}, + {encodeArngSCheck, enc_NIL}, }, } -var a_ARNG_Pd_SizeBHS2224 = operand{ +var a_ARNG_Zn510V1_Size0BH2223 = operand{ class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodePd, enc_Pd}, - {encodeSizeBHS2224, enc_size}, + {encodeZn510V1, enc_Zn}, + {encodeSize0BH2223, enc_size0}, }, } -var a_ARNG_Pd_SizeBHSD2224 = operand{ +var a_ARNG_Zn510V1_Size0SD2223 = operand{ class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodePd, enc_Pd}, - {encodeSizeBHSD2224, enc_size}, + {encodeZn510V1, enc_Zn}, + {encodeSize0SD2223, enc_size0}, }, } -var a_ARNG_Pd_SizeHSD2224 = operand{ +var a_ARNG_Zn510V1_Size0TbBH2223 = operand{ class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodePd, enc_Pd}, - {encodeSizeHSD2224, enc_size}, + {encodeZn510V1, enc_Zn}, + {encodeSize0TbBH2223, enc_size0}, }, } -var a_ARNG_PdmDest_ArngBCheck = operand{ +var a_ARNG_Zn510V1_SizeBHS2224 = operand{ class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodePdmDest, enc_Pdm}, - {encodeArngBCheck, enc_NIL}, + {encodeZn510V1, enc_Zn}, + {encodeSizeBHS2224, enc_size}, }, } -var a_ARNG_PdnDest_SizeBHSD2224 = operand{ +var a_ARNG_Zn510V1_SizeBHSD2224 = operand{ class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodePdnDest, enc_Pdn}, + {encodeZn510V1, enc_Zn}, {encodeSizeBHSD2224, enc_size}, }, } -var a_ARNG_PdnSrcDst_ArngBCheck = operand{ +var a_ARNG_Zn510V1_SizeBhsdTsz1921 = operand{ class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodePdnSrcDst, enc_Pdn}, - {encodeArngBCheck, enc_NIL}, + {encodeZn510V1, enc_Zn}, + {encodeSizeBhsdTsz1921, enc_tszh_tszl}, }, } -var a_ARNG_Pm1620_ArngBCheck = operand{ +var a_ARNG_Zn510V1_SizeHSD2224 = operand{ class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodePm1620, enc_Pm}, - {encodeArngBCheck, enc_NIL}, + {encodeZn510V1, enc_Zn}, + {encodeSizeHSD2224, enc_size}, }, } -var a_ARNG_Pm1620_SizeBHSD2224 = operand{ +var a_ARNG_Zn510V1_SizeHSD2224No00 = operand{ class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodePm1620, enc_Pm}, - {encodeSizeBHSD2224, enc_size}, + {encodeZn510V1, enc_Zn}, + {encodeSizeHSD2224No00, enc_size}, }, } -var a_ARNG_Pm59v1_SizeBHSD2224 = operand{ +var a_ARNG_Zn510V1_SizeTbBHS2224 = operand{ class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodePm59v1, enc_Pm}, - {encodeSizeBHSD2224, enc_size}, + {encodeZn510V1, enc_Zn}, + {encodeSizeTbBHS2224, enc_size}, }, } -var a_ARNG_Pm59v1_SizeHSD2224 = operand{ +var a_ARNG_Zn510V1_SizeTbBS2224 = operand{ class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodePm59v1, enc_Pm}, - {encodeSizeHSD2224, enc_size}, + {encodeZn510V1, enc_Zn}, + {encodeSizeTbBS2224, enc_size}, }, } -var a_ARNG_Pn59_ArngBCheck = operand{ +var a_ARNG_Zn510V1_SizeTbHSD2224Offset1 = operand{ class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodePn59, enc_Pn}, - {encodeArngBCheck, enc_NIL}, + {encodeZn510V1, enc_Zn}, + {encodeSizeTbHSD2224Offset1, enc_size}, }, } -var a_ARNG_Pn59_SizeBHSD2224 = operand{ +var a_ARNG_Zn510V1_SzSD2223 = operand{ class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodePn59, enc_Pn}, - {encodeSizeBHSD2224, enc_size}, + {encodeZn510V1, enc_Zn}, + {encodeSzSD2223, enc_sz}, }, } -var a_ARNG_Pn59v2_ArngBCheck = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodePn59v2, enc_Pn}, - {encodeArngBCheck, enc_NIL}, +var a_IMM_Fimm0_0_1_0_56 = operand{ + class: AC_IMM, elemEncoders: []elemEncoder{ + {encodeFimm0_0_1_0_56, enc_i1}, }, } -var a_ARNG_Pn59v2_ArngDCheck = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodePn59v2, enc_Pn}, - {encodeArngDCheck, enc_NIL}, +var a_IMM_Fimm0_0_56 = operand{ + class: AC_IMM, elemEncoders: []elemEncoder{ + {encodeFimm0_0_56, enc_NIL}, }, } -var a_ARNG_Pn59v2_ArngHCheck = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodePn59v2, enc_Pn}, - {encodeArngHCheck, enc_NIL}, +var a_IMM_Fimm0_5_1_0_56 = operand{ + class: AC_IMM, elemEncoders: []elemEncoder{ + {encodeFimm0_5_1_0_56, enc_i1}, }, } -var a_ARNG_Pn59v2_ArngSCheck = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodePn59v2, enc_Pn}, - {encodeArngSCheck, enc_NIL}, +var a_IMM_Fimm0_5_2_0_56 = operand{ + class: AC_IMM, elemEncoders: []elemEncoder{ + {encodeFimm0_5_2_0_56, enc_i1}, }, } -var a_ARNG_Pn59v2_SizeBHSD2224 = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodePn59v2, enc_Pn}, - {encodeSizeBHSD2224, enc_size}, +var a_IMM_Imm13_518 = operand{ + class: AC_IMM, elemEncoders: []elemEncoder{ + {encodeImm13_518, enc_imm13}, }, } -var a_ARNG_Vd_Size16B8H4S2D = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeVd, enc_Vd}, - {encodeSize16B8H4S2D, enc_size}, +var a_IMM_Imm3Unsigned_1619 = operand{ + class: AC_IMM, elemEncoders: []elemEncoder{ + {encodeImm3Unsigned_1619, enc_imm3}, }, } -var a_ARNG_Vd_Size8H4S2D = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeVd, enc_Vd}, - {encodeSize8H4S2D, enc_size}, +var a_IMM_Imm4Unsigned_1620 = operand{ + class: AC_IMM, elemEncoders: []elemEncoder{ + {encodeImm4Unsigned_1620, enc_imm4}, }, } -var a_ARNG_Za16213Rd_SizeHSD2224 = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZa16213Rd, enc_Za}, - {encodeSizeHSD2224, enc_size}, +var a_IMM_Imm5Signed510Unique = operand{ + class: AC_IMM, elemEncoders: []elemEncoder{ + {encodeImm5Signed510Unique, enc_imm5}, }, } -var a_ARNG_Za5103Rd_ArngDCheck = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZa5103Rd, enc_Za}, - {encodeArngDCheck, enc_NIL}, +var a_IMM_Imm5Signed_1621V1 = operand{ + class: AC_IMM, elemEncoders: []elemEncoder{ + {encodeImm5Signed_1621V1, enc_imm5}, }, } -var a_ARNG_Za5103Rd_SizeBHSD2224 = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZa5103Rd, enc_Za}, - {encodeSizeBHSD2224, enc_size}, +var a_IMM_Imm5Signed_1621V2 = operand{ + class: AC_IMM, elemEncoders: []elemEncoder{ + {encodeImm5Signed_1621V2, enc_imm5}, }, } -var a_ARNG_Zd_ArngBCheck = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZd, enc_Zd}, - {encodeArngBCheck, enc_NIL}, +var a_IMM_Imm5Signed_510 = operand{ + class: AC_IMM, elemEncoders: []elemEncoder{ + {encodeImm5Signed_510, enc_imm5}, }, } -var a_ARNG_Zd_ArngDCheck = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZd, enc_Zd}, - {encodeArngDCheck, enc_NIL}, +var a_IMM_Imm5bSigned_1621 = operand{ + class: AC_IMM, elemEncoders: []elemEncoder{ + {encodeImm5bSigned_1621, enc_imm5b}, }, } -var a_ARNG_Zd_ArngHCheck = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZd, enc_Zd}, - {encodeArngHCheck, enc_NIL}, +var a_IMM_Imm6Signed_511 = operand{ + class: AC_IMM, elemEncoders: []elemEncoder{ + {encodeImm6Signed_511, enc_imm6}, }, } -var a_ARNG_Zd_ArngQCheck = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZd, enc_Zd}, - {encodeArngQCheck, enc_NIL}, +var a_IMM_Imm7Unsigned_1421 = operand{ + class: AC_IMM, elemEncoders: []elemEncoder{ + {encodeImm7Unsigned_1421, enc_imm7}, }, } -var a_ARNG_Zd_ArngSCheck = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZd, enc_Zd}, - {encodeArngSCheck, enc_NIL}, +var a_IMM_Imm8SignedLsl8 = operand{ + class: AC_IMM, elemEncoders: []elemEncoder{ + {encodeImm8SignedLsl8, enc_imm8}, }, } -var a_ARNG_Zd_Size0HalfwordMergeZero = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZd, enc_Zd}, - {encodeSize0HalfwordMergeZero, enc_size0}, +var a_IMM_Imm8Signed_513 = operand{ + class: AC_IMM, elemEncoders: []elemEncoder{ + {encodeImm8Signed_513, enc_imm8}, }, } -var a_ARNG_Zd_Size0SD2223 = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZd, enc_Zd}, - {encodeSize0SD2223, enc_size0}, +var a_IMM_Imm8UnsignedLsl8 = operand{ + class: AC_IMM, elemEncoders: []elemEncoder{ + {encodeImm8UnsignedLsl8, enc_imm8}, }, } -var a_ARNG_Zd_SizeBHS2224 = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZd, enc_Zd}, - {encodeSizeBHS2224, enc_size}, +var a_IMM_Imm8Unsigned_513 = operand{ + class: AC_IMM, elemEncoders: []elemEncoder{ + {encodeImm8Unsigned_513, enc_imm8}, }, } -var a_ARNG_Zd_SizeBHS2224Offset1 = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZd, enc_Zd}, - {encodeSizeBHS2224Offset1, enc_size}, +var a_IMM_Imm8_513_Fimm = operand{ + class: AC_IMM, elemEncoders: []elemEncoder{ + {encodeImm8_513_Fimm, enc_imm8}, }, } -var a_ARNG_Zd_SizeBHSD2224 = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZd, enc_Zd}, - {encodeSizeBHSD2224, enc_size}, +var a_IMM_Imm8hImm8l_Unsigned = operand{ + class: AC_IMM, elemEncoders: []elemEncoder{ + {encodeImm8hImm8l_Unsigned, enc_imm8h_imm8l}, }, } -var a_ARNG_Zd_SizeBhsTsz1921 = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZd, enc_Zd}, - {encodeSizeBhsTsz1921, enc_tszh_tszl}, +var a_IMM_Rot0_90_180_270_1012 = operand{ + class: AC_IMM, elemEncoders: []elemEncoder{ + {encodeRot0_90_180_270_1012, enc_rot}, }, } -var a_ARNG_Zd_SizeBhsdTsz1921 = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZd, enc_Zd}, - {encodeSizeBhsdTsz1921, enc_tszh_tszl}, +var a_IMM_Rot0_90_180_270_1315 = operand{ + class: AC_IMM, elemEncoders: []elemEncoder{ + {encodeRot0_90_180_270_1315, enc_rot}, }, } -var a_ARNG_Zd_SizeByteMergeZero = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZd, enc_Zd}, - {encodeSizeByteMergeZero, enc_size}, +var a_IMM_Rot90_270_1011 = operand{ + class: AC_IMM, elemEncoders: []elemEncoder{ + {encodeRot90_270_1011, enc_rot}, }, } -var a_ARNG_Zd_SizeHD2224 = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZd, enc_Zd}, - {encodeSizeHD2224, enc_size}, +var a_IMM_Rot90_270_1617 = operand{ + class: AC_IMM, elemEncoders: []elemEncoder{ + {encodeRot90_270_1617, enc_rot}, }, } -var a_ARNG_Zd_SizeHSD1315 = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZd, enc_Zd}, - {encodeSizeHSD1315, enc_size}, +var a_IMM_ShiftTsz1619Range0V1 = operand{ + class: AC_IMM, elemEncoders: []elemEncoder{ + {encodeShiftTsz1619Range0V1, enc_tszh_tszl_imm3}, }, } -var a_ARNG_Zd_SizeHSD1719 = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZd, enc_Zd}, - {encodeSizeHSD1719, enc_size}, +var a_IMM_ShiftTsz1619Range0V2 = operand{ + class: AC_IMM, elemEncoders: []elemEncoder{ + {encodeShiftTsz1619Range0V2, enc_tszh_tszl_imm3}, + }, +} + +var a_IMM_ShiftTsz1619Range1V1 = operand{ + class: AC_IMM, elemEncoders: []elemEncoder{ + {encodeShiftTsz1619Range1V1, enc_tszh_tszl_imm3}, + }, +} + +var a_IMM_ShiftTsz1619Range1V2 = operand{ + class: AC_IMM, elemEncoders: []elemEncoder{ + {encodeShiftTsz1619Range1V2, enc_tszh_tszl_imm3}, }, } -var a_ARNG_Zd_SizeHSD2224 = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZd, enc_Zd}, - {encodeSizeHSD2224, enc_size}, +var a_IMM_ShiftTsz58Range0 = operand{ + class: AC_IMM, elemEncoders: []elemEncoder{ + {encodeShiftTsz58Range0, enc_tszh_tszl_imm3}, }, } -var a_ARNG_Zd_SizeHSD2224No00 = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZd, enc_Zd}, - {encodeSizeHSD2224No00, enc_size}, +var a_IMM_ShiftTsz58Range1 = operand{ + class: AC_IMM, elemEncoders: []elemEncoder{ + {encodeShiftTsz58Range1, enc_tszh_tszl_imm3}, }, } -var a_ARNG_Zd_SizeHsdTsz1921 = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZd, enc_Zd}, - {encodeSizeHsdTsz1921, enc_tszh_tszl}, +var a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt1Check = operand{ + class: AC_MEMEXT, elemEncoders: []elemEncoder{ + {encodeRn510SPV2, enc_Rn}, + {encodeNoop, enc_NIL}, + {encodeRm1621V2, enc_Rm}, + {encodeNoop, enc_NIL}, + {encodeModLSLCheck, enc_NIL}, + {encodeModAmt1Check, enc_NIL}, }, } -var a_ARNG_Zd_SizeImm13NoOp = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZd, enc_Zd}, - {encodeSizeImm13NoOp, enc_imm13}, +var a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt2Check = operand{ + class: AC_MEMEXT, elemEncoders: []elemEncoder{ + {encodeRn510SPV2, enc_Rn}, + {encodeNoop, enc_NIL}, + {encodeRm1621V2, enc_Rm}, + {encodeNoop, enc_NIL}, + {encodeModLSLCheck, enc_NIL}, + {encodeModAmt2Check, enc_NIL}, }, } -var a_ARNG_Zd_SzByteHalfword = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZd, enc_Zd}, - {encodeSzByteHalfword, enc_sz}, +var a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt3Check = operand{ + class: AC_MEMEXT, elemEncoders: []elemEncoder{ + {encodeRn510SPV2, enc_Rn}, + {encodeNoop, enc_NIL}, + {encodeRm1621V2, enc_Rm}, + {encodeNoop, enc_NIL}, + {encodeModLSLCheck, enc_NIL}, + {encodeModAmt3Check, enc_NIL}, }, } -var a_ARNG_Zd_SzSD1415 = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZd, enc_Zd}, - {encodeSzSD1415, enc_sz}, +var a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt4Check = operand{ + class: AC_MEMEXT, elemEncoders: []elemEncoder{ + {encodeRn510SPV2, enc_Rn}, + {encodeNoop, enc_NIL}, + {encodeRm1621V2, enc_Rm}, + {encodeNoop, enc_NIL}, + {encodeModLSLCheck, enc_NIL}, + {encodeModAmt4Check, enc_NIL}, }, } -var a_ARNG_Zd_SzSD1718 = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZd, enc_Zd}, - {encodeSzSD1718, enc_sz}, +var a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_NoModCheck_NoAmtCheck = operand{ + class: AC_MEMEXT, elemEncoders: []elemEncoder{ + {encodeRn510SPV2, enc_Rn}, + {encodeNoop, enc_NIL}, + {encodeRm1621V2, enc_Rm}, + {encodeNoop, enc_NIL}, + {encodeNoModCheck, enc_NIL}, + {encodeNoAmtCheck, enc_NIL}, }, } -var a_ARNG_Zd_SzWordDoubleword = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZd, enc_Zd}, - {encodeSzWordDoubleword, enc_sz}, +var a_MEMEXT_Rn510SPV2_Noop_Rm1621XZR_Noop_ModLSLCheck_ModAmt1Check = operand{ + class: AC_MEMEXT, elemEncoders: []elemEncoder{ + {encodeRn510SPV2, enc_Rn}, + {encodeNoop, enc_NIL}, + {encodeRm1621XZR, enc_Rm}, + {encodeNoop, enc_NIL}, + {encodeModLSLCheck, enc_NIL}, + {encodeModAmt1Check, enc_NIL}, }, } -var a_ARNG_Zd_Tsz_1620_SizeSpecifier4 = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZd, enc_Zd}, - {encodeTsz_1620_SizeSpecifier4, enc_tsz}, +var a_MEMEXT_Rn510SPV2_Noop_Rm1621XZR_Noop_ModLSLCheck_ModAmt2Check = operand{ + class: AC_MEMEXT, elemEncoders: []elemEncoder{ + {encodeRn510SPV2, enc_Rn}, + {encodeNoop, enc_NIL}, + {encodeRm1621XZR, enc_Rm}, + {encodeNoop, enc_NIL}, + {encodeModLSLCheck, enc_NIL}, + {encodeModAmt2Check, enc_NIL}, }, } -var a_ARNG_Zd_Tsz_1621_SizeSpecifier5 = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZd, enc_Zd}, - {encodeTsz_1621_SizeSpecifier5, enc_tsz}, +var a_MEMEXT_Rn510SPV2_Noop_Rm1621XZR_Noop_ModLSLCheck_ModAmt3Check = operand{ + class: AC_MEMEXT, elemEncoders: []elemEncoder{ + {encodeRn510SPV2, enc_Rn}, + {encodeNoop, enc_NIL}, + {encodeRm1621XZR, enc_Rm}, + {encodeNoop, enc_NIL}, + {encodeModLSLCheck, enc_NIL}, + {encodeModAmt3Check, enc_NIL}, }, } -var a_ARNG_Zd_TszhTszlBHS = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZd, enc_Zd}, - {encodeTszhTszlBHS, enc_tszh_tszl}, +var a_MEMEXT_Rn510SPV2_Noop_Rm1621XZR_Noop_NoModCheck_NoAmtCheck = operand{ + class: AC_MEMEXT, elemEncoders: []elemEncoder{ + {encodeRn510SPV2, enc_Rn}, + {encodeNoop, enc_NIL}, + {encodeRm1621XZR, enc_Rm}, + {encodeNoop, enc_NIL}, + {encodeNoModCheck, enc_NIL}, + {encodeNoAmtCheck, enc_NIL}, }, } -var a_ARNG_Zda3RdSrcDst_ArngDCheck = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZda3RdSrcDst, enc_Zda}, +var a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_ModLSLCheck_ModAmt1Check = operand{ + class: AC_MEMEXT, elemEncoders: []elemEncoder{ + {encodeRn510SPV2, enc_Rn}, + {encodeNoop, enc_NIL}, + {encodeZm1621V3, enc_Zm}, {encodeArngDCheck, enc_NIL}, + {encodeModLSLCheck, enc_NIL}, + {encodeModAmt1Check, enc_NIL}, }, } -var a_ARNG_Zda3RdSrcDst_ArngHCheck = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZda3RdSrcDst, enc_Zda}, - {encodeArngHCheck, enc_NIL}, - }, -} - -var a_ARNG_Zda3RdSrcDst_ArngSCheck = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZda3RdSrcDst, enc_Zda}, - {encodeArngSCheck, enc_NIL}, +var a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_ModLSLCheck_ModAmt2Check = operand{ + class: AC_MEMEXT, elemEncoders: []elemEncoder{ + {encodeRn510SPV2, enc_Rn}, + {encodeNoop, enc_NIL}, + {encodeZm1621V3, enc_Zm}, + {encodeArngDCheck, enc_NIL}, + {encodeModLSLCheck, enc_NIL}, + {encodeModAmt2Check, enc_NIL}, }, } -var a_ARNG_Zda3RdSrcDst_Size0SD2223 = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZda3RdSrcDst, enc_Zda}, - {encodeSize0SD2223, enc_size0}, +var a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_ModLSLCheck_ModAmt3Check = operand{ + class: AC_MEMEXT, elemEncoders: []elemEncoder{ + {encodeRn510SPV2, enc_Rn}, + {encodeNoop, enc_NIL}, + {encodeZm1621V3, enc_Zm}, + {encodeArngDCheck, enc_NIL}, + {encodeModLSLCheck, enc_NIL}, + {encodeModAmt3Check, enc_NIL}, }, } -var a_ARNG_Zda3RdSrcDst_SizeBHSD2224 = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZda3RdSrcDst, enc_Zda}, - {encodeSizeBHSD2224, enc_size}, +var a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_NoModCheck_NoAmtCheck = operand{ + class: AC_MEMEXT, elemEncoders: []elemEncoder{ + {encodeRn510SPV2, enc_Rn}, + {encodeNoop, enc_NIL}, + {encodeZm1621V3, enc_Zm}, + {encodeArngDCheck, enc_NIL}, + {encodeNoModCheck, enc_NIL}, + {encodeNoAmtCheck, enc_NIL}, }, } -var a_ARNG_Zda3RdSrcDst_SizeBhsdTsz1921 = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZda3RdSrcDst, enc_Zda}, - {encodeSizeBhsdTsz1921, enc_tszh_tszl}, +var a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_Xs1415_ModAmt1Check = operand{ + class: AC_MEMEXT, elemEncoders: []elemEncoder{ + {encodeRn510SPV2, enc_Rn}, + {encodeNoop, enc_NIL}, + {encodeZm1621V3, enc_Zm}, + {encodeArngDCheck, enc_NIL}, + {encodeXs1415, enc_xs}, + {encodeModAmt1Check, enc_NIL}, }, } -var a_ARNG_Zda3RdSrcDst_SizeHSD2224 = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZda3RdSrcDst, enc_Zda}, - {encodeSizeHSD2224, enc_size}, +var a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_Xs1415_ModAmt2Check = operand{ + class: AC_MEMEXT, elemEncoders: []elemEncoder{ + {encodeRn510SPV2, enc_Rn}, + {encodeNoop, enc_NIL}, + {encodeZm1621V3, enc_Zm}, + {encodeArngDCheck, enc_NIL}, + {encodeXs1415, enc_xs}, + {encodeModAmt2Check, enc_NIL}, }, } -var a_ARNG_Zda3RdSrcDst_SizeHSD2224No00 = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZda3RdSrcDst, enc_Zda}, - {encodeSizeHSD2224No00, enc_size}, +var a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_Xs1415_ModAmt3Check = operand{ + class: AC_MEMEXT, elemEncoders: []elemEncoder{ + {encodeRn510SPV2, enc_Rn}, + {encodeNoop, enc_NIL}, + {encodeZm1621V3, enc_Zm}, + {encodeArngDCheck, enc_NIL}, + {encodeXs1415, enc_xs}, + {encodeModAmt3Check, enc_NIL}, }, } -var a_ARNG_Zda3RdSrcDst_SzSD2223 = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZda3RdSrcDst, enc_Zda}, - {encodeSzSD2223, enc_sz}, +var a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_Xs1415_NoAmtCheck = operand{ + class: AC_MEMEXT, elemEncoders: []elemEncoder{ + {encodeRn510SPV2, enc_Rn}, + {encodeNoop, enc_NIL}, + {encodeZm1621V3, enc_Zm}, + {encodeArngDCheck, enc_NIL}, + {encodeXs1415, enc_xs}, + {encodeNoAmtCheck, enc_NIL}, }, } -var a_ARNG_ZdaDest_SizeHSD2224 = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZdaDest, enc_Zda}, - {encodeSizeHSD2224, enc_size}, +var a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_Xs2223_ModAmt1Check = operand{ + class: AC_MEMEXT, elemEncoders: []elemEncoder{ + {encodeRn510SPV2, enc_Rn}, + {encodeNoop, enc_NIL}, + {encodeZm1621V3, enc_Zm}, + {encodeArngDCheck, enc_NIL}, + {encodeXs2223, enc_xs}, + {encodeModAmt1Check, enc_NIL}, }, } -var a_ARNG_ZdnDest_ArngBCheck = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZdnDest, enc_Zdn}, - {encodeArngBCheck, enc_NIL}, +var a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_Xs2223_ModAmt2Check = operand{ + class: AC_MEMEXT, elemEncoders: []elemEncoder{ + {encodeRn510SPV2, enc_Rn}, + {encodeNoop, enc_NIL}, + {encodeZm1621V3, enc_Zm}, + {encodeArngDCheck, enc_NIL}, + {encodeXs2223, enc_xs}, + {encodeModAmt2Check, enc_NIL}, }, } -var a_ARNG_ZdnDest_ArngDCheck = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZdnDest, enc_Zdn}, +var a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_Xs2223_ModAmt3Check = operand{ + class: AC_MEMEXT, elemEncoders: []elemEncoder{ + {encodeRn510SPV2, enc_Rn}, + {encodeNoop, enc_NIL}, + {encodeZm1621V3, enc_Zm}, {encodeArngDCheck, enc_NIL}, + {encodeXs2223, enc_xs}, + {encodeModAmt3Check, enc_NIL}, }, } -var a_ARNG_ZdnDest_ArngHCheck = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZdnDest, enc_Zdn}, - {encodeArngHCheck, enc_NIL}, +var a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_Xs2223_NoAmtCheck = operand{ + class: AC_MEMEXT, elemEncoders: []elemEncoder{ + {encodeRn510SPV2, enc_Rn}, + {encodeNoop, enc_NIL}, + {encodeZm1621V3, enc_Zm}, + {encodeArngDCheck, enc_NIL}, + {encodeXs2223, enc_xs}, + {encodeNoAmtCheck, enc_NIL}, }, } -var a_ARNG_ZdnDest_ArngSCheck = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZdnDest, enc_Zdn}, +var a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngSCheck_Xs1415_ModAmt1Check = operand{ + class: AC_MEMEXT, elemEncoders: []elemEncoder{ + {encodeRn510SPV2, enc_Rn}, + {encodeNoop, enc_NIL}, + {encodeZm1621V3, enc_Zm}, {encodeArngSCheck, enc_NIL}, + {encodeXs1415, enc_xs}, + {encodeModAmt1Check, enc_NIL}, }, } -var a_ARNG_ZdnDest_Size0SD2223 = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZdnDest, enc_Zdn}, - {encodeSize0SD2223, enc_size0}, +var a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngSCheck_Xs1415_ModAmt2Check = operand{ + class: AC_MEMEXT, elemEncoders: []elemEncoder{ + {encodeRn510SPV2, enc_Rn}, + {encodeNoop, enc_NIL}, + {encodeZm1621V3, enc_Zm}, + {encodeArngSCheck, enc_NIL}, + {encodeXs1415, enc_xs}, + {encodeModAmt2Check, enc_NIL}, }, } -var a_ARNG_ZdnDest_SizeBHS2224 = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZdnDest, enc_Zdn}, - {encodeSizeBHS2224, enc_size}, +var a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngSCheck_Xs1415_NoAmtCheck = operand{ + class: AC_MEMEXT, elemEncoders: []elemEncoder{ + {encodeRn510SPV2, enc_Rn}, + {encodeNoop, enc_NIL}, + {encodeZm1621V3, enc_Zm}, + {encodeArngSCheck, enc_NIL}, + {encodeXs1415, enc_xs}, + {encodeNoAmtCheck, enc_NIL}, }, } -var a_ARNG_ZdnDest_SizeBHSD2224 = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZdnDest, enc_Zdn}, - {encodeSizeBHSD2224, enc_size}, +var a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngSCheck_Xs2223_ModAmt1Check = operand{ + class: AC_MEMEXT, elemEncoders: []elemEncoder{ + {encodeRn510SPV2, enc_Rn}, + {encodeNoop, enc_NIL}, + {encodeZm1621V3, enc_Zm}, + {encodeArngSCheck, enc_NIL}, + {encodeXs2223, enc_xs}, + {encodeModAmt1Check, enc_NIL}, }, } -var a_ARNG_ZdnDest_SizeBhsdTsz1921 = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZdnDest, enc_Zdn}, - {encodeSizeBhsdTsz1921, enc_tszh_tszl}, +var a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngSCheck_Xs2223_ModAmt2Check = operand{ + class: AC_MEMEXT, elemEncoders: []elemEncoder{ + {encodeRn510SPV2, enc_Rn}, + {encodeNoop, enc_NIL}, + {encodeZm1621V3, enc_Zm}, + {encodeArngSCheck, enc_NIL}, + {encodeXs2223, enc_xs}, + {encodeModAmt2Check, enc_NIL}, }, } -var a_ARNG_ZdnDest_SizeHSD2224 = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZdnDest, enc_Zdn}, - {encodeSizeHSD2224, enc_size}, +var a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngSCheck_Xs2223_NoAmtCheck = operand{ + class: AC_MEMEXT, elemEncoders: []elemEncoder{ + {encodeRn510SPV2, enc_Rn}, + {encodeNoop, enc_NIL}, + {encodeZm1621V3, enc_Zm}, + {encodeArngSCheck, enc_NIL}, + {encodeXs2223, enc_xs}, + {encodeNoAmtCheck, enc_NIL}, }, } -var a_ARNG_ZdnDest_SizeHSD2224No00 = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZdnDest, enc_Zdn}, - {encodeSizeHSD2224No00, enc_size}, +var a_MEMEXT_Zn510V2_ArngDCheck_Rm1621XZR_Noop_NoModCheck_NoAmtCheck = operand{ + class: AC_MEMEXT, elemEncoders: []elemEncoder{ + {encodeZn510V2, enc_Zn}, + {encodeArngDCheck, enc_NIL}, + {encodeRm1621XZR, enc_Rm}, + {encodeNoop, enc_NIL}, + {encodeNoModCheck, enc_NIL}, + {encodeNoAmtCheck, enc_NIL}, }, } -var a_ARNG_ZdnSrcDst_ArngBCheck = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZdnSrcDst, enc_Zdn}, - {encodeArngBCheck, enc_NIL}, +var a_MEMEXT_Zn510V2_ArngDCheck_Zm1621V3_ArngDCheck_ModSXTWCheck_Msz1012Amount = operand{ + class: AC_MEMEXT, elemEncoders: []elemEncoder{ + {encodeZn510V2, enc_Zn}, + {encodeArngDCheck, enc_NIL}, + {encodeZm1621V3, enc_Zm}, + {encodeArngDCheck, enc_NIL}, + {encodeModSXTWCheck, enc_NIL}, + {encodeMsz1012Amount, enc_msz}, }, } -var a_ARNG_ZdnSrcDst_SizeBHSD2224 = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZdnSrcDst, enc_Zdn}, - {encodeSizeBHSD2224, enc_size}, +var a_MEMEXT_Zn510V2_ArngDCheck_Zm1621V3_ArngDCheck_ModUXTWCheck_Msz1012Amount = operand{ + class: AC_MEMEXT, elemEncoders: []elemEncoder{ + {encodeZn510V2, enc_Zn}, + {encodeArngDCheck, enc_NIL}, + {encodeZm1621V3, enc_Zm}, + {encodeArngDCheck, enc_NIL}, + {encodeModUXTWCheck, enc_NIL}, + {encodeMsz1012Amount, enc_msz}, }, } -var a_ARNG_ZdnSrcDst_SizeBhsdTsz810 = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZdnSrcDst, enc_Zdn}, - {encodeSizeBhsdTsz810, enc_tszh_tszl}, +var a_MEMEXT_Zn510V2_ArngSCheck_Rm1621XZR_Noop_NoModCheck_NoAmtCheck = operand{ + class: AC_MEMEXT, elemEncoders: []elemEncoder{ + {encodeZn510V2, enc_Zn}, + {encodeArngSCheck, enc_NIL}, + {encodeRm1621XZR, enc_Rm}, + {encodeNoop, enc_NIL}, + {encodeNoModCheck, enc_NIL}, + {encodeNoAmtCheck, enc_NIL}, }, } -var a_ARNG_ZdnSrcDst_SizeHSD2224 = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZdnSrcDst, enc_Zdn}, - {encodeSizeHSD2224, enc_size}, +var a_MEMEXT_Zn510V2_SzSD2223_Zm1621V3_SzSD2223_Msz1012_Msz1012Amount = operand{ + class: AC_MEMEXT, elemEncoders: []elemEncoder{ + {encodeZn510V2, enc_Zn}, + {encodeSzSD2223, enc_sz}, + {encodeZm1621V3, enc_Zm}, + {encodeSzSD2223, enc_sz}, + {encodeMsz1012, enc_msz}, + {encodeMsz1012Amount, enc_msz}, }, } -var a_ARNG_ZdnSrcDst_SizeImm13NoOp = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZdnSrcDst, enc_Zdn}, - {encodeSizeImm13NoOp, enc_imm13}, +var a_PREGIDX_PnN_58_Noop_I189 = operand{ + class: AC_PREGIDX, elemEncoders: []elemEncoder{ + {encodePnN_58, enc_PNn}, + {encodeNoop, enc_NIL}, + {encodeI189, enc_i1}, }, } -var a_ARNG_Zk5103Rd_ArngDCheck = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZk5103Rd, enc_Zk}, - {encodeArngDCheck, enc_NIL}, +var a_PREGIDX_PnN_58_Noop_Imm2_810 = operand{ + class: AC_PREGIDX, elemEncoders: []elemEncoder{ + {encodePnN_58, enc_PNn}, + {encodeNoop, enc_NIL}, + {encodeImm2_810, enc_imm2}, }, } -var a_ARNG_Zm1621V2_ArngBCheck = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZm1621V2, enc_Zm}, - {encodeArngBCheck, enc_NIL}, +var a_PREGZM_Pg1013_MergePredCheck = operand{ + class: AC_PREGZM, elemEncoders: []elemEncoder{ + {encodePg1013, enc_Pg}, + {encodeMergePredCheck, enc_NIL}, }, } -var a_ARNG_Zm1621V2_ArngDCheck = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZm1621V2, enc_Zm}, - {encodeArngDCheck, enc_NIL}, +var a_PREGZM_Pg1013_PredQualM1617 = operand{ + class: AC_PREGZM, elemEncoders: []elemEncoder{ + {encodePg1013, enc_Pg}, + {encodePredQualM1617, enc_M}, }, } -var a_ARNG_Zm1621V2_ArngHCheck = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZm1621V2, enc_Zm}, - {encodeArngHCheck, enc_NIL}, +var a_PREGZM_Pg1013_ZeroPredCheck = operand{ + class: AC_PREGZM, elemEncoders: []elemEncoder{ + {encodePg1013, enc_Pg}, + {encodeZeroPredCheck, enc_NIL}, }, } -var a_ARNG_Zm1621V2_ArngQCheck = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZm1621V2, enc_Zm}, - {encodeArngQCheck, enc_NIL}, +var a_PREGZM_Pg1014_PredQualM45 = operand{ + class: AC_PREGZM, elemEncoders: []elemEncoder{ + {encodePg1014, enc_Pg}, + {encodePredQualM45, enc_M}, }, } -var a_ARNG_Zm1621V2_ArngSCheck = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZm1621V2, enc_Zm}, - {encodeArngSCheck, enc_NIL}, +var a_PREGZM_Pg1014_ZeroPredCheck = operand{ + class: AC_PREGZM, elemEncoders: []elemEncoder{ + {encodePg1014, enc_Pg}, + {encodeZeroPredCheck, enc_NIL}, }, } -var a_ARNG_Zm1621V2_Size0BH2223 = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZm1621V2, enc_Zm}, - {encodeSize0BH2223, enc_size0}, +var a_PREGZM_Pg1620_MergePredCheck = operand{ + class: AC_PREGZM, elemEncoders: []elemEncoder{ + {encodePg1620, enc_Pg}, + {encodeMergePredCheck, enc_NIL}, }, } -var a_ARNG_Zm1621V2_Size0SD2223 = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZm1621V2, enc_Zm}, - {encodeSize0SD2223, enc_size0}, +var a_PREGZM_Pg1620_ZeroPredCheck = operand{ + class: AC_PREGZM, elemEncoders: []elemEncoder{ + {encodePg1620, enc_Pg}, + {encodeZeroPredCheck, enc_NIL}, }, } -var a_ARNG_Zm1621V2_Size0TbBH2223 = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZm1621V2, enc_Zm}, - {encodeSize0TbBH2223, enc_size0}, +var a_PREGZM_Pg59_ZeroPredCheck = operand{ + class: AC_PREGZM, elemEncoders: []elemEncoder{ + {encodePg59, enc_Pg}, + {encodeZeroPredCheck, enc_NIL}, }, } -var a_ARNG_Zm1621V2_SizeBHSD2224 = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZm1621V2, enc_Zm}, - {encodeSizeBHSD2224, enc_size}, +var a_PREG_Pg1013_Noop = operand{ + class: AC_PREG, elemEncoders: []elemEncoder{ + {encodePg1013, enc_Pg}, + {encodeNoop, enc_NIL}, }, } -var a_ARNG_Zm1621V2_SizeHSD2224 = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZm1621V2, enc_Zm}, - {encodeSizeHSD2224, enc_size}, +var a_PREG_Pg1014_Noop = operand{ + class: AC_PREG, elemEncoders: []elemEncoder{ + {encodePg1014, enc_Pg}, + {encodeNoop, enc_NIL}, }, } -var a_ARNG_Zm1621V2_SizeHSD2224No00 = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZm1621V2, enc_Zm}, - {encodeSizeHSD2224No00, enc_size}, +var a_PREG_Pg59_Noop = operand{ + class: AC_PREG, elemEncoders: []elemEncoder{ + {encodePg59, enc_Pg}, + {encodeNoop, enc_NIL}, }, } -var a_ARNG_Zm1621V2_SizeTbBHS2224 = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZm1621V2, enc_Zm}, - {encodeSizeTbBHS2224, enc_size}, +var a_PREG_Pv1013_Noop = operand{ + class: AC_PREG, elemEncoders: []elemEncoder{ + {encodePv1013, enc_Pv}, + {encodeNoop, enc_NIL}, }, } -var a_ARNG_Zm1621V2_SizeTbBS2224 = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZm1621V2, enc_Zm}, - {encodeSizeTbBS2224, enc_size}, +var a_PREG_Pv1014_Noop = operand{ + class: AC_PREG, elemEncoders: []elemEncoder{ + {encodePv1014, enc_Pv}, + {encodeNoop, enc_NIL}, }, } -var a_ARNG_Zm1621V2_SizeTbHSD2224Offset1 = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZm1621V2, enc_Zm}, - {encodeSizeTbHSD2224Offset1, enc_size}, +var a_PREG_Pv59_Noop = operand{ + class: AC_PREG, elemEncoders: []elemEncoder{ + {encodePv59, enc_Pv}, + {encodeNoop, enc_NIL}, }, } -var a_ARNG_Zm1621V2_SzSD2223 = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZm1621V2, enc_Zm}, - {encodeSzSD2223, enc_sz}, +var a_REGLIST1_Zn510Table3_ArngBCheck = operand{ + class: AC_REGLIST1, elemEncoders: []elemEncoder{ + {encodeZn510Table3, enc_Zn}, + {encodeArngBCheck, enc_NIL}, }, } -var a_ARNG_Zm510V1_ArngBCheck = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZm510V1, enc_Zm}, - {encodeArngBCheck, enc_NIL}, +var a_REGLIST1_Zn510Table3_ArngHCheck = operand{ + class: AC_REGLIST1, elemEncoders: []elemEncoder{ + {encodeZn510Table3, enc_Zn}, + {encodeArngHCheck, enc_NIL}, }, } -var a_ARNG_Zm510V1_ArngDCheck = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZm510V1, enc_Zm}, - {encodeArngDCheck, enc_NIL}, +var a_REGLIST1_Zn510V1_SizeBHSD2224 = operand{ + class: AC_REGLIST1, elemEncoders: []elemEncoder{ + {encodeZn510V1, enc_Zn}, + {encodeSizeBHSD2224, enc_size}, }, } -var a_ARNG_Zm510V1_ArngHCheck = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZm510V1, enc_Zm}, - {encodeArngHCheck, enc_NIL}, +var a_REGLIST1_Zt05_ArngBCheck = operand{ + class: AC_REGLIST1, elemEncoders: []elemEncoder{ + {encodeZt05, enc_Zt}, + {encodeArngBCheck, enc_NIL}, }, } -var a_ARNG_Zm510V1_ArngSCheck = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZm510V1, enc_Zm}, - {encodeArngSCheck, enc_NIL}, +var a_REGLIST1_Zt05_ArngDCheck = operand{ + class: AC_REGLIST1, elemEncoders: []elemEncoder{ + {encodeZt05, enc_Zt}, + {encodeArngDCheck, enc_NIL}, }, } -var a_ARNG_Zm510V1_Size0SD2223 = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZm510V1, enc_Zm}, - {encodeSize0SD2223, enc_size0}, +var a_REGLIST1_Zt05_ArngHCheck = operand{ + class: AC_REGLIST1, elemEncoders: []elemEncoder{ + {encodeZt05, enc_Zt}, + {encodeArngHCheck, enc_NIL}, }, } -var a_ARNG_Zm510V1_SizeBHSD2224 = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZm510V1, enc_Zm}, - {encodeSizeBHSD2224, enc_size}, +var a_REGLIST1_Zt05_ArngQCheck = operand{ + class: AC_REGLIST1, elemEncoders: []elemEncoder{ + {encodeZt05, enc_Zt}, + {encodeArngQCheck, enc_NIL}, }, } -var a_ARNG_Zm510V1_SizeBhsdTsz1921 = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZm510V1, enc_Zm}, - {encodeSizeBhsdTsz1921, enc_tszh_tszl}, +var a_REGLIST1_Zt05_ArngSCheck = operand{ + class: AC_REGLIST1, elemEncoders: []elemEncoder{ + {encodeZt05, enc_Zt}, + {encodeArngSCheck, enc_NIL}, }, } -var a_ARNG_Zm510V1_SizeHSD2224 = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZm510V1, enc_Zm}, - {encodeSizeHSD2224, enc_size}, +var a_REGLIST1_Zt05_Size2123V1 = operand{ + class: AC_REGLIST1, elemEncoders: []elemEncoder{ + {encodeZt05, enc_Zt}, + {encodeSize2123V1, enc_size}, }, } -var a_ARNG_Zm510V1_SizeHSD2224No00 = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZm510V1, enc_Zm}, - {encodeSizeHSD2224No00, enc_size}, +var a_REGLIST1_Zt05_Size2123V2 = operand{ + class: AC_REGLIST1, elemEncoders: []elemEncoder{ + {encodeZt05, enc_Zt}, + {encodeSize2123V2, enc_size}, }, } -var a_ARNG_Zm510V2_SizeBHSD2224 = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZm510V2, enc_Zm}, +var a_REGLIST2_Pd04_SizeBHSD2224_Pd04Plus1_SizeBHSD2224 = operand{ + class: AC_REGLIST2, elemEncoders: []elemEncoder{ + {encodePd04, enc_Pd}, + {encodeSizeBHSD2224, enc_size}, + {encodePd04Plus1, enc_Pd}, {encodeSizeBHSD2224, enc_size}, }, } -var a_ARNG_Zm510V2_SizeHSD2224 = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZm510V2, enc_Zm}, - {encodeSizeHSD2224, enc_size}, +var a_REGLIST2_Pd14_SizeBHSD2224_Pd14Plus1_SizeBHSD2224 = operand{ + class: AC_REGLIST2, elemEncoders: []elemEncoder{ + {encodePd14, enc_Pd}, + {encodeSizeBHSD2224, enc_size}, + {encodePd14Plus1, enc_Pd}, + {encodeSizeBHSD2224, enc_size}, }, } -var a_ARNG_Zn510Src_ArngBCheck = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZn510Src, enc_Zn}, +var a_REGLIST2_Zn510MultiSrc1_ArngBCheck_Zn510MultiSrc2_ArngBCheck = operand{ + class: AC_REGLIST2, elemEncoders: []elemEncoder{ + {encodeZn510MultiSrc1, enc_Zn}, + {encodeArngBCheck, enc_NIL}, + {encodeZn510MultiSrc2, enc_Zn}, {encodeArngBCheck, enc_NIL}, }, } -var a_ARNG_Zn510Src_ArngDCheck = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZn510Src, enc_Zn}, - {encodeArngDCheck, enc_NIL}, - }, -} - -var a_ARNG_Zn510Src_ArngHCheck = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZn510Src, enc_Zn}, - {encodeArngHCheck, enc_NIL}, +var a_REGLIST2_Zn510MultiSrc1_SizeBHSD2224_Zn510MultiSrc2_SizeBHSD2224 = operand{ + class: AC_REGLIST2, elemEncoders: []elemEncoder{ + {encodeZn510MultiSrc1, enc_Zn}, + {encodeSizeBHSD2224, enc_size}, + {encodeZn510MultiSrc2, enc_Zn}, + {encodeSizeBHSD2224, enc_size}, }, } -var a_ARNG_Zn510Src_ArngQCheck = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZn510Src, enc_Zn}, - {encodeArngQCheck, enc_NIL}, +var a_REGLIST2_Zn510Table1_ArngBCheck_Zn510Table2_ArngBCheck = operand{ + class: AC_REGLIST2, elemEncoders: []elemEncoder{ + {encodeZn510Table1, enc_Zn}, + {encodeArngBCheck, enc_NIL}, + {encodeZn510Table2, enc_Zn}, + {encodeArngBCheck, enc_NIL}, }, } -var a_ARNG_Zn510Src_ArngSCheck = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZn510Src, enc_Zn}, - {encodeArngSCheck, enc_NIL}, +var a_REGLIST2_Zn510Table1_ArngHCheck_Zn510Table2_ArngHCheck = operand{ + class: AC_REGLIST2, elemEncoders: []elemEncoder{ + {encodeZn510Table1, enc_Zn}, + {encodeArngHCheck, enc_NIL}, + {encodeZn510Table2, enc_Zn}, + {encodeArngHCheck, enc_NIL}, }, } -var a_ARNG_Zn510Src_Size0HalfwordMergeZero = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZn510Src, enc_Zn}, - {encodeSize0HalfwordMergeZero, enc_size0}, +var a_REGLIST2_Zt051_ArngBCheck_Zt052_ArngBCheck = operand{ + class: AC_REGLIST2, elemEncoders: []elemEncoder{ + {encodeZt051, enc_Zt}, + {encodeArngBCheck, enc_NIL}, + {encodeZt052, enc_Zt}, + {encodeArngBCheck, enc_NIL}, }, } -var a_ARNG_Zn510Src_SizeBHS2224 = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZn510Src, enc_Zn}, - {encodeSizeBHS2224, enc_size}, +var a_REGLIST2_Zt051_ArngDCheck_Zt052_ArngDCheck = operand{ + class: AC_REGLIST2, elemEncoders: []elemEncoder{ + {encodeZt051, enc_Zt}, + {encodeArngDCheck, enc_NIL}, + {encodeZt052, enc_Zt}, + {encodeArngDCheck, enc_NIL}, }, } -var a_ARNG_Zn510Src_SizeBHSD2224 = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZn510Src, enc_Zn}, - {encodeSizeBHSD2224, enc_size}, +var a_REGLIST2_Zt051_ArngHCheck_Zt052_ArngHCheck = operand{ + class: AC_REGLIST2, elemEncoders: []elemEncoder{ + {encodeZt051, enc_Zt}, + {encodeArngHCheck, enc_NIL}, + {encodeZt052, enc_Zt}, + {encodeArngHCheck, enc_NIL}, }, } -var a_ARNG_Zn510Src_SizeBhsTsz1921Unique = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZn510Src, enc_Zn}, - {encodeSizeBhsTsz1921Unique, enc_tszh_tszl}, +var a_REGLIST2_Zt051_ArngQCheck_Zt052_ArngQCheck = operand{ + class: AC_REGLIST2, elemEncoders: []elemEncoder{ + {encodeZt051, enc_Zt}, + {encodeArngQCheck, enc_NIL}, + {encodeZt052, enc_Zt}, + {encodeArngQCheck, enc_NIL}, }, } -var a_ARNG_Zn510Src_SizeBhsdTsz1921 = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZn510Src, enc_Zn}, - {encodeSizeBhsdTsz1921, enc_tszh_tszl}, +var a_REGLIST2_Zt051_ArngSCheck_Zt052_ArngSCheck = operand{ + class: AC_REGLIST2, elemEncoders: []elemEncoder{ + {encodeZt051, enc_Zt}, + {encodeArngSCheck, enc_NIL}, + {encodeZt052, enc_Zt}, + {encodeArngSCheck, enc_NIL}, }, } -var a_ARNG_Zn510Src_SizeByteMergeZero = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZn510Src, enc_Zn}, - {encodeSizeByteMergeZero, enc_size}, +var a_REGLIST3_Zt051_ArngBCheck_Zt052_ArngBCheck_Zt053_ArngBCheck = operand{ + class: AC_REGLIST3, elemEncoders: []elemEncoder{ + {encodeZt051, enc_Zt}, + {encodeArngBCheck, enc_NIL}, + {encodeZt052, enc_Zt}, + {encodeArngBCheck, enc_NIL}, + {encodeZt053, enc_Zt}, + {encodeArngBCheck, enc_NIL}, }, } -var a_ARNG_Zn510Src_SizeHSD1315 = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZn510Src, enc_Zn}, - {encodeSizeHSD1315, enc_size}, +var a_REGLIST3_Zt051_ArngDCheck_Zt052_ArngDCheck_Zt053_ArngDCheck = operand{ + class: AC_REGLIST3, elemEncoders: []elemEncoder{ + {encodeZt051, enc_Zt}, + {encodeArngDCheck, enc_NIL}, + {encodeZt052, enc_Zt}, + {encodeArngDCheck, enc_NIL}, + {encodeZt053, enc_Zt}, + {encodeArngDCheck, enc_NIL}, }, } -var a_ARNG_Zn510Src_SizeHSD1719 = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZn510Src, enc_Zn}, - {encodeSizeHSD1719, enc_size}, +var a_REGLIST3_Zt051_ArngHCheck_Zt052_ArngHCheck_Zt053_ArngHCheck = operand{ + class: AC_REGLIST3, elemEncoders: []elemEncoder{ + {encodeZt051, enc_Zt}, + {encodeArngHCheck, enc_NIL}, + {encodeZt052, enc_Zt}, + {encodeArngHCheck, enc_NIL}, + {encodeZt053, enc_Zt}, + {encodeArngHCheck, enc_NIL}, }, } -var a_ARNG_Zn510Src_SizeHSD2224 = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZn510Src, enc_Zn}, - {encodeSizeHSD2224, enc_size}, +var a_REGLIST3_Zt051_ArngQCheck_Zt052_ArngQCheck_Zt053_ArngQCheck = operand{ + class: AC_REGLIST3, elemEncoders: []elemEncoder{ + {encodeZt051, enc_Zt}, + {encodeArngQCheck, enc_NIL}, + {encodeZt052, enc_Zt}, + {encodeArngQCheck, enc_NIL}, + {encodeZt053, enc_Zt}, + {encodeArngQCheck, enc_NIL}, }, } -var a_ARNG_Zn510Src_SizeHsdTsz1921Unique = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZn510Src, enc_Zn}, - {encodeSizeHsdTsz1921Unique, enc_tszh_tszl}, +var a_REGLIST3_Zt051_ArngSCheck_Zt052_ArngSCheck_Zt053_ArngSCheck = operand{ + class: AC_REGLIST3, elemEncoders: []elemEncoder{ + {encodeZt051, enc_Zt}, + {encodeArngSCheck, enc_NIL}, + {encodeZt052, enc_Zt}, + {encodeArngSCheck, enc_NIL}, + {encodeZt053, enc_Zt}, + {encodeArngSCheck, enc_NIL}, }, } -var a_ARNG_Zn510Src_SizeTbBHS2224 = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZn510Src, enc_Zn}, - {encodeSizeTbBHS2224, enc_size}, +var a_REGLIST4_Zt051_ArngBCheck_Zt052_ArngBCheck_Zt053_ArngBCheck_Zt054_ArngBCheck = operand{ + class: AC_REGLIST4, elemEncoders: []elemEncoder{ + {encodeZt051, enc_Zt}, + {encodeArngBCheck, enc_NIL}, + {encodeZt052, enc_Zt}, + {encodeArngBCheck, enc_NIL}, + {encodeZt053, enc_Zt}, + {encodeArngBCheck, enc_NIL}, + {encodeZt054, enc_Zt}, + {encodeArngBCheck, enc_NIL}, }, } -var a_ARNG_Zn510Src_SizeTbBHSD2224 = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZn510Src, enc_Zn}, - {encodeSizeTbBHSD2224, enc_size}, +var a_REGLIST4_Zt051_ArngDCheck_Zt052_ArngDCheck_Zt053_ArngDCheck_Zt054_ArngDCheck = operand{ + class: AC_REGLIST4, elemEncoders: []elemEncoder{ + {encodeZt051, enc_Zt}, + {encodeArngDCheck, enc_NIL}, + {encodeZt052, enc_Zt}, + {encodeArngDCheck, enc_NIL}, + {encodeZt053, enc_Zt}, + {encodeArngDCheck, enc_NIL}, + {encodeZt054, enc_Zt}, + {encodeArngDCheck, enc_NIL}, }, } -var a_ARNG_Zn510Src_SizeTbHSD2224Offset1 = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZn510Src, enc_Zn}, - {encodeSizeTbHSD2224Offset1, enc_size}, +var a_REGLIST4_Zt051_ArngHCheck_Zt052_ArngHCheck_Zt053_ArngHCheck_Zt054_ArngHCheck = operand{ + class: AC_REGLIST4, elemEncoders: []elemEncoder{ + {encodeZt051, enc_Zt}, + {encodeArngHCheck, enc_NIL}, + {encodeZt052, enc_Zt}, + {encodeArngHCheck, enc_NIL}, + {encodeZt053, enc_Zt}, + {encodeArngHCheck, enc_NIL}, + {encodeZt054, enc_Zt}, + {encodeArngHCheck, enc_NIL}, }, } -var a_ARNG_Zn510Src_SzByteHalfword = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZn510Src, enc_Zn}, - {encodeSzByteHalfword, enc_sz}, +var a_REGLIST4_Zt051_ArngQCheck_Zt052_ArngQCheck_Zt053_ArngQCheck_Zt054_ArngQCheck = operand{ + class: AC_REGLIST4, elemEncoders: []elemEncoder{ + {encodeZt051, enc_Zt}, + {encodeArngQCheck, enc_NIL}, + {encodeZt052, enc_Zt}, + {encodeArngQCheck, enc_NIL}, + {encodeZt053, enc_Zt}, + {encodeArngQCheck, enc_NIL}, + {encodeZt054, enc_Zt}, + {encodeArngQCheck, enc_NIL}, }, } -var a_ARNG_Zn510Src_SzSD1415 = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZn510Src, enc_Zn}, - {encodeSzSD1415, enc_sz}, +var a_REGLIST4_Zt051_ArngSCheck_Zt052_ArngSCheck_Zt053_ArngSCheck_Zt054_ArngSCheck = operand{ + class: AC_REGLIST4, elemEncoders: []elemEncoder{ + {encodeZt051, enc_Zt}, + {encodeArngSCheck, enc_NIL}, + {encodeZt052, enc_Zt}, + {encodeArngSCheck, enc_NIL}, + {encodeZt053, enc_Zt}, + {encodeArngSCheck, enc_NIL}, + {encodeZt054, enc_Zt}, + {encodeArngSCheck, enc_NIL}, }, } -var a_ARNG_Zn510Src_SzSD1718 = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZn510Src, enc_Zn}, - {encodeSzSD1718, enc_sz}, +var a_SPZGREG_Noop_Rd05 = operand{ + class: AC_SPZGREG, elemEncoders: []elemEncoder{ + {encodeNoop, enc_NIL}, + {encodeRd05, enc_Rd}, }, } -var a_ARNG_Zn510Src_SzWordDoubleword = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZn510Src, enc_Zn}, - {encodeSzWordDoubleword, enc_sz}, +var a_SPZGREG_Noop_Rd05ZR = operand{ + class: AC_SPZGREG, elemEncoders: []elemEncoder{ + {encodeNoop, enc_NIL}, + {encodeRd05ZR, enc_Rd}, }, } -var a_ARNG_Zn510Src_TszhTszlTbHSD = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZn510Src, enc_Zn}, - {encodeTszhTszlTbHSD, enc_tszh_tszl}, +var a_SPZGREG_Noop_Rdn05ZR = operand{ + class: AC_SPZGREG, elemEncoders: []elemEncoder{ + {encodeNoop, enc_NIL}, + {encodeRdn05ZR, enc_Rdn}, }, } -var a_ARNG_Zn510_ArngBCheck = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZn510, enc_Zn}, - {encodeArngBCheck, enc_NIL}, +var a_SPZGREG_Noop_Rm1621V1 = operand{ + class: AC_SPZGREG, elemEncoders: []elemEncoder{ + {encodeNoop, enc_NIL}, + {encodeRm1621V1, enc_Rm}, }, } -var a_ARNG_Zn510_ArngDCheck = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZn510, enc_Zn}, - {encodeArngDCheck, enc_NIL}, +var a_SPZGREG_Noop_Rm1621ZR = operand{ + class: AC_SPZGREG, elemEncoders: []elemEncoder{ + {encodeNoop, enc_NIL}, + {encodeRm1621ZR, enc_Rm}, }, } -var a_ARNG_Zn510_ArngHCheck = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZn510, enc_Zn}, - {encodeArngHCheck, enc_NIL}, +var a_SPZGREG_Noop_Rm510ZR = operand{ + class: AC_SPZGREG, elemEncoders: []elemEncoder{ + {encodeNoop, enc_NIL}, + {encodeRm510ZR, enc_Rm}, }, } -var a_ARNG_Zn510_ArngQCheck = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZn510, enc_Zn}, - {encodeArngQCheck, enc_NIL}, +var a_SPZGREG_Noop_Rn510 = operand{ + class: AC_SPZGREG, elemEncoders: []elemEncoder{ + {encodeNoop, enc_NIL}, + {encodeRn510, enc_Rn}, }, } -var a_ARNG_Zn510_ArngSCheck = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZn510, enc_Zn}, - {encodeArngSCheck, enc_NIL}, +var a_SPZGREG_Noop_Rn510SPV1 = operand{ + class: AC_SPZGREG, elemEncoders: []elemEncoder{ + {encodeNoop, enc_NIL}, + {encodeRn510SPV1, enc_Rn}, }, } -var a_ARNG_Zn510_Size0BH2223 = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZn510, enc_Zn}, - {encodeSize0BH2223, enc_size0}, +var a_SPZGREG_Noop_Rn510ZR = operand{ + class: AC_SPZGREG, elemEncoders: []elemEncoder{ + {encodeNoop, enc_NIL}, + {encodeRn510ZR, enc_Rn}, }, } -var a_ARNG_Zn510_Size0SD2223 = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZn510, enc_Zn}, - {encodeSize0SD2223, enc_size0}, +var a_SPZGREG_Noop_Wdn05 = operand{ + class: AC_SPZGREG, elemEncoders: []elemEncoder{ + {encodeNoop, enc_NIL}, + {encodeWdn05, enc_Rdn}, }, } -var a_ARNG_Zn510_Size0TbBH2223 = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZn510, enc_Zn}, - {encodeSize0TbBH2223, enc_size0}, +var a_SPZGREG_Noop_Xdn05 = operand{ + class: AC_SPZGREG, elemEncoders: []elemEncoder{ + {encodeNoop, enc_NIL}, + {encodeXdn05, enc_Rdn}, }, } -var a_ARNG_Zn510_SizeBHS2224 = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZn510, enc_Zn}, - {encodeSizeBHS2224, enc_size}, +var a_SPZGREG_XCheck_Rd05_SPAllowed = operand{ + class: AC_SPZGREG, elemEncoders: []elemEncoder{ + {encodeXCheck, enc_NIL}, + {encodeRd05_SPAllowed, enc_Rd}, }, } -var a_ARNG_Zn510_SizeBHSD2224 = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZn510, enc_Zn}, - {encodeSizeBHSD2224, enc_size}, +var a_SPZGREG_XCheck_Rn1621_SPAllowed = operand{ + class: AC_SPZGREG, elemEncoders: []elemEncoder{ + {encodeXCheck, enc_NIL}, + {encodeRn1621_SPAllowed, enc_Rn}, }, } -var a_ARNG_Zn510_SizeBhsdTsz1921 = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZn510, enc_Zn}, - {encodeSizeBhsdTsz1921, enc_tszh_tszl}, +var a_VREG_Noop_Vd05 = operand{ + class: AC_VREG, elemEncoders: []elemEncoder{ + {encodeNoop, enc_NIL}, + {encodeVd05, enc_Vd}, }, } -var a_ARNG_Zn510_SizeHSD2224 = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZn510, enc_Zn}, - {encodeSizeHSD2224, enc_size}, +var a_VREG_Noop_Vd0564 = operand{ + class: AC_VREG, elemEncoders: []elemEncoder{ + {encodeNoop, enc_NIL}, + {encodeVd0564, enc_Vd}, }, } -var a_ARNG_Zn510_SizeHSD2224No00 = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZn510, enc_Zn}, - {encodeSizeHSD2224No00, enc_size}, +var a_VREG_Noop_Vdn05 = operand{ + class: AC_VREG, elemEncoders: []elemEncoder{ + {encodeNoop, enc_NIL}, + {encodeVdn05, enc_Vdn}, }, } -var a_ARNG_Zn510_SizeTbBHS2224 = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZn510, enc_Zn}, - {encodeSizeTbBHS2224, enc_size}, +var a_VREG_Noop_Vm510 = operand{ + class: AC_VREG, elemEncoders: []elemEncoder{ + {encodeNoop, enc_NIL}, + {encodeVm510, enc_Vm}, }, } -var a_ARNG_Zn510_SizeTbBS2224 = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZn510, enc_Zn}, - {encodeSizeTbBS2224, enc_size}, +var a_VREG_Noop_Vn510 = operand{ + class: AC_VREG, elemEncoders: []elemEncoder{ + {encodeNoop, enc_NIL}, + {encodeVn510, enc_Vn}, }, } -var a_ARNG_Zn510_SizeTbHSD2224Offset1 = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZn510, enc_Zn}, - {encodeSizeTbHSD2224Offset1, enc_size}, +var a_ZREGIDX_Zd_Noop_I1_1718_Halfword = operand{ + class: AC_ZREGIDX, elemEncoders: []elemEncoder{ + {encodeZd, enc_Zd}, + {encodeNoop, enc_NIL}, + {encodeI1_1718_Halfword, enc_i1}, }, } -var a_ARNG_Zn510_SzSD2223 = operand{ - class: AC_ARNG, elemEncoders: []elemEncoder{ - {encodeZn510, enc_Zn}, - {encodeSzSD2223, enc_sz}, +var a_ZREGIDX_Zd_Noop_I2_1719_Word = operand{ + class: AC_ZREGIDX, elemEncoders: []elemEncoder{ + {encodeZd, enc_Zd}, + {encodeNoop, enc_NIL}, + {encodeI2_1719_Word, enc_i2}, }, } -var a_IMM_Fimm0_0_1_0_56 = operand{ - class: AC_IMM, elemEncoders: []elemEncoder{ - {encodeFimm0_0_1_0_56, enc_i1}, +var a_ZREGIDX_Zd_Noop_I3hI3l_1722_Doubleword = operand{ + class: AC_ZREGIDX, elemEncoders: []elemEncoder{ + {encodeZd, enc_Zd}, + {encodeNoop, enc_NIL}, + {encodeI3hI3l_1722_Doubleword, enc_i3h_i3l}, }, } -var a_IMM_Fimm0_0_56 = operand{ - class: AC_IMM, elemEncoders: []elemEncoder{ - {encodeFimm0_0_56, enc_NIL}, +var a_ZREGIDX_Zm1621V1_Noop_I12324 = operand{ + class: AC_ZREGIDX, elemEncoders: []elemEncoder{ + {encodeZm1621V1, enc_Zm}, + {encodeNoop, enc_NIL}, + {encodeI12324, enc_i1}, }, } -var a_IMM_Fimm0_5_1_0_56 = operand{ - class: AC_IMM, elemEncoders: []elemEncoder{ - {encodeFimm0_5_1_0_56, enc_i1}, +var a_ZREGIDX_Zm1621V1_Noop_I12324B = operand{ + class: AC_ZREGIDX, elemEncoders: []elemEncoder{ + {encodeZm1621V1, enc_Zm}, + {encodeNoop, enc_NIL}, + {encodeI12324B, enc_i1}, }, } -var a_IMM_Fimm0_5_2_0_56 = operand{ - class: AC_IMM, elemEncoders: []elemEncoder{ - {encodeFimm0_5_2_0_56, enc_i1}, +var a_ZREGIDX_Zm1621V1_Noop_I22224 = operand{ + class: AC_ZREGIDX, elemEncoders: []elemEncoder{ + {encodeZm1621V1, enc_Zm}, + {encodeNoop, enc_NIL}, + {encodeI22224, enc_i2}, }, } -var a_IMM_Imm13_518 = operand{ - class: AC_IMM, elemEncoders: []elemEncoder{ - {encodeImm13_518, enc_imm13}, +var a_ZREGIDX_Zm1621V1_Noop_I22224HW = operand{ + class: AC_ZREGIDX, elemEncoders: []elemEncoder{ + {encodeZm1621V1, enc_Zm}, + {encodeNoop, enc_NIL}, + {encodeI22224HW, enc_i2}, }, } -var a_IMM_Imm3Unsigned_1619 = operand{ - class: AC_IMM, elemEncoders: []elemEncoder{ - {encodeImm3Unsigned_1619, enc_imm3}, +var a_ZREGIDX_Zm1621V1_Noop_I3224I31213 = operand{ + class: AC_ZREGIDX, elemEncoders: []elemEncoder{ + {encodeZm1621V1, enc_Zm}, + {encodeNoop, enc_NIL}, + {encodeI3224I31213, enc_i3h_i3l}, }, } -var a_IMM_Imm4Unsigned_1620 = operand{ - class: AC_IMM, elemEncoders: []elemEncoder{ - {encodeImm4Unsigned_1620, enc_imm4}, +var a_ZREGIDX_Zn510Src_Noop_I1_1718_Halfword = operand{ + class: AC_ZREGIDX, elemEncoders: []elemEncoder{ + {encodeZn510Src, enc_Zn}, + {encodeNoop, enc_NIL}, + {encodeI1_1718_Halfword, enc_i1}, }, } -var a_IMM_Imm5Signed510Unique = operand{ - class: AC_IMM, elemEncoders: []elemEncoder{ - {encodeImm5Signed510Unique, enc_imm5}, +var a_ZREGIDX_Zn510Src_Noop_I2_1719_Word = operand{ + class: AC_ZREGIDX, elemEncoders: []elemEncoder{ + {encodeZn510Src, enc_Zn}, + {encodeNoop, enc_NIL}, + {encodeI2_1719_Word, enc_i2}, + }, +} + +var a_ZREGIDX_Zn510Src_Noop_I3hI3l_1722_Doubleword = operand{ + class: AC_ZREGIDX, elemEncoders: []elemEncoder{ + {encodeZn510Src, enc_Zn}, + {encodeNoop, enc_NIL}, + {encodeI3hI3l_1722_Doubleword, enc_i3h_i3l}, }, } -var a_IMM_Imm5Signed_1621V1 = operand{ - class: AC_IMM, elemEncoders: []elemEncoder{ - {encodeImm5Signed_1621V1, enc_imm5}, +var a_ZREG_Zd_Noop = operand{ + class: AC_ZREG, elemEncoders: []elemEncoder{ + {encodeZd, enc_Zd}, + {encodeNoop, enc_NIL}, }, } -var a_IMM_Imm5Signed_1621V2 = operand{ - class: AC_IMM, elemEncoders: []elemEncoder{ - {encodeImm5Signed_1621V2, enc_imm5}, +var a_ZREG_Zm1621V1_Noop = operand{ + class: AC_ZREG, elemEncoders: []elemEncoder{ + {encodeZm1621V1, enc_Zm}, + {encodeNoop, enc_NIL}, }, } -var a_IMM_Imm5Signed_510 = operand{ - class: AC_IMM, elemEncoders: []elemEncoder{ - {encodeImm5Signed_510, enc_imm5}, +var a_ZREG_Zn510Src_Noop = operand{ + class: AC_ZREG, elemEncoders: []elemEncoder{ + {encodeZn510Src, enc_Zn}, + {encodeNoop, enc_NIL}, }, } -var a_IMM_Imm5bSigned_1621 = operand{ - class: AC_IMM, elemEncoders: []elemEncoder{ - {encodeImm5bSigned_1621, enc_imm5b}, - }, +var PNd_T = []operand{ + a_ARNG_PNd_SizeBHSD2224, } -var a_IMM_Imm6Signed_511 = operand{ - class: AC_IMM, elemEncoders: []elemEncoder{ - {encodeImm6Signed_511, enc_imm6}, - }, +var PNn_imm___Pd_T = []operand{ + a_PREGIDX_PnN_58_Noop_Imm2_810, + a_ARNG_Pd_SizeBHSD2224, } -var a_IMM_Imm7Unsigned_1421 = operand{ - class: AC_IMM, elemEncoders: []elemEncoder{ - {encodeImm7Unsigned_1421, enc_imm7}, - }, +var PNn_imm____Pd1_T__Pd2_T_ = []operand{ + a_PREGIDX_PnN_58_Noop_I189, + a_REGLIST2_Pd04_SizeBHSD2224_Pd04Plus1_SizeBHSD2224, } -var a_IMM_Imm8SignedLsl8 = operand{ - class: AC_IMM, elemEncoders: []elemEncoder{ - {encodeImm8SignedLsl8, enc_imm8}, - }, +var Pd_B = []operand{ + a_ARNG_Pd_ArngBCheck, } -var a_IMM_Imm8Signed_513 = operand{ - class: AC_IMM, elemEncoders: []elemEncoder{ - {encodeImm8Signed_513, enc_imm8}, - }, +var Pdm_B__Pn_B__PgZ__Pdm_B = []operand{ + a_ARNG_PdmDest_ArngBCheck, + a_ARNG_Pn59_ArngBCheck, + a_PREGZM_Pg1014_ZeroPredCheck, + a_ARNG_PdmDest_ArngBCheck, } -var a_IMM_Imm8UnsignedLsl8 = operand{ - class: AC_IMM, elemEncoders: []elemEncoder{ - {encodeImm8UnsignedLsl8, enc_imm8}, - }, +var Pdn_B__Pg__Pdn_B = []operand{ + a_ARNG_PdnSrcDst_ArngBCheck, + a_PREG_Pg59_Noop, + a_ARNG_PdnSrcDst_ArngBCheck, } -var a_IMM_Imm8Unsigned_513 = operand{ - class: AC_IMM, elemEncoders: []elemEncoder{ - {encodeImm8Unsigned_513, enc_imm8}, - }, +var Pdn_T__Pv__Pdn_T = []operand{ + a_ARNG_PdnDest_SizeBHSD2224, + a_PREG_Pv59_Noop, + a_ARNG_PdnDest_SizeBHSD2224, } -var a_IMM_Imm8_513_Fimm = operand{ - class: AC_IMM, elemEncoders: []elemEncoder{ - {encodeImm8_513_Fimm, enc_imm8}, - }, +var PgZ__Pd_B = []operand{ + a_PREGZM_Pg59_ZeroPredCheck, + a_ARNG_Pd_ArngBCheck, } -var a_IMM_Imm8hImm8l_Unsigned = operand{ - class: AC_IMM, elemEncoders: []elemEncoder{ - {encodeImm8hImm8l_Unsigned, enc_imm8h_imm8l}, - }, +var Pm_B__Pn_B__PgZ__Pd_B = []operand{ + a_ARNG_Pm1620_ArngBCheck, + a_ARNG_Pn59_ArngBCheck, + a_PREGZM_Pg1014_ZeroPredCheck, + a_ARNG_Pd_ArngBCheck, } -var a_IMM_Rot0_90_180_270_1012 = operand{ - class: AC_IMM, elemEncoders: []elemEncoder{ - {encodeRot0_90_180_270_1012, enc_rot}, - }, +var Pm_B__Pn_B__Pg__Pd_B = []operand{ + a_ARNG_Pm1620_ArngBCheck, + a_ARNG_Pn59_ArngBCheck, + a_PREG_Pg1014_Noop, + a_ARNG_Pd_ArngBCheck, } -var a_IMM_Rot0_90_180_270_1315 = operand{ - class: AC_IMM, elemEncoders: []elemEncoder{ - {encodeRot0_90_180_270_1315, enc_rot}, - }, +var Pm_T__Pn_T__Pd_T = []operand{ + a_ARNG_Pm1620_SizeBHSD2224, + a_ARNG_Pn59_SizeBHSD2224, + a_ARNG_Pd_SizeBHSD2224, } -var a_IMM_Rot90_270_1011 = operand{ - class: AC_IMM, elemEncoders: []elemEncoder{ - {encodeRot90_270_1011, enc_rot}, - }, +var Pm_T__Wdn = []operand{ + a_ARNG_Pm59v1_SizeBHSD2224, + a_SPZGREG_Noop_Wdn05, } -var a_IMM_Rot90_270_1617 = operand{ - class: AC_IMM, elemEncoders: []elemEncoder{ - {encodeRot90_270_1617, enc_rot}, - }, +var Pm_T__Xdn = []operand{ + a_ARNG_Pm59v1_SizeBHSD2224, + a_SPZGREG_Noop_Xdn05, } -var a_IMM_ShiftTsz1619Range0V1 = operand{ - class: AC_IMM, elemEncoders: []elemEncoder{ - {encodeShiftTsz1619Range0V1, enc_tszh_tszl_imm3}, - }, +var Pm_T__Zdn_T = []operand{ + a_ARNG_Pm59v1_SizeHSD2224, + a_ARNG_ZdnSrcDst_SizeHSD2224, } -var a_IMM_ShiftTsz1619Range0V2 = operand{ - class: AC_IMM, elemEncoders: []elemEncoder{ - {encodeShiftTsz1619Range0V2, enc_tszh_tszl_imm3}, - }, +var Pn_B = []operand{ + a_ARNG_Pn59v2_ArngBCheck, } -var a_IMM_ShiftTsz1619Range1V1 = operand{ - class: AC_IMM, elemEncoders: []elemEncoder{ - {encodeShiftTsz1619Range1V1, enc_tszh_tszl_imm3}, - }, +var Pn_B__Pd_H = []operand{ + a_ARNG_Pn59v2_ArngBCheck, + a_ARNG_Pd_ArngHCheck, } -var a_IMM_ShiftTsz1619Range1V2 = operand{ - class: AC_IMM, elemEncoders: []elemEncoder{ - {encodeShiftTsz1619Range1V2, enc_tszh_tszl_imm3}, - }, +var Pn_B__Pg = []operand{ + a_ARNG_Pn59v2_ArngBCheck, + a_PREG_Pg1014_Noop, } -var a_IMM_ShiftTsz58Range0 = operand{ - class: AC_IMM, elemEncoders: []elemEncoder{ - {encodeShiftTsz58Range0, enc_tszh_tszl_imm3}, - }, +var Pn_B__PgZM__Pd_B = []operand{ + a_ARNG_Pn59v2_ArngBCheck, + a_PREGZM_Pg1014_PredQualM45, + a_ARNG_Pd_ArngBCheck, } -var a_IMM_ShiftTsz58Range1 = operand{ - class: AC_IMM, elemEncoders: []elemEncoder{ - {encodeShiftTsz58Range1, enc_tszh_tszl_imm3}, - }, +var Pn_B__PgZ__Pd_B = []operand{ + a_ARNG_Pn59v2_ArngBCheck, + a_PREGZM_Pg1014_ZeroPredCheck, + a_ARNG_Pd_ArngBCheck, } -var a_PREGIDX_PnN_58_Noop_I189 = operand{ - class: AC_PREGIDX, elemEncoders: []elemEncoder{ - {encodePnN_58, enc_PNn}, - {encodeNoop, enc_NIL}, - {encodeI189, enc_i1}, - }, +var Pn_B__Zd = []operand{ + a_ARNG_Pn59v2_ArngBCheck, + a_ZREG_Zd_Noop, } -var a_PREGIDX_PnN_58_Noop_Imm2_810 = operand{ - class: AC_PREGIDX, elemEncoders: []elemEncoder{ - {encodePnN_58, enc_PNn}, - {encodeNoop, enc_NIL}, - {encodeImm2_810, enc_imm2}, - }, +var Pn_D__Zd_imm_ = []operand{ + a_ARNG_Pn59v2_ArngDCheck, + a_ZREGIDX_Zd_Noop_I3hI3l_1722_Doubleword, } -var a_PREGZM_Pg1013_MergePredCheck = operand{ - class: AC_PREGZM, elemEncoders: []elemEncoder{ - {encodePg1013, enc_Pg}, - {encodeMergePredCheck, enc_NIL}, - }, +var Pn_H__Zd_imm_ = []operand{ + a_ARNG_Pn59v2_ArngHCheck, + a_ZREGIDX_Zd_Noop_I1_1718_Halfword, } -var a_PREGZM_Pg1013_PredQualM1617 = operand{ - class: AC_PREGZM, elemEncoders: []elemEncoder{ - {encodePg1013, enc_Pg}, - {encodePredQualM1617, enc_M}, - }, +var Pn_S__Zd_imm_ = []operand{ + a_ARNG_Pn59v2_ArngSCheck, + a_ZREGIDX_Zd_Noop_I2_1719_Word, } -var a_PREGZM_Pg1013_ZeroPredCheck = operand{ - class: AC_PREGZM, elemEncoders: []elemEncoder{ - {encodePg1013, enc_Pg}, - {encodeZeroPredCheck, enc_NIL}, - }, +var Pn_T__Pd_T = []operand{ + a_ARNG_Pn59v2_SizeBHSD2224, + a_ARNG_Pd_SizeBHSD2224, } -var a_PREGZM_Pg1014_PredQualM45 = operand{ - class: AC_PREGZM, elemEncoders: []elemEncoder{ - {encodePg1014, enc_Pg}, - {encodePredQualM45, enc_M}, - }, +var Pn_T__Pg__Xd = []operand{ + a_ARNG_Pn59v2_SizeBHSD2224, + a_PREG_Pg1014_Noop, + a_SPZGREG_Noop_Rd05, } -var a_PREGZM_Pg1014_ZeroPredCheck = operand{ - class: AC_PREGZM, elemEncoders: []elemEncoder{ - {encodePg1014, enc_Pg}, - {encodeZeroPredCheck, enc_NIL}, - }, +var Rm__Rn = []operand{ + a_SPZGREG_Noop_Rm1621ZR, + a_SPZGREG_Noop_Rn510ZR, } -var a_PREGZM_Pg1620_MergePredCheck = operand{ - class: AC_PREGZM, elemEncoders: []elemEncoder{ - {encodePg1620, enc_Pg}, - {encodeMergePredCheck, enc_NIL}, - }, +var Rm__Rn__Pd_T = []operand{ + a_SPZGREG_Noop_Rm1621ZR, + a_SPZGREG_Noop_Rn510ZR, + a_ARNG_Pd_SizeBHSD2224, } -var a_PREGZM_Pg1620_ZeroPredCheck = operand{ - class: AC_PREGZM, elemEncoders: []elemEncoder{ - {encodePg1620, enc_Pg}, - {encodeZeroPredCheck, enc_NIL}, - }, +var Rm__Rn__Zd_T = []operand{ + a_SPZGREG_Noop_Rm1621ZR, + a_SPZGREG_Noop_Rn510ZR, + a_ARNG_Zd_SizeBHSD2224, } -var a_PREGZM_Pg59_ZeroPredCheck = operand{ - class: AC_PREGZM, elemEncoders: []elemEncoder{ - {encodePg59, enc_Pg}, - {encodeZeroPredCheck, enc_NIL}, - }, +var Rm__Zdn_T = []operand{ + a_SPZGREG_Noop_Rm510ZR, + a_ARNG_ZdnSrcDst_SizeBHSD2224, } -var a_PREG_Pg1013_Noop = operand{ - class: AC_PREG, elemEncoders: []elemEncoder{ - {encodePg1013, enc_Pg}, - {encodeNoop, enc_NIL}, - }, +var Rm__cimm__Zd_T = []operand{ + a_SPZGREG_Noop_Rm1621ZR, + a_IMM_Imm5Signed510Unique, + a_ARNG_Zd_SizeBHSD2224, } -var a_PREG_Pg1014_Noop = operand{ - class: AC_PREG, elemEncoders: []elemEncoder{ - {encodePg1014, enc_Pg}, - {encodeNoop, enc_NIL}, - }, +var RnSP__PgM__Zd_T = []operand{ + a_SPZGREG_Noop_Rn510SPV1, + a_PREGZM_Pg1013_MergePredCheck, + a_ARNG_Zd_SizeBHSD2224, } -var a_PREG_Pg59_Noop = operand{ - class: AC_PREG, elemEncoders: []elemEncoder{ - {encodePg59, enc_Pg}, - {encodeNoop, enc_NIL}, - }, +var RnSP__Zd_T = []operand{ + a_SPZGREG_Noop_Rn510SPV1, + a_ARNG_Zd_SizeBHSD2224, } -var a_PREG_Pv1013_Noop = operand{ - class: AC_PREG, elemEncoders: []elemEncoder{ - {encodePv1013, enc_Pv}, - {encodeNoop, enc_NIL}, - }, +var Vm__Zdn_T = []operand{ + a_VREG_Noop_Vm510, + a_ARNG_ZdnSrcDst_SizeBHSD2224, } -var a_PREG_Pv1014_Noop = operand{ - class: AC_PREG, elemEncoders: []elemEncoder{ - {encodePv1014, enc_Pv}, - {encodeNoop, enc_NIL}, - }, +var Vn__PgM__Zd_T = []operand{ + a_VREG_Noop_Vn510, + a_PREGZM_Pg1013_MergePredCheck, + a_ARNG_Zd_SizeBHSD2224, } -var a_PREG_Pv59_Noop = operand{ - class: AC_PREG, elemEncoders: []elemEncoder{ - {encodePv59, enc_Pv}, - {encodeNoop, enc_NIL}, - }, +var Wdn__Pm_T__Xdn = []operand{ + a_SPZGREG_Noop_Wdn05, + a_ARNG_Pm59v1_SizeBHSD2224, + a_SPZGREG_Noop_Xdn05, } -var a_REGLIST1_Zn510Table3_ArngBCheck = operand{ - class: AC_REGLIST1, elemEncoders: []elemEncoder{ - {encodeZn510Table3, enc_Zn}, - {encodeArngBCheck, enc_NIL}, - }, +var Xm__Xn__Pd_T = []operand{ + a_SPZGREG_Noop_Rm1621V1, + a_SPZGREG_Noop_Rn510, + a_ARNG_Pd_SizeBHSD2224, } -var a_REGLIST1_Zn510Table3_ArngHCheck = operand{ - class: AC_REGLIST1, elemEncoders: []elemEncoder{ - {encodeZn510Table3, enc_Zn}, - {encodeArngHCheck, enc_NIL}, - }, +var Xm__Xn___Pd1_T__Pd2_T_ = []operand{ + a_SPZGREG_Noop_Rm1621V1, + a_SPZGREG_Noop_Rn510, + a_REGLIST2_Pd14_SizeBHSD2224_Pd14Plus1_SizeBHSD2224, } -var a_REGLIST1_Zn510_SizeBHSD2224 = operand{ - class: AC_REGLIST1, elemEncoders: []elemEncoder{ - {encodeZn510, enc_Zn}, - {encodeSizeBHSD2224, enc_size}, - }, +var XnSP__Xm__LSL_c1___PgZ___Zt1_H__Zt2_H_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt1Check, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST2_Zt051_ArngHCheck_Zt052_ArngHCheck, } -var a_REGLIST2_Pd04_SizeBHSD2224_Pd04Plus1_SizeBHSD2224 = operand{ - class: AC_REGLIST2, elemEncoders: []elemEncoder{ - {encodePd04, enc_Pd}, - {encodeSizeBHSD2224, enc_size}, - {encodePd04Plus1, enc_Pd}, - {encodeSizeBHSD2224, enc_size}, - }, +var XnSP__Xm__LSL_c1___PgZ___Zt1_H__Zt2_H__Zt3_H_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt1Check, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST3_Zt051_ArngHCheck_Zt052_ArngHCheck_Zt053_ArngHCheck, } -var a_REGLIST2_Pd14_SizeBHSD2224_Pd14Plus1_SizeBHSD2224 = operand{ - class: AC_REGLIST2, elemEncoders: []elemEncoder{ - {encodePd14, enc_Pd}, - {encodeSizeBHSD2224, enc_size}, - {encodePd14Plus1, enc_Pd}, - {encodeSizeBHSD2224, enc_size}, - }, +var XnSP__Xm__LSL_c1___PgZ___Zt1_H__Zt2_H__Zt3_H__Zt4_H_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt1Check, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST4_Zt051_ArngHCheck_Zt052_ArngHCheck_Zt053_ArngHCheck_Zt054_ArngHCheck, } -var a_REGLIST2_Zn510MultiSrc1_ArngBCheck_Zn510MultiSrc2_ArngBCheck = operand{ - class: AC_REGLIST2, elemEncoders: []elemEncoder{ - {encodeZn510MultiSrc1, enc_Zn}, - {encodeArngBCheck, enc_NIL}, - {encodeZn510MultiSrc2, enc_Zn}, - {encodeArngBCheck, enc_NIL}, - }, +var XnSP__Xm__LSL_c1___PgZ___Zt_D_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt1Check, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST1_Zt05_ArngDCheck, } -var a_REGLIST2_Zn510MultiSrc1_SizeBHSD2224_Zn510MultiSrc2_SizeBHSD2224 = operand{ - class: AC_REGLIST2, elemEncoders: []elemEncoder{ - {encodeZn510MultiSrc1, enc_Zn}, - {encodeSizeBHSD2224, enc_size}, - {encodeZn510MultiSrc2, enc_Zn}, - {encodeSizeBHSD2224, enc_size}, - }, +var XnSP__Xm__LSL_c1___PgZ___Zt_D__V2 = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621XZR_Noop_ModLSLCheck_ModAmt1Check, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST1_Zt05_ArngDCheck, } -var a_REGLIST2_Zn510Table1_ArngBCheck_Zn510Table2_ArngBCheck = operand{ - class: AC_REGLIST2, elemEncoders: []elemEncoder{ - {encodeZn510Table1, enc_Zn}, - {encodeArngBCheck, enc_NIL}, - {encodeZn510Table2, enc_Zn}, - {encodeArngBCheck, enc_NIL}, - }, +var XnSP__Xm__LSL_c1___PgZ___Zt_H_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt1Check, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST1_Zt05_ArngHCheck, } -var a_REGLIST2_Zn510Table1_ArngHCheck_Zn510Table2_ArngHCheck = operand{ - class: AC_REGLIST2, elemEncoders: []elemEncoder{ - {encodeZn510Table1, enc_Zn}, - {encodeArngHCheck, enc_NIL}, - {encodeZn510Table2, enc_Zn}, - {encodeArngHCheck, enc_NIL}, - }, +var XnSP__Xm__LSL_c1___PgZ___Zt_H__V2 = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621XZR_Noop_ModLSLCheck_ModAmt1Check, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST1_Zt05_ArngHCheck, } -var a_SPZGREG_Noop_Rd05 = operand{ - class: AC_SPZGREG, elemEncoders: []elemEncoder{ - {encodeNoop, enc_NIL}, - {encodeRd05, enc_Rd}, - }, +var XnSP__Xm__LSL_c1___PgZ___Zt_S_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt1Check, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST1_Zt05_ArngSCheck, } -var a_SPZGREG_Noop_Rd05ZR = operand{ - class: AC_SPZGREG, elemEncoders: []elemEncoder{ - {encodeNoop, enc_NIL}, - {encodeRd05ZR, enc_Rd}, - }, +var XnSP__Xm__LSL_c1___PgZ___Zt_S__V2 = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621XZR_Noop_ModLSLCheck_ModAmt1Check, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST1_Zt05_ArngSCheck, } -var a_SPZGREG_Noop_Rdn05ZR = operand{ - class: AC_SPZGREG, elemEncoders: []elemEncoder{ - {encodeNoop, enc_NIL}, - {encodeRdn05ZR, enc_Rdn}, - }, +var XnSP__Xm__LSL_c1___Pg___Zt1_H__Zt2_H_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt1Check, + a_PREG_Pg1013_Noop, + a_REGLIST2_Zt051_ArngHCheck_Zt052_ArngHCheck, } -var a_SPZGREG_Noop_Rm1621 = operand{ - class: AC_SPZGREG, elemEncoders: []elemEncoder{ - {encodeNoop, enc_NIL}, - {encodeRm1621, enc_Rm}, - }, +var XnSP__Xm__LSL_c1___Pg___Zt1_H__Zt2_H__Zt3_H_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt1Check, + a_PREG_Pg1013_Noop, + a_REGLIST3_Zt051_ArngHCheck_Zt052_ArngHCheck_Zt053_ArngHCheck, } -var a_SPZGREG_Noop_Rm1621ZR = operand{ - class: AC_SPZGREG, elemEncoders: []elemEncoder{ - {encodeNoop, enc_NIL}, - {encodeRm1621ZR, enc_Rm}, - }, +var XnSP__Xm__LSL_c1___Pg___Zt1_H__Zt2_H__Zt3_H__Zt4_H_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt1Check, + a_PREG_Pg1013_Noop, + a_REGLIST4_Zt051_ArngHCheck_Zt052_ArngHCheck_Zt053_ArngHCheck_Zt054_ArngHCheck, } -var a_SPZGREG_Noop_Rm510ZR = operand{ - class: AC_SPZGREG, elemEncoders: []elemEncoder{ - {encodeNoop, enc_NIL}, - {encodeRm510ZR, enc_Rm}, - }, +var XnSP__Xm__LSL_c1___Pg___Zt_H_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt1Check, + a_PREG_Pg1013_Noop, + a_REGLIST1_Zt05_ArngHCheck, } -var a_SPZGREG_Noop_Rn510 = operand{ - class: AC_SPZGREG, elemEncoders: []elemEncoder{ - {encodeNoop, enc_NIL}, - {encodeRn510, enc_Rn}, - }, +var XnSP__Xm__LSL_c1___Pg___Zt_T_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt1Check, + a_PREG_Pg1013_Noop, + a_REGLIST1_Zt05_Size2123V2, } -var a_SPZGREG_Noop_Rn510SP = operand{ - class: AC_SPZGREG, elemEncoders: []elemEncoder{ - {encodeNoop, enc_NIL}, - {encodeRn510SP, enc_Rn}, - }, +var XnSP__Xm__LSL_c2___PgZ___Zt1_S__Zt2_S_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt2Check, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST2_Zt051_ArngSCheck_Zt052_ArngSCheck, } -var a_SPZGREG_Noop_Rn510ZR = operand{ - class: AC_SPZGREG, elemEncoders: []elemEncoder{ - {encodeNoop, enc_NIL}, - {encodeRn510ZR, enc_Rn}, - }, +var XnSP__Xm__LSL_c2___PgZ___Zt1_S__Zt2_S__Zt3_S_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt2Check, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST3_Zt051_ArngSCheck_Zt052_ArngSCheck_Zt053_ArngSCheck, } -var a_SPZGREG_Noop_Wdn05 = operand{ - class: AC_SPZGREG, elemEncoders: []elemEncoder{ - {encodeNoop, enc_NIL}, - {encodeWdn05, enc_Rdn}, - }, +var XnSP__Xm__LSL_c2___PgZ___Zt1_S__Zt2_S__Zt3_S__Zt4_S_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt2Check, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST4_Zt051_ArngSCheck_Zt052_ArngSCheck_Zt053_ArngSCheck_Zt054_ArngSCheck, } -var a_SPZGREG_Noop_Xdn05 = operand{ - class: AC_SPZGREG, elemEncoders: []elemEncoder{ - {encodeNoop, enc_NIL}, - {encodeXdn05, enc_Rdn}, - }, +var XnSP__Xm__LSL_c2___PgZ___Zt_D_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt2Check, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST1_Zt05_ArngDCheck, } -var a_SPZGREG_XCheck_Rd05_SPAllowed = operand{ - class: AC_SPZGREG, elemEncoders: []elemEncoder{ - {encodeXCheck, enc_NIL}, - {encodeRd05_SPAllowed, enc_Rd}, - }, +var XnSP__Xm__LSL_c2___PgZ___Zt_D__V2 = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621XZR_Noop_ModLSLCheck_ModAmt2Check, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST1_Zt05_ArngDCheck, } -var a_SPZGREG_XCheck_Rn1621_SPAllowed = operand{ - class: AC_SPZGREG, elemEncoders: []elemEncoder{ - {encodeXCheck, enc_NIL}, - {encodeRn1621_SPAllowed, enc_Rn}, - }, +var XnSP__Xm__LSL_c2___PgZ___Zt_S_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt2Check, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST1_Zt05_ArngSCheck, } -var a_VREG_Noop_Vd05 = operand{ - class: AC_VREG, elemEncoders: []elemEncoder{ - {encodeNoop, enc_NIL}, - {encodeVd05, enc_Vd}, - }, +var XnSP__Xm__LSL_c2___PgZ___Zt_S__V2 = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621XZR_Noop_ModLSLCheck_ModAmt2Check, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST1_Zt05_ArngSCheck, } -var a_VREG_Noop_Vd0564 = operand{ - class: AC_VREG, elemEncoders: []elemEncoder{ - {encodeNoop, enc_NIL}, - {encodeVd0564, enc_Vd}, - }, +var XnSP__Xm__LSL_c2___Pg___Zt1_S__Zt2_S_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt2Check, + a_PREG_Pg1013_Noop, + a_REGLIST2_Zt051_ArngSCheck_Zt052_ArngSCheck, } -var a_VREG_Noop_Vdn05 = operand{ - class: AC_VREG, elemEncoders: []elemEncoder{ - {encodeNoop, enc_NIL}, - {encodeVdn05, enc_Vdn}, - }, +var XnSP__Xm__LSL_c2___Pg___Zt1_S__Zt2_S__Zt3_S_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt2Check, + a_PREG_Pg1013_Noop, + a_REGLIST3_Zt051_ArngSCheck_Zt052_ArngSCheck_Zt053_ArngSCheck, } -var a_VREG_Noop_Vm510 = operand{ - class: AC_VREG, elemEncoders: []elemEncoder{ - {encodeNoop, enc_NIL}, - {encodeVm510, enc_Vm}, - }, +var XnSP__Xm__LSL_c2___Pg___Zt1_S__Zt2_S__Zt3_S__Zt4_S_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt2Check, + a_PREG_Pg1013_Noop, + a_REGLIST4_Zt051_ArngSCheck_Zt052_ArngSCheck_Zt053_ArngSCheck_Zt054_ArngSCheck, } -var a_VREG_Noop_Vn510 = operand{ - class: AC_VREG, elemEncoders: []elemEncoder{ - {encodeNoop, enc_NIL}, - {encodeVn510, enc_Vn}, - }, +var XnSP__Xm__LSL_c2___Pg___Zt_S_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt2Check, + a_PREG_Pg1013_Noop, + a_REGLIST1_Zt05_ArngSCheck, } -var a_ZREGIDX_Zd_Noop_I1_1718_Halfword = operand{ - class: AC_ZREGIDX, elemEncoders: []elemEncoder{ - {encodeZd, enc_Zd}, - {encodeNoop, enc_NIL}, - {encodeI1_1718_Halfword, enc_i1}, - }, +var XnSP__Xm__LSL_c3___PgZ___Zt1_D__Zt2_D_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt3Check, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST2_Zt051_ArngDCheck_Zt052_ArngDCheck, } -var a_ZREGIDX_Zd_Noop_I2_1719_Word = operand{ - class: AC_ZREGIDX, elemEncoders: []elemEncoder{ - {encodeZd, enc_Zd}, - {encodeNoop, enc_NIL}, - {encodeI2_1719_Word, enc_i2}, - }, +var XnSP__Xm__LSL_c3___PgZ___Zt1_D__Zt2_D__Zt3_D_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt3Check, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST3_Zt051_ArngDCheck_Zt052_ArngDCheck_Zt053_ArngDCheck, } -var a_ZREGIDX_Zd_Noop_I3hI3l_1722_Doubleword = operand{ - class: AC_ZREGIDX, elemEncoders: []elemEncoder{ - {encodeZd, enc_Zd}, - {encodeNoop, enc_NIL}, - {encodeI3hI3l_1722_Doubleword, enc_i3h_i3l}, - }, +var XnSP__Xm__LSL_c3___PgZ___Zt1_D__Zt2_D__Zt3_D__Zt4_D_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt3Check, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST4_Zt051_ArngDCheck_Zt052_ArngDCheck_Zt053_ArngDCheck_Zt054_ArngDCheck, } -var a_ZREGIDX_Zm1621V1_Noop_I12324 = operand{ - class: AC_ZREGIDX, elemEncoders: []elemEncoder{ - {encodeZm1621V1, enc_Zm}, - {encodeNoop, enc_NIL}, - {encodeI12324, enc_i1}, - }, +var XnSP__Xm__LSL_c3___PgZ___Zt_D_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt3Check, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST1_Zt05_ArngDCheck, } -var a_ZREGIDX_Zm1621V1_Noop_I12324B = operand{ - class: AC_ZREGIDX, elemEncoders: []elemEncoder{ - {encodeZm1621V1, enc_Zm}, - {encodeNoop, enc_NIL}, - {encodeI12324B, enc_i1}, - }, +var XnSP__Xm__LSL_c3___PgZ___Zt_D__V2 = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621XZR_Noop_ModLSLCheck_ModAmt3Check, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST1_Zt05_ArngDCheck, } -var a_ZREGIDX_Zm1621V1_Noop_I22224 = operand{ - class: AC_ZREGIDX, elemEncoders: []elemEncoder{ - {encodeZm1621V1, enc_Zm}, - {encodeNoop, enc_NIL}, - {encodeI22224, enc_i2}, - }, +var XnSP__Xm__LSL_c3___Pg___Zt1_D__Zt2_D_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt3Check, + a_PREG_Pg1013_Noop, + a_REGLIST2_Zt051_ArngDCheck_Zt052_ArngDCheck, } -var a_ZREGIDX_Zm1621V1_Noop_I22224HW = operand{ - class: AC_ZREGIDX, elemEncoders: []elemEncoder{ - {encodeZm1621V1, enc_Zm}, - {encodeNoop, enc_NIL}, - {encodeI22224HW, enc_i2}, - }, +var XnSP__Xm__LSL_c3___Pg___Zt1_D__Zt2_D__Zt3_D_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt3Check, + a_PREG_Pg1013_Noop, + a_REGLIST3_Zt051_ArngDCheck_Zt052_ArngDCheck_Zt053_ArngDCheck, } -var a_ZREGIDX_Zm1621V1_Noop_I3224I31213 = operand{ - class: AC_ZREGIDX, elemEncoders: []elemEncoder{ - {encodeZm1621V1, enc_Zm}, - {encodeNoop, enc_NIL}, - {encodeI3224I31213, enc_i3h_i3l}, - }, +var XnSP__Xm__LSL_c3___Pg___Zt1_D__Zt2_D__Zt3_D__Zt4_D_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt3Check, + a_PREG_Pg1013_Noop, + a_REGLIST4_Zt051_ArngDCheck_Zt052_ArngDCheck_Zt053_ArngDCheck_Zt054_ArngDCheck, } -var a_ZREGIDX_Zn510Src_Noop_I1_1718_Halfword = operand{ - class: AC_ZREGIDX, elemEncoders: []elemEncoder{ - {encodeZn510Src, enc_Zn}, - {encodeNoop, enc_NIL}, - {encodeI1_1718_Halfword, enc_i1}, - }, +var XnSP__Xm__LSL_c3___Pg___Zt_D_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt3Check, + a_PREG_Pg1013_Noop, + a_REGLIST1_Zt05_ArngDCheck, } -var a_ZREGIDX_Zn510Src_Noop_I2_1719_Word = operand{ - class: AC_ZREGIDX, elemEncoders: []elemEncoder{ - {encodeZn510Src, enc_Zn}, - {encodeNoop, enc_NIL}, - {encodeI2_1719_Word, enc_i2}, - }, +var XnSP__Xm__LSL_c4___PgZ___Zt1_Q__Zt2_Q_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt4Check, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST2_Zt051_ArngQCheck_Zt052_ArngQCheck, } -var a_ZREGIDX_Zn510Src_Noop_I3hI3l_1722_Doubleword = operand{ - class: AC_ZREGIDX, elemEncoders: []elemEncoder{ - {encodeZn510Src, enc_Zn}, - {encodeNoop, enc_NIL}, - {encodeI3hI3l_1722_Doubleword, enc_i3h_i3l}, - }, +var XnSP__Xm__LSL_c4___PgZ___Zt1_Q__Zt2_Q__Zt3_Q_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt4Check, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST3_Zt051_ArngQCheck_Zt052_ArngQCheck_Zt053_ArngQCheck, } -var a_ZREG_Zd_Noop = operand{ - class: AC_ZREG, elemEncoders: []elemEncoder{ - {encodeZd, enc_Zd}, - {encodeNoop, enc_NIL}, - }, +var XnSP__Xm__LSL_c4___PgZ___Zt1_Q__Zt2_Q__Zt3_Q__Zt4_Q_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt4Check, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST4_Zt051_ArngQCheck_Zt052_ArngQCheck_Zt053_ArngQCheck_Zt054_ArngQCheck, } -var a_ZREG_Zm1621V1_Noop = operand{ - class: AC_ZREG, elemEncoders: []elemEncoder{ - {encodeZm1621V1, enc_Zm}, - {encodeNoop, enc_NIL}, - }, +var XnSP__Xm__LSL_c4___Pg___Zt1_Q__Zt2_Q_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt4Check, + a_PREG_Pg1013_Noop, + a_REGLIST2_Zt051_ArngQCheck_Zt052_ArngQCheck, } -var a_ZREG_Zn510Src_Noop = operand{ - class: AC_ZREG, elemEncoders: []elemEncoder{ - {encodeZn510Src, enc_Zn}, - {encodeNoop, enc_NIL}, - }, +var XnSP__Xm__LSL_c4___Pg___Zt1_Q__Zt2_Q__Zt3_Q_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt4Check, + a_PREG_Pg1013_Noop, + a_REGLIST3_Zt051_ArngQCheck_Zt052_ArngQCheck_Zt053_ArngQCheck, } -var PNd_T = []operand{ - a_ARNG_PNd_SizeBHSD2224, +var XnSP__Xm__LSL_c4___Pg___Zt1_Q__Zt2_Q__Zt3_Q__Zt4_Q_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_ModLSLCheck_ModAmt4Check, + a_PREG_Pg1013_Noop, + a_REGLIST4_Zt051_ArngQCheck_Zt052_ArngQCheck_Zt053_ArngQCheck_Zt054_ArngQCheck, } -var PNn_imm___Pd_T = []operand{ - a_PREGIDX_PnN_58_Noop_Imm2_810, - a_ARNG_Pd_SizeBHSD2224, +var XnSP__Xm___PgZ___Zt1_B__Zt2_B_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_NoModCheck_NoAmtCheck, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST2_Zt051_ArngBCheck_Zt052_ArngBCheck, } -var PNn_imm____Pd1_T__Pd2_T_ = []operand{ - a_PREGIDX_PnN_58_Noop_I189, - a_REGLIST2_Pd04_SizeBHSD2224_Pd04Plus1_SizeBHSD2224, +var XnSP__Xm___PgZ___Zt1_B__Zt2_B__Zt3_B_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_NoModCheck_NoAmtCheck, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST3_Zt051_ArngBCheck_Zt052_ArngBCheck_Zt053_ArngBCheck, } -var Pd_B = []operand{ - a_ARNG_Pd_ArngBCheck, +var XnSP__Xm___PgZ___Zt1_B__Zt2_B__Zt3_B__Zt4_B_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_NoModCheck_NoAmtCheck, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST4_Zt051_ArngBCheck_Zt052_ArngBCheck_Zt053_ArngBCheck_Zt054_ArngBCheck, } -var Pdm_B__Pn_B__PgZ__Pdm_B = []operand{ - a_ARNG_PdmDest_ArngBCheck, - a_ARNG_Pn59_ArngBCheck, - a_PREGZM_Pg1014_ZeroPredCheck, - a_ARNG_PdmDest_ArngBCheck, +var XnSP__Xm___PgZ___Zt_B_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_NoModCheck_NoAmtCheck, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST1_Zt05_ArngBCheck, } -var Pdn_B__Pg__Pdn_B = []operand{ - a_ARNG_PdnSrcDst_ArngBCheck, - a_PREG_Pg59_Noop, - a_ARNG_PdnSrcDst_ArngBCheck, +var XnSP__Xm___PgZ___Zt_B__V2 = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621XZR_Noop_NoModCheck_NoAmtCheck, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST1_Zt05_ArngBCheck, } -var Pdn_T__Pv__Pdn_T = []operand{ - a_ARNG_PdnDest_SizeBHSD2224, - a_PREG_Pv59_Noop, - a_ARNG_PdnDest_SizeBHSD2224, +var XnSP__Xm___PgZ___Zt_D_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_NoModCheck_NoAmtCheck, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST1_Zt05_ArngDCheck, } -var PgZ__Pd_B = []operand{ - a_PREGZM_Pg59_ZeroPredCheck, - a_ARNG_Pd_ArngBCheck, +var XnSP__Xm___PgZ___Zt_D__V2 = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621XZR_Noop_NoModCheck_NoAmtCheck, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST1_Zt05_ArngDCheck, } -var Pm_B__Pn_B__PgZ__Pd_B = []operand{ - a_ARNG_Pm1620_ArngBCheck, - a_ARNG_Pn59_ArngBCheck, - a_PREGZM_Pg1014_ZeroPredCheck, - a_ARNG_Pd_ArngBCheck, +var XnSP__Xm___PgZ___Zt_H_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_NoModCheck_NoAmtCheck, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST1_Zt05_ArngHCheck, } -var Pm_B__Pn_B__Pg__Pd_B = []operand{ - a_ARNG_Pm1620_ArngBCheck, - a_ARNG_Pn59_ArngBCheck, - a_PREG_Pg1014_Noop, - a_ARNG_Pd_ArngBCheck, +var XnSP__Xm___PgZ___Zt_H__V2 = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621XZR_Noop_NoModCheck_NoAmtCheck, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST1_Zt05_ArngHCheck, } -var Pm_T__Pn_T__Pd_T = []operand{ - a_ARNG_Pm1620_SizeBHSD2224, - a_ARNG_Pn59_SizeBHSD2224, - a_ARNG_Pd_SizeBHSD2224, +var XnSP__Xm___PgZ___Zt_S_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_NoModCheck_NoAmtCheck, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST1_Zt05_ArngSCheck, } -var Pm_T__Wdn = []operand{ - a_ARNG_Pm59v1_SizeBHSD2224, - a_SPZGREG_Noop_Wdn05, +var XnSP__Xm___PgZ___Zt_S__V2 = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621XZR_Noop_NoModCheck_NoAmtCheck, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST1_Zt05_ArngSCheck, } -var Pm_T__Xdn = []operand{ - a_ARNG_Pm59v1_SizeBHSD2224, - a_SPZGREG_Noop_Xdn05, +var XnSP__Xm___Pg___Zt1_B__Zt2_B_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_NoModCheck_NoAmtCheck, + a_PREG_Pg1013_Noop, + a_REGLIST2_Zt051_ArngBCheck_Zt052_ArngBCheck, } -var Pm_T__Zdn_T = []operand{ - a_ARNG_Pm59v1_SizeHSD2224, - a_ARNG_ZdnSrcDst_SizeHSD2224, +var XnSP__Xm___Pg___Zt1_B__Zt2_B__Zt3_B_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_NoModCheck_NoAmtCheck, + a_PREG_Pg1013_Noop, + a_REGLIST3_Zt051_ArngBCheck_Zt052_ArngBCheck_Zt053_ArngBCheck, } -var Pn_B = []operand{ - a_ARNG_Pn59v2_ArngBCheck, +var XnSP__Xm___Pg___Zt1_B__Zt2_B__Zt3_B__Zt4_B_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_NoModCheck_NoAmtCheck, + a_PREG_Pg1013_Noop, + a_REGLIST4_Zt051_ArngBCheck_Zt052_ArngBCheck_Zt053_ArngBCheck_Zt054_ArngBCheck, } -var Pn_B__Pd_H = []operand{ - a_ARNG_Pn59v2_ArngBCheck, - a_ARNG_Pd_ArngHCheck, +var XnSP__Xm___Pg___Zt_B_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_NoModCheck_NoAmtCheck, + a_PREG_Pg1013_Noop, + a_REGLIST1_Zt05_ArngBCheck, } -var Pn_B__Pg = []operand{ - a_ARNG_Pn59v2_ArngBCheck, - a_PREG_Pg1014_Noop, +var XnSP__Xm___Pg___Zt_T_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Rm1621V2_Noop_NoModCheck_NoAmtCheck, + a_PREG_Pg1013_Noop, + a_REGLIST1_Zt05_Size2123V1, } -var Pn_B__PgZM__Pd_B = []operand{ - a_ARNG_Pn59v2_ArngBCheck, - a_PREGZM_Pg1014_PredQualM45, - a_ARNG_Pd_ArngBCheck, +var XnSP__Zm_D__LSL_c1___PgZ___Zt_D_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_ModLSLCheck_ModAmt1Check, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST1_Zt05_ArngDCheck, } -var Pn_B__PgZ__Pd_B = []operand{ - a_ARNG_Pn59v2_ArngBCheck, - a_PREGZM_Pg1014_ZeroPredCheck, - a_ARNG_Pd_ArngBCheck, +var XnSP__Zm_D__LSL_c1___Pg___Zt_D_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_ModLSLCheck_ModAmt1Check, + a_PREG_Pg1013_Noop, + a_REGLIST1_Zt05_ArngDCheck, } -var Pn_B__Zd = []operand{ - a_ARNG_Pn59v2_ArngBCheck, - a_ZREG_Zd_Noop, +var XnSP__Zm_D__LSL_c2___PgZ___Zt_D_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_ModLSLCheck_ModAmt2Check, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST1_Zt05_ArngDCheck, } -var Pn_D__Zd_imm_ = []operand{ - a_ARNG_Pn59v2_ArngDCheck, - a_ZREGIDX_Zd_Noop_I3hI3l_1722_Doubleword, +var XnSP__Zm_D__LSL_c2___Pg___Zt_D_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_ModLSLCheck_ModAmt2Check, + a_PREG_Pg1013_Noop, + a_REGLIST1_Zt05_ArngDCheck, } -var Pn_H__Zd_imm_ = []operand{ - a_ARNG_Pn59v2_ArngHCheck, - a_ZREGIDX_Zd_Noop_I1_1718_Halfword, +var XnSP__Zm_D__LSL_c3___PgZ___Zt_D_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_ModLSLCheck_ModAmt3Check, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST1_Zt05_ArngDCheck, } -var Pn_S__Zd_imm_ = []operand{ - a_ARNG_Pn59v2_ArngSCheck, - a_ZREGIDX_Zd_Noop_I2_1719_Word, +var XnSP__Zm_D__LSL_c3___Pg___Zt_D_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_ModLSLCheck_ModAmt3Check, + a_PREG_Pg1013_Noop, + a_REGLIST1_Zt05_ArngDCheck, } -var Pn_T__Pd_T = []operand{ - a_ARNG_Pn59v2_SizeBHSD2224, - a_ARNG_Pd_SizeBHSD2224, +var XnSP__Zm_D___PgZ___Zt_D_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_NoModCheck_NoAmtCheck, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST1_Zt05_ArngDCheck, } -var Pn_T__Pg__Xd = []operand{ - a_ARNG_Pn59v2_SizeBHSD2224, - a_PREG_Pg1014_Noop, - a_SPZGREG_Noop_Rd05, +var XnSP__Zm_D___Pg___Zt_D_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_NoModCheck_NoAmtCheck, + a_PREG_Pg1013_Noop, + a_REGLIST1_Zt05_ArngDCheck, } -var Rm__Rn = []operand{ - a_SPZGREG_Noop_Rm1621ZR, - a_SPZGREG_Noop_Rn510ZR, +var XnSP__Zm_D__mod___PgZ___Zt_D_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_Xs2223_NoAmtCheck, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST1_Zt05_ArngDCheck, } -var Rm__Rn__Pd_T = []operand{ - a_SPZGREG_Noop_Rm1621ZR, - a_SPZGREG_Noop_Rn510ZR, - a_ARNG_Pd_SizeBHSD2224, +var XnSP__Zm_D__mod___Pg___Zt_D_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_Xs1415_NoAmtCheck, + a_PREG_Pg1013_Noop, + a_REGLIST1_Zt05_ArngDCheck, } -var Rm__Rn__Zd_T = []operand{ - a_SPZGREG_Noop_Rm1621ZR, - a_SPZGREG_Noop_Rn510ZR, - a_ARNG_Zd_SizeBHSD2224, +var XnSP__Zm_D__mod_c1___PgZ___Zt_D_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_Xs2223_ModAmt1Check, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST1_Zt05_ArngDCheck, } -var Rm__Zdn_T = []operand{ - a_SPZGREG_Noop_Rm510ZR, - a_ARNG_ZdnSrcDst_SizeBHSD2224, +var XnSP__Zm_D__mod_c1___Pg___Zt_D_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_Xs1415_ModAmt1Check, + a_PREG_Pg1013_Noop, + a_REGLIST1_Zt05_ArngDCheck, } -var Rm__cimm__Zd_T = []operand{ - a_SPZGREG_Noop_Rm1621ZR, - a_IMM_Imm5Signed510Unique, - a_ARNG_Zd_SizeBHSD2224, +var XnSP__Zm_D__mod_c2___PgZ___Zt_D_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_Xs2223_ModAmt2Check, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST1_Zt05_ArngDCheck, } -var RnSP__PgM__Zd_T = []operand{ - a_SPZGREG_Noop_Rn510SP, - a_PREGZM_Pg1013_MergePredCheck, - a_ARNG_Zd_SizeBHSD2224, +var XnSP__Zm_D__mod_c2___Pg___Zt_D_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_Xs1415_ModAmt2Check, + a_PREG_Pg1013_Noop, + a_REGLIST1_Zt05_ArngDCheck, } -var RnSP__Zd_T = []operand{ - a_SPZGREG_Noop_Rn510SP, - a_ARNG_Zd_SizeBHSD2224, +var XnSP__Zm_D__mod_c3___PgZ___Zt_D_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_Xs2223_ModAmt3Check, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST1_Zt05_ArngDCheck, } -var Vm__Zdn_T = []operand{ - a_VREG_Noop_Vm510, - a_ARNG_ZdnSrcDst_SizeBHSD2224, +var XnSP__Zm_D__mod_c3___Pg___Zt_D_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngDCheck_Xs1415_ModAmt3Check, + a_PREG_Pg1013_Noop, + a_REGLIST1_Zt05_ArngDCheck, } -var Vn__PgM__Zd_T = []operand{ - a_VREG_Noop_Vn510, - a_PREGZM_Pg1013_MergePredCheck, - a_ARNG_Zd_SizeBHSD2224, +var XnSP__Zm_S__mod___PgZ___Zt_S_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngSCheck_Xs2223_NoAmtCheck, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST1_Zt05_ArngSCheck, } -var Wdn__Pm_T__Xdn = []operand{ - a_SPZGREG_Noop_Wdn05, - a_ARNG_Pm59v1_SizeBHSD2224, - a_SPZGREG_Noop_Xdn05, +var XnSP__Zm_S__mod___Pg___Zt_S_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngSCheck_Xs1415_NoAmtCheck, + a_PREG_Pg1013_Noop, + a_REGLIST1_Zt05_ArngSCheck, } -var Xm__Xn__Pd_T = []operand{ - a_SPZGREG_Noop_Rm1621, - a_SPZGREG_Noop_Rn510, - a_ARNG_Pd_SizeBHSD2224, +var XnSP__Zm_S__mod_c1___PgZ___Zt_S_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngSCheck_Xs2223_ModAmt1Check, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST1_Zt05_ArngSCheck, } -var Xm__Xn___Pd1_T__Pd2_T_ = []operand{ - a_SPZGREG_Noop_Rm1621, - a_SPZGREG_Noop_Rn510, - a_REGLIST2_Pd14_SizeBHSD2224_Pd14Plus1_SizeBHSD2224, +var XnSP__Zm_S__mod_c1___Pg___Zt_S_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngSCheck_Xs1415_ModAmt1Check, + a_PREG_Pg1013_Noop, + a_REGLIST1_Zt05_ArngSCheck, +} + +var XnSP__Zm_S__mod_c2___PgZ___Zt_S_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngSCheck_Xs2223_ModAmt2Check, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST1_Zt05_ArngSCheck, +} + +var XnSP__Zm_S__mod_c2___Pg___Zt_S_ = []operand{ + a_MEMEXT_Rn510SPV2_Noop_Zm1621V3_ArngSCheck_Xs1415_ModAmt2Check, + a_PREG_Pg1013_Noop, + a_REGLIST1_Zt05_ArngSCheck, } var Za_D__Zm_D__Zdn_D = []operand{ @@ -9422,55 +11777,55 @@ var Zm_B__Zdn_B__Zdn_B = []operand{ var Zm_B__Zn_B__Zd_B = []operand{ a_ARNG_Zm1621V2_ArngBCheck, - a_ARNG_Zn510_ArngBCheck, + a_ARNG_Zn510V1_ArngBCheck, a_ARNG_Zd_ArngBCheck, } var Zm_B__Zn_B__Zda_H = []operand{ a_ARNG_Zm1621V2_ArngBCheck, - a_ARNG_Zn510_ArngBCheck, + a_ARNG_Zn510V1_ArngBCheck, a_ARNG_Zda3RdSrcDst_ArngHCheck, } var Zm_B__Zn_B__Zda_S = []operand{ a_ARNG_Zm1621V2_ArngBCheck, - a_ARNG_Zn510_ArngBCheck, + a_ARNG_Zn510V1_ArngBCheck, a_ARNG_Zda3RdSrcDst_ArngSCheck, } var Zm_B_imm___Zn_B__Zda_H__1 = []operand{ a_ARNGIDX_Zm_1619_Range0_7V2_ArngBCheck_I4hI4l_1019, - a_ARNG_Zn510_ArngBCheck, + a_ARNG_Zn510V1_ArngBCheck, a_ARNG_Zda3RdSrcDst_ArngHCheck, } var Zm_B_imm___Zn_B__Zda_H__2 = []operand{ a_ARNGIDX_Zm_1619_Range0_7V2_ArngBCheck_I3hI3l_1923_8To16Bit, - a_ARNG_Zn510_ArngBCheck, + a_ARNG_Zn510V1_ArngBCheck, a_ARNG_Zda3RdSrcDst_ArngHCheck, } var Zm_B_imm___Zn_B__Zda_H__3 = []operand{ a_ARNGIDX_Zm_1619_Range0_7V2_ArngBCheck_I3hI3l_1119_Pair8Bit, - a_ARNG_Zn510_ArngBCheck, + a_ARNG_Zn510V1_ArngBCheck, a_ARNG_Zda3RdSrcDst_ArngHCheck, } var Zm_B_imm___Zn_B__Zda_S__1 = []operand{ a_ARNGIDX_Zm_1619_Range0_7V2_ArngBCheck_I4hI4l_1019, - a_ARNG_Zn510_ArngBCheck, + a_ARNG_Zn510V1_ArngBCheck, a_ARNG_Zda3RdSrcDst_ArngSCheck, } var Zm_B_imm___Zn_B__Zda_S__2 = []operand{ a_ARNGIDX_Zm_1619_Range0_7V2_ArngBCheck_I2_1921_8BitGroup, - a_ARNG_Zn510_ArngBCheck, + a_ARNG_Zn510V1_ArngBCheck, a_ARNG_Zda3RdSrcDst_ArngSCheck, } var Zm_B_imm___Zn_B__Zda_S__3 = []operand{ a_ARNGIDX_Zm1619_8To32Bit_ArngBCheck_I2_1921_8To32Bit, - a_ARNG_Zn510_ArngBCheck, + a_ARNG_Zn510V1_ArngBCheck, a_ARNG_Zda3RdSrcDst_ArngSCheck, } @@ -9490,56 +11845,56 @@ var Zm_D__Zdn_T__PgM__Zdn_T = []operand{ var Zm_D__Zn_D__Zd_D = []operand{ a_ARNG_Zm1621V2_ArngDCheck, - a_ARNG_Zn510_ArngDCheck, + a_ARNG_Zn510V1_ArngDCheck, a_ARNG_Zd_ArngDCheck, } var Zm_D__Zn_D__Zd_Q = []operand{ a_ARNG_Zm1621V2_ArngDCheck, - a_ARNG_Zn510_ArngDCheck, + a_ARNG_Zn510V1_ArngDCheck, a_ARNG_Zd_ArngQCheck, } var Zm_D__Zn_D__Zda_D = []operand{ a_ARNG_Zm1621V2_ArngDCheck, - a_ARNG_Zn510_ArngDCheck, + a_ARNG_Zn510V1_ArngDCheck, a_ARNG_Zda3RdSrcDst_ArngDCheck, } var Zm_D__Zn_T__PgZ__Pd_T = []operand{ a_ARNG_Zm1621V2_ArngDCheck, - a_ARNG_Zn510_SizeBHS2224, + a_ARNG_Zn510V1_SizeBHS2224, a_PREGZM_Pg1013_ZeroPredCheck, a_ARNG_Pd_SizeBHS2224, } var Zm_D__Zn_T__Zd_T = []operand{ a_ARNG_Zm1621V2_ArngDCheck, - a_ARNG_Zn510_SizeBHS2224, + a_ARNG_Zn510V1_SizeBHS2224, a_ARNG_Zd_SizeBHS2224, } var Zm_D_imm___Zn_D__Zd_D__1 = []operand{ a_ARNGIDX_Zm1620_64Bit_ArngDCheck_I1_2021_64Bit, - a_ARNG_Zn510_ArngDCheck, + a_ARNG_Zn510V1_ArngDCheck, a_ARNG_Zd_ArngDCheck, } var Zm_D_imm___Zn_D__Zd_D__2 = []operand{ a_ARNGIDX_Zm1620_DoublePrecision_ArngDCheck_I1_2021_DoublePrecision, - a_ARNG_Zn510_ArngDCheck, + a_ARNG_Zn510V1_ArngDCheck, a_ARNG_Zd_ArngDCheck, } var Zm_D_imm___Zn_D__Zda_D__1 = []operand{ a_ARNGIDX_Zm1620_64Bit_ArngDCheck_I1_2021_64Bit, - a_ARNG_Zn510_ArngDCheck, + a_ARNG_Zn510V1_ArngDCheck, a_ARNG_Zda3RdSrcDst_ArngDCheck, } var Zm_D_imm___Zn_D__Zda_D__2 = []operand{ a_ARNGIDX_Zm1620_DoublePrecision_ArngDCheck_I1_2021_DoublePrecision, - a_ARNG_Zn510_ArngDCheck, + a_ARNG_Zn510V1_ArngDCheck, a_ARNG_Zda3RdSrcDst_ArngDCheck, } @@ -9552,104 +11907,104 @@ var Zm_H__Zdn_H__PgM__Zdn_H = []operand{ var Zm_H__Zn_H__PgM__Zda_H = []operand{ a_ARNG_Zm1621V2_ArngHCheck, - a_ARNG_Zn510_ArngHCheck, + a_ARNG_Zn510V1_ArngHCheck, a_PREGZM_Pg1013_MergePredCheck, a_ARNG_Zda3RdSrcDst_ArngHCheck, } var Zm_H__Zn_H__Zd_H = []operand{ a_ARNG_Zm1621V2_ArngHCheck, - a_ARNG_Zn510_ArngHCheck, + a_ARNG_Zn510V1_ArngHCheck, a_ARNG_Zd_ArngHCheck, } var Zm_H__Zn_H__Zda_H = []operand{ a_ARNG_Zm1621V2_ArngHCheck, - a_ARNG_Zn510_ArngHCheck, + a_ARNG_Zn510V1_ArngHCheck, a_ARNG_Zda3RdSrcDst_ArngHCheck, } var Zm_H__Zn_H__Zda_S = []operand{ a_ARNG_Zm1621V2_ArngHCheck, - a_ARNG_Zn510_ArngHCheck, + a_ARNG_Zn510V1_ArngHCheck, a_ARNG_Zda3RdSrcDst_ArngSCheck, } var Zm_H_imm___Zn_H__Zd_H__1 = []operand{ a_ARNGIDX_Zm1619_16Bit32Bit_ArngHCheck_I3hI3l_1923_16Bit, - a_ARNG_Zn510_ArngHCheck, + a_ARNG_Zn510V1_ArngHCheck, a_ARNG_Zd_ArngHCheck, } var Zm_H_imm___Zn_H__Zd_H__2 = []operand{ a_ARNGIDX_Zm_1619_Range0_7V2_ArngHCheck_I3hI3l_1922, - a_ARNG_Zn510_ArngHCheck, + a_ARNG_Zn510V1_ArngHCheck, a_ARNG_Zd_ArngHCheck, } var Zm_H_imm___Zn_H__Zd_H__3 = []operand{ a_ARNGIDX_Zm1619_HalfSinglePrecision_ArngHCheck_I3hI3l_1923_HalfPrecision, - a_ARNG_Zn510_ArngHCheck, + a_ARNG_Zn510V1_ArngHCheck, a_ARNG_Zd_ArngHCheck, } var Zm_H_imm___Zn_H__Zd_S = []operand{ a_ARNGIDX_Zm1619_32Bit_ArngHCheck_I3hI3l_1119_32Bit, - a_ARNG_Zn510_ArngHCheck, + a_ARNG_Zn510V1_ArngHCheck, a_ARNG_Zd_ArngSCheck, } var Zm_H_imm___Zn_H__Zda_D = []operand{ a_ARNGIDX_Zm1620_16To64Bit_ArngHCheck_I1_2021_16To64Bit, - a_ARNG_Zn510_ArngHCheck, + a_ARNG_Zn510V1_ArngHCheck, a_ARNG_Zda3RdSrcDst_ArngDCheck, } var Zm_H_imm___Zn_H__Zda_H__1 = []operand{ a_ARNGIDX_Zm1619_16Bit32Bit_ArngHCheck_I3hI3l_1923_16Bit, - a_ARNG_Zn510_ArngHCheck, + a_ARNG_Zn510V1_ArngHCheck, a_ARNG_Zda3RdSrcDst_ArngHCheck, } var Zm_H_imm___Zn_H__Zda_H__2 = []operand{ a_ARNGIDX_Zm_1619_Range0_7V2_ArngHCheck_I3hI3l_1922, - a_ARNG_Zn510_ArngHCheck, + a_ARNG_Zn510V1_ArngHCheck, a_ARNG_Zda3RdSrcDst_ArngHCheck, } var Zm_H_imm___Zn_H__Zda_H__3 = []operand{ a_ARNGIDX_Zm1619_HalfSinglePrecision_ArngHCheck_I3hI3l_1923_HalfPrecision, - a_ARNG_Zn510_ArngHCheck, + a_ARNG_Zn510V1_ArngHCheck, a_ARNG_Zda3RdSrcDst_ArngHCheck, } var Zm_H_imm___Zn_H__Zda_S__1 = []operand{ a_ARNGIDX_Zm1619_32Bit_ArngHCheck_I3hI3l_1119_32Bit, - a_ARNG_Zn510_ArngHCheck, + a_ARNG_Zn510V1_ArngHCheck, a_ARNG_Zda3RdSrcDst_ArngSCheck, } var Zm_H_imm___Zn_H__Zda_S__2 = []operand{ a_ARNGIDX_Zm_1619_Range0_7V2_ArngHCheck_I3hI3l_1119, - a_ARNG_Zn510_ArngHCheck, + a_ARNG_Zn510V1_ArngHCheck, a_ARNG_Zda3RdSrcDst_ArngSCheck, } var Zm_H_imm___Zn_H__Zda_S__3 = []operand{ a_ARNGIDX_Zm_1619_Range0_7V2_ArngHCheck_I2_1921_Pair16Bit, - a_ARNG_Zn510_ArngHCheck, + a_ARNG_Zn510V1_ArngHCheck, a_ARNG_Zda3RdSrcDst_ArngSCheck, } var Zm_H_imm___Zn_H__Zda_S__4 = []operand{ a_ARNGIDX_Zm_1619_Range0_7V2_ArngHCheck_I2_1921_16To32Bit, - a_ARNG_Zn510_ArngHCheck, + a_ARNG_Zn510V1_ArngHCheck, a_ARNG_Zda3RdSrcDst_ArngSCheck, } var Zm_Q__Zn_Q__Zd_Q = []operand{ a_ARNG_Zm1621V2_ArngQCheck, - a_ARNG_Zn510_ArngQCheck, + a_ARNG_Zn510V1_ArngQCheck, a_ARNG_Zd_ArngQCheck, } @@ -9661,49 +12016,49 @@ var Zm_S__Zdn_S__Zdn_S = []operand{ var Zm_S__Zn_S__Zd_S = []operand{ a_ARNG_Zm1621V2_ArngSCheck, - a_ARNG_Zn510_ArngSCheck, + a_ARNG_Zn510V1_ArngSCheck, a_ARNG_Zd_ArngSCheck, } var Zm_S__Zn_S__Zda_S = []operand{ a_ARNG_Zm1621V2_ArngSCheck, - a_ARNG_Zn510_ArngSCheck, + a_ARNG_Zn510V1_ArngSCheck, a_ARNG_Zda3RdSrcDst_ArngSCheck, } var Zm_S_imm___Zn_S__Zd_D = []operand{ a_ARNGIDX_Zm1620_64Bit_ArngSCheck_I2hI2l_1120_64Bit, - a_ARNG_Zn510_ArngSCheck, + a_ARNG_Zn510V1_ArngSCheck, a_ARNG_Zd_ArngDCheck, } var Zm_S_imm___Zn_S__Zd_S__1 = []operand{ a_ARNGIDX_Zm1619_16Bit32Bit_ArngSCheck_I2_1921_32Bit, - a_ARNG_Zn510_ArngSCheck, + a_ARNG_Zn510V1_ArngSCheck, a_ARNG_Zd_ArngSCheck, } var Zm_S_imm___Zn_S__Zd_S__2 = []operand{ a_ARNGIDX_Zm1619_HalfSinglePrecision_ArngSCheck_I2_1921_SinglePrecision, - a_ARNG_Zn510_ArngSCheck, + a_ARNG_Zn510V1_ArngSCheck, a_ARNG_Zd_ArngSCheck, } var Zm_S_imm___Zn_S__Zda_D = []operand{ a_ARNGIDX_Zm1620_64Bit_ArngSCheck_I2hI2l_1120_64Bit, - a_ARNG_Zn510_ArngSCheck, + a_ARNG_Zn510V1_ArngSCheck, a_ARNG_Zda3RdSrcDst_ArngDCheck, } var Zm_S_imm___Zn_S__Zda_S__1 = []operand{ a_ARNGIDX_Zm1619_16Bit32Bit_ArngSCheck_I2_1921_32Bit, - a_ARNG_Zn510_ArngSCheck, + a_ARNG_Zn510V1_ArngSCheck, a_ARNG_Zda3RdSrcDst_ArngSCheck, } var Zm_S_imm___Zn_S__Zda_S__2 = []operand{ a_ARNGIDX_Zm1619_HalfSinglePrecision_ArngSCheck_I2_1921_SinglePrecision, - a_ARNG_Zn510_ArngSCheck, + a_ARNG_Zn510V1_ArngSCheck, a_ARNG_Zda3RdSrcDst_ArngSCheck, } @@ -9772,122 +12127,122 @@ var Zm_T__Zdn_T__Pv__Zdn_T = []operand{ var Zm_T__Zn_T__PgM__Zda_T__1 = []operand{ a_ARNG_Zm1621V2_SizeHSD2224No00, - a_ARNG_Zn510_SizeHSD2224No00, + a_ARNG_Zn510V1_SizeHSD2224No00, a_PREGZM_Pg1013_MergePredCheck, a_ARNG_Zda3RdSrcDst_SizeHSD2224No00, } var Zm_T__Zn_T__PgM__Zda_T__2 = []operand{ a_ARNG_Zm1621V2_SizeBHSD2224, - a_ARNG_Zn510_SizeBHSD2224, + a_ARNG_Zn510V1_SizeBHSD2224, a_PREGZM_Pg1013_MergePredCheck, a_ARNG_Zda3RdSrcDst_SizeBHSD2224, } var Zm_T__Zn_T__PgZ__Pd_T__1 = []operand{ a_ARNG_Zm1621V2_SizeHSD2224, - a_ARNG_Zn510_SizeHSD2224, + a_ARNG_Zn510V1_SizeHSD2224, a_PREGZM_Pg1013_ZeroPredCheck, a_ARNG_Pd_SizeHSD2224, } var Zm_T__Zn_T__PgZ__Pd_T__2 = []operand{ a_ARNG_Zm1621V2_SizeBHSD2224, - a_ARNG_Zn510_SizeBHSD2224, + a_ARNG_Zn510V1_SizeBHSD2224, a_PREGZM_Pg1013_ZeroPredCheck, a_ARNG_Pd_SizeBHSD2224, } var Zm_T__Zn_T__PgZ__Pd_T__3 = []operand{ a_ARNG_Zm1621V2_Size0BH2223, - a_ARNG_Zn510_Size0BH2223, + a_ARNG_Zn510V1_Size0BH2223, a_PREGZM_Pg1013_ZeroPredCheck, a_ARNG_Pd_Size0BH2223, } var Zm_T__Zn_T__PgZ__Zd_T = []operand{ a_ARNG_Zm1621V2_Size0SD2223, - a_ARNG_Zn510_Size0SD2223, + a_ARNG_Zn510V1_Size0SD2223, a_PREGZM_Pg1013_ZeroPredCheck, a_ARNG_Zd_Size0SD2223, } var Zm_T__Zn_T__Pv__Zd_T = []operand{ a_ARNG_Zm1621V2_SizeBHSD2224, - a_ARNG_Zn510_SizeBHSD2224, + a_ARNG_Zn510V1_SizeBHSD2224, a_PREG_Pv1014_Noop, a_ARNG_Zd_SizeBHSD2224, } var Zm_T__Zn_T__Zd_T__1 = []operand{ a_ARNG_Zm1621V2_SizeBHSD2224, - a_ARNG_Zn510_SizeBHSD2224, + a_ARNG_Zn510V1_SizeBHSD2224, a_ARNG_Zd_SizeBHSD2224, } var Zm_T__Zn_T__Zd_T__2 = []operand{ a_ARNG_Zm1621V2_SizeHSD2224No00, - a_ARNG_Zn510_SizeHSD2224No00, + a_ARNG_Zn510V1_SizeHSD2224No00, a_ARNG_Zd_SizeHSD2224No00, } var Zm_T__Zn_T__Zd_T__3 = []operand{ a_ARNG_Zm1621V2_SizeHSD2224, - a_ARNG_Zn510_SizeHSD2224, + a_ARNG_Zn510V1_SizeHSD2224, a_ARNG_Zd_SizeHSD2224, } var Zm_T__Zn_T__Zda_T__1 = []operand{ a_ARNG_Zm1621V2_SzSD2223, - a_ARNG_Zn510_SzSD2223, + a_ARNG_Zn510V1_SzSD2223, a_ARNG_Zda3RdSrcDst_SzSD2223, } var Zm_T__Zn_T__Zda_T__2 = []operand{ a_ARNG_Zm1621V2_SizeBHSD2224, - a_ARNG_Zn510_SizeBHSD2224, + a_ARNG_Zn510V1_SizeBHSD2224, a_ARNG_Zda3RdSrcDst_SizeBHSD2224, } var Zm_T___Zn_T___Zd_T = []operand{ a_ARNG_Zm1621V2_SizeBHSD2224, - a_REGLIST1_Zn510_SizeBHSD2224, + a_REGLIST1_Zn510V1_SizeBHSD2224, a_ARNG_Zd_SizeBHSD2224, } var Zm_Tb__Zn_T__Zd_T = []operand{ a_ARNG_Zm1621V2_SizeTbBHS2224, - a_ARNG_Zn510_SizeHSD2224, + a_ARNG_Zn510V1_SizeHSD2224, a_ARNG_Zd_SizeHSD2224, } var Zm_Tb__Zn_Tb__Zd_T__1 = []operand{ a_ARNG_Zm1621V2_SizeTbBHS2224, - a_ARNG_Zn510_SizeTbBHS2224, + a_ARNG_Zn510V1_SizeTbBHS2224, a_ARNG_Zd_SizeHSD2224, } var Zm_Tb__Zn_Tb__Zd_T__2 = []operand{ a_ARNG_Zm1621V2_SizeTbHSD2224Offset1, - a_ARNG_Zn510_SizeTbHSD2224Offset1, + a_ARNG_Zn510V1_SizeTbHSD2224Offset1, a_ARNG_Zd_SizeBHS2224Offset1, } var Zm_Tb__Zn_Tb__Zd_T__3 = []operand{ a_ARNG_Zm1621V2_SizeTbBS2224, - a_ARNG_Zn510_SizeTbBS2224, + a_ARNG_Zn510V1_SizeTbBS2224, a_ARNG_Zd_SizeHD2224, } var Zm_Tb__Zn_Tb__Zda_T__1 = []operand{ a_ARNG_Zm1621V2_SizeTbBHS2224, - a_ARNG_Zn510_SizeTbBHS2224, + a_ARNG_Zn510V1_SizeTbBHS2224, a_ARNG_Zda3RdSrcDst_SizeHSD2224, } var Zm_Tb__Zn_Tb__Zda_T__2 = []operand{ a_ARNG_Zm1621V2_Size0TbBH2223, - a_ARNG_Zn510_Size0TbBH2223, + a_ARNG_Zn510V1_Size0TbBH2223, a_ARNG_Zda3RdSrcDst_Size0SD2223, } @@ -9933,6 +12288,12 @@ var Zm_index____Zn_H___Zd_H__2 = []operand{ a_ARNG_Zd_ArngHCheck, } +var Zn1_T__Zn2_T___Pv__Zd_T = []operand{ + a_REGLIST2_Zn510MultiSrc1_SizeBHSD2224_Zn510MultiSrc2_SizeBHSD2224, + a_PREG_Pv1013_Noop, + a_ARNG_Zd_SizeBHSD2224, +} + var Zn_B__Zd_H = []operand{ a_ARNG_Zn510Src_ArngBCheck, a_ARNG_Zd_ArngHCheck, @@ -9974,6 +12335,40 @@ var Zn_D__PgZ__Zd_S = []operand{ a_ARNG_Zd_ArngSCheck, } +var Zn_D__Xm___PgZ___Zt_D_ = []operand{ + a_MEMEXT_Zn510V2_ArngDCheck_Rm1621XZR_Noop_NoModCheck_NoAmtCheck, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST1_Zt05_ArngDCheck, +} + +var Zn_D__Xm___PgZ___Zt_Q_ = []operand{ + a_MEMEXT_Zn510V2_ArngDCheck_Rm1621XZR_Noop_NoModCheck_NoAmtCheck, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST1_Zt05_ArngQCheck, +} + +var Zn_D__Xm___Pg___Zt_D_ = []operand{ + a_MEMEXT_Zn510V2_ArngDCheck_Rm1621XZR_Noop_NoModCheck_NoAmtCheck, + a_PREG_Pg1013_Noop, + a_REGLIST1_Zt05_ArngDCheck, +} + +var Zn_D__Xm___Pg___Zt_Q_ = []operand{ + a_MEMEXT_Zn510V2_ArngDCheck_Rm1621XZR_Noop_NoModCheck_NoAmtCheck, + a_PREG_Pg1013_Noop, + a_REGLIST1_Zt05_ArngQCheck, +} + +var Zn_D__Zm_D__SXTWamount___Zd_D = []operand{ + a_MEMEXT_Zn510V2_ArngDCheck_Zm1621V3_ArngDCheck_ModSXTWCheck_Msz1012Amount, + a_ARNG_Zd_ArngDCheck, +} + +var Zn_D__Zm_D__UXTWamount___Zd_D = []operand{ + a_MEMEXT_Zn510V2_ArngDCheck_Zm1621V3_ArngDCheck_ModUXTWCheck_Msz1012Amount, + a_ARNG_Zd_ArngDCheck, +} + var Zn_H__PgM__Zd_D = []operand{ a_ARNG_Zn510Src_ArngHCheck, a_PREGZM_Pg1013_MergePredCheck, @@ -10058,6 +12453,18 @@ var Zn_S__PgZ__Zd_S = []operand{ a_ARNG_Zd_ArngSCheck, } +var Zn_S__Xm___PgZ___Zt_S_ = []operand{ + a_MEMEXT_Zn510V2_ArngSCheck_Rm1621XZR_Noop_NoModCheck_NoAmtCheck, + a_PREGZM_Pg1013_ZeroPredCheck, + a_REGLIST1_Zt05_ArngSCheck, +} + +var Zn_S__Xm___Pg___Zt_S_ = []operand{ + a_MEMEXT_Zn510V2_ArngSCheck_Rm1621XZR_Noop_NoModCheck_NoAmtCheck, + a_PREG_Pg1013_Noop, + a_REGLIST1_Zt05_ArngSCheck, +} + var Zn_T__PgM__Zd_T__1 = []operand{ a_ARNG_Zn510Src_SizeHSD2224, a_PREGZM_Pg1013_MergePredCheck, @@ -10194,6 +12601,11 @@ var Zn_T__Zd_T__2 = []operand{ a_ARNG_Zd_SizeBHSD2224, } +var Zn_T__Zm_T__mod_amount___Zd_T = []operand{ + a_MEMEXT_Zn510V2_SzSD2223_Zm1621V3_SzSD2223_Msz1012_Msz1012Amount, + a_ARNG_Zd_SzSD2223, +} + var Zn_T_imm___Zd_T__1 = []operand{ a_ARNGIDX_Zn510Src_Tsz_1621_SizeSpecifier5_Imm2Tsz_Delegate, a_ARNG_Zd_Tsz_1621_SizeSpecifier5, @@ -10205,7 +12617,7 @@ var Zn_T_imm___Zd_T__2 = []operand{ } var Zn_Tb__PgM__Zda_T = []operand{ - a_ARNG_Zn510_SizeTbBHS2224, + a_ARNG_Zn510V1_SizeTbBHS2224, a_PREGZM_Pg1013_MergePredCheck, a_ARNG_ZdaDest_SizeHSD2224, } @@ -10257,12 +12669,6 @@ var Zn_imm___Pd_S = []operand{ a_ARNG_Pd_ArngSCheck, } -var _Zn1_T__Zn2_T___Pv__Zd_T = []operand{ - a_REGLIST2_Zn510MultiSrc1_SizeBHSD2224_Zn510MultiSrc2_SizeBHSD2224, - a_PREG_Pv1013_Noop, - a_ARNG_Zd_SizeBHSD2224, -} - var c0_0__Zn_T__PgZ__Pd_T = []operand{ a_IMM_Fimm0_0_56, a_ARNG_Zn510Src_SizeHSD2224, @@ -10327,7 +12733,7 @@ var cconst__Zn_T__Zd_T__2 = []operand{ var cconst__Zn_T__Zda_T = []operand{ a_IMM_ShiftTsz1619Range1V2, - a_ARNG_Zn510_SizeBhsdTsz1921, + a_ARNG_Zn510V1_SizeBhsdTsz1921, a_ARNG_Zda3RdSrcDst_SizeBhsdTsz1921, } @@ -10466,42 +12872,42 @@ var const__Zdn_T__PgM__Zdn_T__3 = []operand{ var const__Zm_B_imm___Zn_B__Zda_S = []operand{ a_IMM_Rot0_90_180_270_1012, a_ARNGIDX_Zm1619_8To32Bit_ArngBCheck_I2_1921_8To32Bit, - a_ARNG_Zn510_ArngBCheck, + a_ARNG_Zn510V1_ArngBCheck, a_ARNG_Zda3RdSrcDst_ArngSCheck, } var const__Zm_H_imm___Zn_H__Zda_D = []operand{ a_IMM_Rot0_90_180_270_1012, a_ARNGIDX_Zm1620_16To64Bit_ArngHCheck_I1_2021_16To64Bit, - a_ARNG_Zn510_ArngHCheck, + a_ARNG_Zn510V1_ArngHCheck, a_ARNG_Zda3RdSrcDst_ArngDCheck, } var const__Zm_H_imm___Zn_H__Zda_H__1 = []operand{ a_IMM_Rot0_90_180_270_1012, a_ARNGIDX_Zm_1619_Range0_7V1_ArngHCheck_I2_1921_16bit, - a_ARNG_Zn510_ArngHCheck, + a_ARNG_Zn510V1_ArngHCheck, a_ARNG_Zda3RdSrcDst_ArngHCheck, } var const__Zm_H_imm___Zn_H__Zda_H__2 = []operand{ a_IMM_Rot0_90_180_270_1012, a_ARNGIDX_Zm_1619_Half_ArngHCheck_I2_1921_Half, - a_ARNG_Zn510_ArngHCheck, + a_ARNG_Zn510V1_ArngHCheck, a_ARNG_Zda3RdSrcDst_ArngHCheck, } var const__Zm_S_imm___Zn_S__Zda_S__1 = []operand{ a_IMM_Rot0_90_180_270_1012, a_ARNGIDX_Zm_1620_Range0_15_ArngSCheck_I1_2021_32bit, - a_ARNG_Zn510_ArngSCheck, + a_ARNG_Zn510V1_ArngSCheck, a_ARNG_Zda3RdSrcDst_ArngSCheck, } var const__Zm_S_imm___Zn_S__Zda_S__2 = []operand{ a_IMM_Rot0_90_180_270_1012, a_ARNGIDX_Zm_1620_Single_ArngSCheck_I1_2021_Single, - a_ARNG_Zn510_ArngSCheck, + a_ARNG_Zn510V1_ArngSCheck, a_ARNG_Zda3RdSrcDst_ArngSCheck, } @@ -10523,7 +12929,7 @@ var const__Zm_T__Zdn_T__Zdn_T = []operand{ var const__Zm_T__Zn_T__PgM__Zda_T = []operand{ a_IMM_Rot0_90_180_270_1315, a_ARNG_Zm1621V2_SizeHSD2224, - a_ARNG_Zn510_SizeHSD2224, + a_ARNG_Zn510V1_SizeHSD2224, a_PREGZM_Pg1013_MergePredCheck, a_ARNG_Zda3RdSrcDst_SizeHSD2224, } @@ -10531,14 +12937,14 @@ var const__Zm_T__Zn_T__PgM__Zda_T = []operand{ var const__Zm_T__Zn_T__Zda_T = []operand{ a_IMM_Rot0_90_180_270_1012, a_ARNG_Zm1621V2_SizeBHSD2224, - a_ARNG_Zn510_SizeBHSD2224, + a_ARNG_Zn510V1_SizeBHSD2224, a_ARNG_Zda3RdSrcDst_SizeBHSD2224, } var const__Zm_Tb__Zn_Tb__Zda_T = []operand{ a_IMM_Rot0_90_180_270_1012, a_ARNG_Zm1621V2_Size0TbBH2223, - a_ARNG_Zn510_Size0TbBH2223, + a_ARNG_Zn510V1_Size0TbBH2223, a_ARNG_Zda3RdSrcDst_Size0SD2223, } diff --git a/src/cmd/internal/obj/util.go b/src/cmd/internal/obj/util.go index 9b440ebd58..4349f4d741 100644 --- a/src/cmd/internal/obj/util.go +++ b/src/cmd/internal/obj/util.go @@ -222,6 +222,11 @@ func (ctxt *Link) CanReuseProgs() bool { return ctxt.Debugasm == 0 } +func isZReg(r int) bool { + return (r >= RBaseARM64+96 && r <= RBaseARM64+127) || + (r >= RBaseARM64+2048 && r < RBaseARM64+3072) +} + // Dconv accepts an argument 'a' within a prog 'p' and returns a string // with a formatted version of the argument. func Dconv(p *Prog, a *Addr) string { @@ -297,13 +302,35 @@ func writeDconv(w io.Writer, p *Prog, a *Addr, abiDetail bool) { a.writeNameTo(w, abiDetail) case TYPE_MEM: - a.WriteNameTo(w) - if a.Index != REG_NONE { - if a.Scale == 0 { - // arm64 shifted or extended register offset, scale = 0. - fmt.Fprintf(w, "(%v)", Rconv(int(a.Index))) - } else { - fmt.Fprintf(w, "(%v*%d)", Rconv(int(a.Index)), int(a.Scale)) + if buildcfg.GOARCH == "arm64" && (a.Scale < 0 || isZReg(int(a.Reg)) || isZReg(int(a.Index))) { + // SVE extended addressing pattern + amount := 0 + mod := 0 + if a.Scale < 0 { + amount = int((a.Scale >> 12) & 0x7) + mod = int((a.Scale >> 9) & 0x7) + } + modStr := "" + switch mod { + case 1: + modStr = ".UXTW" + case 2: + modStr = ".SXTW" + } + amountStr := "" + if amount != 0 { + amountStr = fmt.Sprintf("<<%d", amount) + } + fmt.Fprintf(w, "(%v%s%s)(%v)", Rconv(int(a.Reg)), modStr, amountStr, Rconv(int(a.Index))) + } else { + a.WriteNameTo(w) + if a.Index != REG_NONE { + if a.Scale == 0 { + // arm64 shifted or extended register offset, scale = 0. + fmt.Fprintf(w, "(%v)", Rconv(int(a.Index))) + } else { + fmt.Fprintf(w, "(%v*%d)", Rconv(int(a.Index)), int(a.Scale)) + } } } -- cgit v1.3