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2025-07-19cmd/internal/obj: enable got pcrel itype in fips140 for riscv64Meng Zhuo
This CL enable R_RISCV_GOT_PCREL_ITYPE in fips140 Fixes #74662 Change-Id: Ic189c4e352517ae74034f207a5f944b610f2eb73 Reviewed-on: https://go-review.googlesource.com/c/go/+/688635 Reviewed-by: Mark Ryan <markdryan@rivosinc.com> Reviewed-by: Cherry Mui <cherryyz@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Carlos Amedee <carlos@golang.org> Reviewed-by: Julian Zhu <jz531210@gmail.com>
2025-07-16cmd/link, runtime: on Wasm, put only function index in method table and func ↵Cherry Mui
table In the type descriptor's method table, it contains relative PCs of the methods (relative to the start of the text section) stored as 32-bit offsets. On Wasm, a PC is PC_F<<16 + PC_B, where PC_F is the function index, and PC_B is the block index. When there are more than 65536 functions, the PC will not fit into 32-bit (and relative to the section start doesn't help). Since there are no more bits for the function index, and the method table always targets the entry of a method, we put just the PC_F there, and rewrite back to a full PC at run time when we need the PC. This way we can have more than 65536 functions. The func table also contains 32-bit relative PCs, and it also always points to function entries. Do the same there, as well as other places where we use relative text offsets. Also add the relocation type in the relocation overflow error message. Also add check for function too big on Wasm. If a function has more than 65536 blocks, PC_B will overflow and PC = PC_F<<16 + PC_B will points to the wrong function. Fixes #64856. Change-Id: If9c307e9fb1641f367a5f19c39f88f455805d0bb Reviewed-on: https://go-review.googlesource.com/c/go/+/552835 Reviewed-by: Than McIntosh <thanm@google.com> Reviewed-by: Dmitri Shuralyov <dmitshur@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
2025-07-16cmd/internal/obj/wasm: use 64-bit instructions for indirect callsCherry Mui
Currently, on Wasm, an indirect call is compiled to // function index = PC>>16, PC is already on stack I32WrapI64 I32Const $16 ShrU // set PC_B to 0 ... // actual call CallIndirect Specifically, the function index is extracted from bits 16-31 of the "PC". When there are more than 65536 functions, this will overflow and wrap around, causing wrong function being called. This CL changes it to use 64-bit operations to extract the function index from the "PC", so there are enough bits to for it. For #64856. Change-Id: I83c11db4b78cf66250e88ac02a82bd13730a8914 Reviewed-on: https://go-review.googlesource.com/c/go/+/567896 LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Than McIntosh <thanm@google.com> Reviewed-by: Dmitri Shuralyov <dmitshur@google.com>
2025-05-29cmd/internal/obj/s390x: fix potential recursive String callMichael Anthony Knyszek
This String method can potentially recurse infinitely, since %#x will apparently call String if the method exists. This isn't well documented, but cmd/vet will be updated soon to check this (when we update the vendored x/tools dependency) so cut off the recursion by converting to the underlying type first. Change-Id: Ia6fc046c9eb56a5dd6a33772afd23da443a06116 Reviewed-on: https://go-review.googlesource.com/c/go/+/677261 Auto-Submit: Michael Knyszek <mknyszek@google.com> Reviewed-by: David Chase <drchase@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
2025-05-21cmd/internal/obj/loong64: remove unused register alias definitionsGuoqi Chen
Change-Id: Ie788747372cd47cb3780e75b35750bb08bd166fc Reviewed-on: https://go-review.googlesource.com/c/go/+/542835 Reviewed-by: sophie zhao <zhaoxiaolin@loongson.cn> Reviewed-by: David Chase <drchase@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Meidan Li <limeidan@loongson.cn> Auto-Submit: abner chenc <chenguoqi@loongson.cn> Reviewed-by: Michael Knyszek <mknyszek@google.com>
2025-05-21cmd/internal/obj/riscv: fix vector integer multiply addMark Ryan
The RISC-V integer vector multiply add instructions are not encoded correctly; the first and second arguments are swapped. For example, the instruction VMACCVV V1, V2, V3 encodes to b620a1d7 or vmacc.vv v3,v1,v2 and not b61121d7 or vmacc.vv v3,v2,v1 as expected. This is inconsistent with the argument ordering we use for 3 argument vector instructions, in which the argument order, as given in the RISC-V specifications, is reversed, and also with the vector FMA instructions which have the same argument ordering as the vector integer multiply add instructions in the "The RISC-V Instruction Set Manual Volume I". For example, in the ISA manual we have the following instruction definitions ; Integer multiply-add, overwrite addend vmacc.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vs2[i]) + vd[i] ; FP multiply-accumulate, overwrites addend vfmacc.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vs2[i]) + vd[i] It's reasonable to expect that the Go assembler would use the same argument ordering for both of these instructions. It currently does not. We fix the issue by switching the argument ordering for the vector integer multiply add instructions to match those of the vector FMA instructions. Change-Id: Ib98e9999617f991969e5c831734b3bb3324439f6 Reviewed-on: https://go-review.googlesource.com/c/go/+/670335 Reviewed-by: Carlos Amedee <carlos@golang.org> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com> Reviewed-by: Cherry Mui <cherryyz@google.com>
2025-05-15cmd/internal/obj/loong64: change the plan9 format of the prefetch ↵Guoqi Chen
instruction PRELDX before: MOVV $n + $offset, Roff PRELDX (Rbase)(Roff), $hint after: PRELDX offset(Rbase), $n, $hint This instruction is supported in CL 671875, but is not actually used Change-Id: I943d488ea6dc77781cd796ef480a89fede666bab Reviewed-on: https://go-review.googlesource.com/c/go/+/673155 Reviewed-by: Meidan Li <limeidan@loongson.cn> Reviewed-by: sophie zhao <zhaoxiaolin@loongson.cn> Reviewed-by: Michael Knyszek <mknyszek@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Cherry Mui <cherryyz@google.com>
2025-05-14cmd/intarnal/obj: add new assembly format for VANDV and VANDB on loong64Xiaolin Zhao
In order to make it easier to write in assembly and to be consistent with the usage of general instructions, a new assembly format is added for the instructions VANDV and VANDB. It also works for instructions XVAND{V,B}, [X]V{OR,XOR,NOR,ANDN,ORN}V and [X]V{OR,XOR,NOR}B. Change-Id: Ia75d607ac918950e58840ec627aaf0be45d837fe Reviewed-on: https://go-review.googlesource.com/c/go/+/671316 Reviewed-by: Cherry Mui <cherryyz@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Michael Knyszek <mknyszek@google.com>
2025-05-12cmd/internal/obj/loong64: Add preld{,x} instructions supportGuoqi Chen
Go asm syntax: PRELD 16(R4), $8 PRELDX (R4)(R5), $8 Equivalent platform assembler syntax: preld $8, $r4, 16 preldx $8, $r4, $r5 Change-Id: Ie81d22ebaf4153388a7e9d8fa0f618a0ae7a1c9f Reviewed-on: https://go-review.googlesource.com/c/go/+/671875 Reviewed-by: sophie zhao <zhaoxiaolin@loongson.cn> Reviewed-by: Meidan Li <limeidan@loongson.cn> Reviewed-by: Cherry Mui <cherryyz@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Michael Knyszek <mknyszek@google.com>
2025-05-11cmd/internal/obj/loong64: add [X]VFCLASS.{S/D} instructionsXiaolin Zhao
Go asm syntax: VFCLASS{F/D} VJ, VD XVFCLASS{F/D} XJ, XD Equivalent platform assembler syntax: vfclass.{s/d} vd, vj xvfclass.{s/d} xd, xj Change-Id: Iec373f393be315696d1fefc747a4a5882f993195 Reviewed-on: https://go-review.googlesource.com/c/go/+/670256 Reviewed-by: Cherry Mui <cherryyz@google.com> Reviewed-by: Dustin Turner <dustin.turner44@gmail.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Carlos Amedee <carlos@golang.org> Reviewed-by: abner chenc <chenguoqi@loongson.cn>
2025-05-08cmd/internal/obj/loong64: add [X]VF{ADD/SUB/MUL/DIV}.{S/D} instructionsXiaolin Zhao
Go asm syntax: V{ADD/SUB/MUL/DIV}{F/D} VK, VJ, VD XV{ADD/SUB/MUL/DIV}{F/D} XK, XJ, XD Equivalent platform assembler syntax: vf{add/sub/mul/div}.{s/d} vd, vj, vk xvf{add/sub/mul/div}.{s/d} xd, xj, xk Change-Id: I4607884212167ac97d7b6448ea3c849fc0fdd506 Reviewed-on: https://go-review.googlesource.com/c/go/+/670255 Reviewed-by: abner chenc <chenguoqi@loongson.cn> Reviewed-by: Carlos Amedee <carlos@golang.org> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Cherry Mui <cherryyz@google.com>
2025-05-08cmd/internal/obj/riscv: reject invalid vadc/vsbc encodingsMark Ryan
The RISC-V Instruction Set Manual Volume states that "for vadc and vsbc, the instruction encoding is reserved if the destination vector register is v0". The assembler currently allows instructions like VADCVVM V1, V2, V0, V0 to be assembled. It's not clear what the behaviour of such instructions will be on target hardware so it's best to disallow them. For reference, binutils (2.44-3.fc42) allows the instruction vadc.vvm v0, v4, v8, v0 to be assembled and the instruction actually executes on a Banana PI F3 without crashing. However, clang (20.1.2) refuses to assemble the instruction, producing the following error. error: the destination vector register group cannot be V0 vadc.vvm v0, v4, v8, v0 ^ Change-Id: Ia913cbd864ae8dbcf9227f69b963c93a99481cff Reviewed-on: https://go-review.googlesource.com/c/go/+/669315 Reviewed-by: Carlos Amedee <carlos@golang.org> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Cherry Mui <cherryyz@google.com> Reviewed-by: Joel Sing <joel@sing.id.au>
2025-05-08cmd/internal/obj/riscv: fix LMUL encoding for MF2 and MF8Mark Ryan
The encodings for the riscv64 special operands SPOP_MF2 and SPOP_MF8 are incorrect, i.e., their values are swapped. This leads to incorrect encodings for the VSETVLI and VSETIVLI instructions. The assembler currently encodes VSETVLI X10, E32, MF8, TA, MA, X12 as VSETVLI X10, E32, MF2, TA, MA, X12 We update the encodings for SPOP_MF2 and SPOP_MF8 so that they match the LMUL table in section "31.3.4. Vector type register, vtype" of the "RISC-V Instruction Set Manual Volume 1". Change-Id: Ic73355533d7c2a901ee060b35c2f7af6d58453e4 Reviewed-on: https://go-review.googlesource.com/c/go/+/670016 LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Cherry Mui <cherryyz@google.com> Reviewed-by: Carlos Amedee <carlos@golang.org> Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com> Reviewed-by: Joel Sing <joel@sing.id.au>
2025-05-07cmd/internal/obj/loong64: add [X]VFRINT[{RNE/RZ/RP/RM}].{S/D} instructionsXiaolin Zhao
Go asm syntax: VFRINT[{RNE/RZ/RP/RM}]{F/D} VJ, VD XVFRINT[{RNE/RZ/RP/RM}]{F/D} XJ, XD Equivalent platform assembler syntax: vfrint[{rne/rz/rp/rm}].{s/d} vd, vj xvfrint[{rne/rz/rp/rm}].{s/d} xd, xj Change-Id: I4ed8782289ae3329d675239f799d5f75b1adc4ad Reviewed-on: https://go-review.googlesource.com/c/go/+/670235 Reviewed-by: abner chenc <chenguoqi@loongson.cn> Reviewed-by: Cherry Mui <cherryyz@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Carlos Amedee <carlos@golang.org>
2025-05-05Revert "cmd/compile: allow all of the preamble to be preemptible"Keith Randall
This reverts commits 3f3782feed6e0726ddb08afd32dad7d94fbb38c6 (CL 648518) b386b628521780c048af14a148f373c84e687b26 (CL 668475) Fixes #73542 Change-Id: I218851c5c0b62700281feb0b3f82b6b9b97b910d Reviewed-on: https://go-review.googlesource.com/c/go/+/670055 Reviewed-by: Keith Randall <khr@google.com> Auto-Submit: Keith Randall <khr@golang.org> Reviewed-by: Cherry Mui <cherryyz@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
2025-05-02cmd/internal/obj/riscv: add support for vector permutation instructionsJoel Sing
Add support for vector permutation instructions to the RISC-V assembler. This includes integer scalar move, floating point scalar move, slide up and slide down, register gather, compression and whole vector register move instructions. Change-Id: I1da9f393091504fd81714006355725b8b9ecadea Reviewed-on: https://go-review.googlesource.com/c/go/+/646780 LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Carlos Amedee <carlos@golang.org> Reviewed-by: Mark Ryan <markdryan@rivosinc.com> Reviewed-by: Junyang Shao <shaojunyang@google.com> Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com>
2025-05-02cmd/internal/obj/riscv: add support for vector mask instructionsJoel Sing
Add support for vector mask instructions to the RISC-V assembler. These allow manipulation of vector masks and include mask register logical instructions, population count and find-first bit set instructions. Change-Id: I3ab3aa0f918338aee9b37ac5a2b2fdc407875072 Reviewed-on: https://go-review.googlesource.com/c/go/+/646779 Reviewed-by: Carlos Amedee <carlos@golang.org> Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Mark Ryan <markdryan@rivosinc.com> Reviewed-by: Junyang Shao <shaojunyang@google.com>
2025-05-02cmd/internal/obj/riscv: add support for vector reduction instructionsJoel Sing
Add support for vector reduction instructions to the RISC-V assembler, including single-width integer reduction, widening integer reduction, single-width floating-point reduction and widening floating-point reduction. Change-Id: I8f17bef11389f3a017e0430275023fc5d75936e3 Reviewed-on: https://go-review.googlesource.com/c/go/+/646778 Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com> Reviewed-by: Mark Ryan <markdryan@rivosinc.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Carlos Amedee <carlos@golang.org> Reviewed-by: Dmitri Shuralyov <dmitshur@google.com>
2025-05-01cmd/internal/obj/riscv: add support for vector floating-point instructionsJoel Sing
Add support for vector floating-point instructions to the RISC-V assembler. This includes single-width and widening addition and subtraction, multiplication and division, fused multiply-addition, comparison, min/max, sign-injection, classification and type conversion instructions. Change-Id: I8bceb1c5d7eead0561ba5407ace00805a6144f51 Reviewed-on: https://go-review.googlesource.com/c/go/+/646777 Reviewed-by: Carlos Amedee <carlos@golang.org> Reviewed-by: Junyang Shao <shaojunyang@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com> Reviewed-by: Mark Ryan <markdryan@rivosinc.com>
2025-04-28cmd/internal/obj/loong64: fix the error parameters when calling ↵Guoqi Chen
UnspillRegisterArgs This bug was introduced in CL 648518. Fixes #73518. Change-Id: I4988dd0b636c6a6a48d2aa2e2ae868e43f69995a Reviewed-on: https://go-review.googlesource.com/c/go/+/668475 LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Meidan Li <limeidan@loongson.cn> Reviewed-by: Dmitri Shuralyov <dmitshur@google.com> Reviewed-by: Keith Randall <khr@google.com>
2025-04-25cmd/compile: allow all of the preamble to be preemptibleKeith Randall
We currently make some parts of the preamble unpreemptible because it confuses morestack. See comments in the code. Instead, have morestack handle those weird cases so we can remove unpreemptible marks from most places. This CL makes user functions preemptible everywhere if they have no write barriers (at least, on x86). In cmd/go the fraction of functions that need preemptible markings drops from 82% to 36%. Makes the cmd/go binary 0.3% smaller. Update #35470 Change-Id: Ic83d5eabfd0f6d239a92e65684bcce7e67ff30bb Reviewed-on: https://go-review.googlesource.com/c/go/+/648518 Auto-Submit: Keith Randall <khr@google.com> Reviewed-by: Keith Randall <khr@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Cherry Mui <cherryyz@google.com>
2025-04-24cmd/internal/obj: add new assembly format for BFPT and BFPF on loong64Guoqi Chen
On loong64, BFPT and BFPF are mapped to the platform assembly as follows: Go asm syntax: BFPT FCCx, offs21 BFPF FCCx, offs21 Equivalent platform assembler syntax: bcnez cj, offs21 bceqz cj, offs21 If the condition register is not specified, it defaults to FCC0. Change-Id: I2cc3df62a9c55d4b5eb124789358983c6737319c Reviewed-on: https://go-review.googlesource.com/c/go/+/667456 Reviewed-by: Dmitri Shuralyov <dmitshur@google.com> Reviewed-by: Junyang Shao <shaojunyang@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Meidan Li <limeidan@loongson.cn>
2025-04-15cmd/internal/obj/loong64: add support for {V,XV}SET{EQ,NE}Z.V series ↵limeidan
instructions Change-Id: If3794dfde3ff461662c8a493ff51d0c779e81bca Reviewed-on: https://go-review.googlesource.com/c/go/+/664795 LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: abner chenc <chenguoqi@loongson.cn> Reviewed-by: Michael Pratt <mpratt@google.com> Reviewed-by: Dmitri Shuralyov <dmitshur@google.com>
2025-04-09cmd/internal/obj/wasm: use i64 for large return addrZxilly
Use i64 to avoid overflow when getting PC_F from the return addr. Fixes #73246 Change-Id: I5683dccf7eada4b8536edf53e2e83116a2f6d943 GitHub-Last-Rev: 267d9a1a031868430d0af530de14229ee1ae8609 GitHub-Pull-Request: golang/go#73277 Reviewed-on: https://go-review.googlesource.com/c/go/+/663995 LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Dmitri Shuralyov <dmitshur@google.com> Reviewed-by: Cherry Mui <cherryyz@google.com>
2025-04-03cmd/internal/obj/arm64: return a bit shift from movconJoel Sing
Return the shift in bits from movcon, rather than returning an index. This allows a number of multiplications to be removed, making the code more readable. Scale down to an index only when encoding. Change-Id: I1be91eb526ad95d389e2f8ce97212311551790df Reviewed-on: https://go-review.googlesource.com/c/go/+/650939 Auto-Submit: Joel Sing <joel@sing.id.au> Reviewed-by: Dmitri Shuralyov <dmitshur@google.com> Reviewed-by: Cherry Mui <cherryyz@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
2025-04-03cmd/internal/obj/arm64: deduplicate con32classJoel Sing
Teach conclass how to handle 32 bit values and deduplicate the code between con32class and conclass. Change-Id: I9c5eea31d443fd4c2ce700c6ea21e1d0bef665b0 Reviewed-on: https://go-review.googlesource.com/c/go/+/650938 LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Cherry Mui <cherryyz@google.com> Reviewed-by: Dmitri Shuralyov <dmitshur@google.com> Auto-Submit: Joel Sing <joel@sing.id.au>
2025-04-03cmd/internal/obj/arm64: simplify conclassJoel Sing
Reduce repetition by pulling some common conversions into variables. Change-Id: I8c1cc806236b5ecdadf90f4507923718fa5de9b6 Reviewed-on: https://go-review.googlesource.com/c/go/+/650937 Reviewed-by: Cherry Mui <cherryyz@google.com> Reviewed-by: Dmitri Shuralyov <dmitshur@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
2025-04-01cmd/internal/obj/riscv: add support for vector fixed-point arithmetic ↵Joel Sing
instructions Add support for vector fixed-point arithmetic instructions to the RISC-V assembler. This includes single width saturating addition and subtraction, averaging addition and subtraction and scaling shift instructions. Change-Id: I9aa27e9565ad016ba5bb2b479e1ba70db24e4ff5 Reviewed-on: https://go-review.googlesource.com/c/go/+/646776 Reviewed-by: Mark Ryan <markdryan@rivosinc.com> Reviewed-by: Carlos Amedee <carlos@golang.org> Reviewed-by: Dmitri Shuralyov <dmitshur@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
2025-03-29cmd/internal/obj/arm64: factor out constant classification codeJoel Sing
This will allow for further improvements and deduplication. Change-Id: I9374fc2d16168ced06f3fcc9e558a9c85e24fd01 Reviewed-on: https://go-review.googlesource.com/c/go/+/650936 Reviewed-by: Fannie Zhang <Fannie.Zhang@arm.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Cherry Mui <cherryyz@google.com> Reviewed-by: Dmitri Shuralyov <dmitshur@google.com>
2025-03-29cmd/internal/obj/riscv: add support for vector integer arithmetic instructionsJoel Sing
Add support for vector integer arithmetic instructions to the RISC-V assembler. This includes vector addition, subtraction, integer extension, add-with-carry, subtract-with-borrow, bitwise logical operations, comparison, min/max, integer division and multiplication instructions. Change-Id: I8c191ef8e31291e13743732903e4f12356133a46 Reviewed-on: https://go-review.googlesource.com/c/go/+/646775 Reviewed-by: Dmitri Shuralyov <dmitshur@google.com> Reviewed-by: Cherry Mui <cherryyz@google.com> Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Mark Ryan <markdryan@rivosinc.com>
2025-03-27cmd/internal/obj/riscv,internal/bytealg: synthesize MIN/MAX/MINU/MAXU ↵Joel Sing
instructions Provide a synthesized version of the MIN/MAX/MINU/MAXU instructions if they're not natively available. This allows these instructions to be used in assembly unconditionally. Use MIN in internal/bytealg.compare. Cq-Include-Trybots: luci.golang.try:gotip-linux-riscv64 Change-Id: I8a5a3a59f0a9205e136fc3d673b23eaf3ca469f8 Reviewed-on: https://go-review.googlesource.com/c/go/+/653295 Reviewed-by: Mark Ryan <markdryan@rivosinc.com> Reviewed-by: Cherry Mui <cherryyz@google.com> Reviewed-by: Dmitri Shuralyov <dmitshur@google.com> Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
2025-03-27cmd/internal/obj/riscv: improve constant constructionJoel Sing
Attempt to construct large constants that have a consecutive sequence of ones from a small negative constant, with a logical right and/or left shift. This allows for a large range of mask like constants to be constructed with only two or three instructions, avoiding the need to load from memory. Change-Id: I35a77fecdd2df0ed3f33b772d518f85119d4ff66 Reviewed-on: https://go-review.googlesource.com/c/go/+/652778 LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Dmitri Shuralyov <dmitshur@google.com> Reviewed-by: Cherry Mui <cherryyz@google.com> Reviewed-by: Mark Ryan <markdryan@rivosinc.com> Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com>
2025-03-26cmd/internal/obj/arm64: add support for BTI instructionJoel Sing
Add support for the `BTI' instruction to the arm64 assembler. This instruction provides Branch Target Identification for targets of indirect branches. A BTI can be marked with a target type of 'C' (call), 'J' (jump) or 'JC' (jump or call). Updates #66054 Change-Id: I1cf31a0382207bb75b9b2deb49ac298a59c00d8a Reviewed-on: https://go-review.googlesource.com/c/go/+/646781 LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Marvin Drees <marvin.drees@9elements.com> Reviewed-by: Cherry Mui <cherryyz@google.com> Reviewed-by: Dmitri Shuralyov <dmitshur@google.com>
2025-03-25cmd/internal/obj/loong64: add [X]VSHUF4I.{B/H/W/D} instructions supportXiaolin Zhao
Go asm syntax: VSHUF4I{B/H/W/V} $1, V1, V2 XVSHUF4I{B/H/W/V} $2, X1, X2 Equivalent platform assembler syntax: vshuf4i.{b/h/w/d} v2, v1, $1 xvshuf4i.{b/h/w/d} x2, x1, $2 Change-Id: I6a847ccbd2c93432d87bd1390b5cf1508da06496 Reviewed-on: https://go-review.googlesource.com/c/go/+/658376 Reviewed-by: Cherry Mui <cherryyz@google.com> Reviewed-by: Dmitri Shuralyov <dmitshur@google.com> Reviewed-by: abner chenc <chenguoqi@loongson.cn> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
2025-03-25cmd/internal/obj/arm64: move register encoding into opldrr/opstrrJoel Sing
Rather than having register encoding knowledge in each caller of opldrr/opstrr (and in a separate olsxrr function), pass the registers into opldrr/opstrr and let them handle the encoding. This reduces duplication and improves readability. Change-Id: I50a25263f305d01454f3ff95e8b6e7c76e760ab0 Reviewed-on: https://go-review.googlesource.com/c/go/+/471521 Reviewed-by: Cherry Mui <cherryyz@google.com> Reviewed-by: Dmitri Shuralyov <dmitshur@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
2025-03-25cmd/internal/obj/loong64: add [X]VMULW{EV/OD} series instructions supportXiaolin Zhao
Go asm syntax: VMULW{EV/OD}{HB/WH/VW/QV}[U] VK, VJ, VD XVMULW{EV/OD}{HB/WH/VW/QV}[U] XK, XJ, XD VMULW{EV/OD}{HBUB/WHUH/VWUW/QVUV} VK, VJ, VD XVMULW{EV/OD}{HBUB/WHUH/VWUW/QVUV} XK, XJ, XD Equivalent platform assembler syntax: vmulw{ev/od}.{h.b/w.h/d.w/q.d}[u] vd, vj, vk xvmulw{ev/od}.{h.b/w.h/d.w/q.d}[u] xd, xj, xk vmulw{ev/od}.{h.bu.b/w.hu.h/d.wu.w/q.du.d} vd, vj, vk xvmulw{ev/od}.{h.bu.b/w.hu.h/d.wu.w/q.du.d} xd, xj, xk Change-Id: Ib1b5fb9605417a2b81841deae40e0e2beb90d03c Reviewed-on: https://go-review.googlesource.com/c/go/+/658375 LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: abner chenc <chenguoqi@loongson.cn> Reviewed-by: Cherry Mui <cherryyz@google.com> Reviewed-by: David Chase <drchase@google.com>
2025-03-25cmd/internal/obj/arm64: provide and use an oprrrr functionJoel Sing
Provide a four register version of oprrr, which takes an additional 'ra' register. Use this instead of oprrr where appropriate. Change-Id: I8882957a83c2b08e407f37a37c61864cd920bbc9 Reviewed-on: https://go-review.googlesource.com/c/go/+/471519 Reviewed-by: Dmitri Shuralyov <dmitshur@google.com> Reviewed-by: Cherry Mui <cherryyz@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
2025-03-25cmd/internal/obj/arm64: move register encoding into oprrrJoel Sing
Rather than having register encoding knowledge in each caller of oprrr, pass the registers into oprrr and let it handle the encoding. This reduces duplication and improves readability. Change-Id: Iab6c70f7796b7a8c071419654b8a5686aeee8c1b Reviewed-on: https://go-review.googlesource.com/c/go/+/471518 Reviewed-by: Fannie Zhang <Fannie.Zhang@arm.com> Reviewed-by: Dmitri Shuralyov <dmitshur@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Cherry Mui <cherryyz@google.com>
2025-03-25cmd/internal/obj/arm64: replace range checks with isaddcon2Joel Sing
isaddcon2 tests for the range 0 <= v <= 0xffffff - replace duplicated range checks with calls to isaddcon2. Change-Id: Ia6f331852ed3d77715b265cb4fcc500579eac711 Reviewed-on: https://go-review.googlesource.com/c/go/+/650935 LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Fannie Zhang <Fannie.Zhang@arm.com> Reviewed-by: Cherry Mui <cherryyz@google.com> Reviewed-by: Dmitri Shuralyov <dmitshur@google.com>
2025-03-24cmd/asm: add LCDBR instruction on s390xVishwanatha HD
This CL is to add LCDBR assembly instruction mnemonics, mainly used in math package. The LCDBR instruction has the same effect as the FNEG pseudo-instructions, just that it sets the flag. Change-Id: I3f00f1ed19148d074c3b6c5f64af0772289f2802 Reviewed-on: https://go-review.googlesource.com/c/go/+/648036 Reviewed-by: Srinivas Pokala <Pokala.Srinivas@ibm.com> Reviewed-by: Cherry Mui <cherryyz@google.com> Reviewed-by: Michael Munday <mike.munday@lowrisc.org> Reviewed-by: Michael Pratt <mpratt@google.com> Run-TryBot: Michael Munday <mike.munday@lowrisc.org> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> TryBot-Result: Gopher Robot <gobot@golang.org>
2025-03-21cmd/internal/obj/riscv: factor out shift constant codeJoel Sing
Move the code that tests to see if a constant can be represented by a 32 bit signed integer and a logical left shift. This reduces duplication and increases readability. Also add test coverage now that this is an independent function. Change-Id: Id25395b1380b00cf5b69ca201b7715ef84f7ade6 Reviewed-on: https://go-review.googlesource.com/c/go/+/652777 LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com> Reviewed-by: David Chase <drchase@google.com> Reviewed-by: Cherry Mui <cherryyz@google.com>
2025-03-20cmd/internal/obj/riscv: fix the encoding for REV8 and ORCBMark Ryan
The instructions are currently encoded and validated using an iIIEncoding which is incorrect as these instructions do not take an immediate operand. Encode them instead using an rIIEncoding as is done for the other two register argument bitmanip instructions. Change-Id: Ia4d9c6f6ebd2dfc381935ebc11afa8fc3664232b Reviewed-on: https://go-review.googlesource.com/c/go/+/637317 Reviewed-by: David Chase <drchase@google.com> Reviewed-by: Joel Sing <joel@sing.id.au> Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Cherry Mui <cherryyz@google.com>
2025-03-19cmd/internal/obj/riscv: prevent panics on bad branchesMark Ryan
Syntactically incorrect branches, such as BEQ X5, X6, $1 BEQ X5, X6, 31(X10) cause the assembler to panic, which they shouldn't really do. It's better for the user to see a normal error, as reported for other syntax errors in riscv64 assembly. The panics also prevent us from writing negative tests for these sorts of errors. Here we fix the issue by ensuring we generate a normal error instead of panicking when the user provides an invalid branch target. We also add a couple of negative tests. Change-Id: I1da568999a75097484b61a01d418f5d4be3e04fa Reviewed-on: https://go-review.googlesource.com/c/go/+/637316 Reviewed-by: Cherry Mui <cherryyz@google.com> Reviewed-by: Joel Sing <joel@sing.id.au> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: David Chase <drchase@google.com> Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com>
2025-03-18cmd/internal/obj/riscv: prevent duplicate error reportsMark Ryan
The riscv64 Go assembler can output certain errors, ones produced by instructionsForProg, multiple times. These errors are guaranteed to be output at least twice and can appear three or more times if a rescan is needed to recompute branch addresses. For example, the syntactically incorrect instruction MOV (X10), $1 will generate at least two identical errors asm: 86076 (asm.s:21524) MOV (X10), $1: unsupported MOV asm: 86076 (asm.s:21524) MOV (X10), $1: unsupported MOV asm: assembly failed In addition to confusing the user, these duplicate errors make it difficult to write negative tests for certain types of instructions, e.g., branches, whose duplicate errors are not always identical, and so not ignored by endtoend_test.go. We fix the issue by returning from preprocess if any errors have been generated by the time we reach the end of the rescan loop. One implication of this change is that validation errors will no longer be reported if an error is generated earlier in the preprocess stage. Negative test cases for validation errors are therefore moved to their own file as the existing riscv64error.s file contains errors generated by instructionsForProg that will now suppress the validation errors. Change-Id: Iffacdbefce28f44970dd5dda44990b822b8a23d4 Reviewed-on: https://go-review.googlesource.com/c/go/+/637315 LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Joel Sing <joel@sing.id.au> Reviewed-by: David Chase <drchase@google.com> Reviewed-by: Cherry Mui <cherryyz@google.com>
2025-03-16cmd/internal/obj/loong64: add {V,XV}NEG{B/H/W/V} instructions supportXiaolin Zhao
Go asm syntax: VNEG{B/H/W/V} VJ, VD XVNEG{B/H/W/V} XJ, XD Equivalent platform assembler syntax: vneg.{b/h/w/d} vd, vj xvneg.{b/h/w/d} xd, xj Change-Id: Ie0a82a434b0ffbcb77425a65b96eff56e030028c Reviewed-on: https://go-review.googlesource.com/c/go/+/635935 Reviewed-by: abner chenc <chenguoqi@loongson.cn> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Cherry Mui <cherryyz@google.com> Reviewed-by: David Chase <drchase@google.com>
2025-03-13cmd/internal/obj/loong64: add {V,XV}{FSQRT/FRECIP/FRSQRT}.{S/D} instructions ↵Xiaolin Zhao
support Go asm syntax: V{FSQRT/FRECIP/FRSQRT}{F/D} VJ, VD XV{FSQRT/FRECIP/FRSQRT}{F/D} XJ, XD Equivalent platform assembler syntax: v{fsqrt/frecip/frsqrt}.{s/d} vd, vj xv{fsqrt/frecip/frsqrt}.{s/d} xd, xj Change-Id: I3fdbe3193659d7532164451b087ccf725053172f Reviewed-on: https://go-review.googlesource.com/c/go/+/636395 Reviewed-by: David Chase <drchase@google.com> Reviewed-by: abner chenc <chenguoqi@loongson.cn> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Junyang Shao <shaojunyang@google.com>
2025-03-12cmd/internal/obj/loong64: add {V,XV}DIV{B/H/W/V}[U] and ↵Xiaolin Zhao
{V,XV}MOD{B/H/W/V}[U] instructions support Go asm syntax: VDIV{B/H/W/V}[U] VK, VJ, VD XVDIV{B/H/W/V}[U] XK, XJ, XD VMOD{B/H/W/V}[U] VK, VJ, VD XVMOD{B/H/W/V}[U] XK, XJ, XD Equivalent platform assembler syntax: vdiv.{b/h/w/d}[u] vd, vj, vk xvdiv.{b/h/w/d}[u] xd, xj, xk vmod.{b/h/w/d}[u] vd, vj, vk xvmod.{b/h/w/d}[u] xd, xj, xk Change-Id: I3676721c3c415de0f2ebbd480ecd1b2400a28dba Reviewed-on: https://go-review.googlesource.com/c/go/+/636376 Reviewed-by: abner chenc <chenguoqi@loongson.cn> Reviewed-by: Junyang Shao <shaojunyang@google.com> Reviewed-by: David Chase <drchase@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
2025-03-11cmd/internal/obj/loong64: add {V,XV}MUL{B/H/W/V} and {V,XV}MUH{B/H/W/V}[U] ↵Xiaolin Zhao
instructions support Go asm syntax: VMUL{B/H/W/V} VK, VJ, VD VMUH{B/H/W/V}[U] VK, VJ, VD XVMUL{B/H/W/V} XK, XJ, XD XVMUH{B/H/W/V}[U] XK, XJ, XD Equivalent platform assembler syntax: vmul.{b/h/w/d} vd, vj, vk vmuh.{b/h/w/d}[u] vd, vj, vk xvmul.{b/h/w/d} xd, xj, xk xvmuh.{b/h/w/d}[u] xd, xj, xk Change-Id: I2f15a5b4b6303a0f82cb85114477f58e1b5fd950 Reviewed-on: https://go-review.googlesource.com/c/go/+/636375 LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Auto-Submit: abner chenc <chenguoqi@loongson.cn> Reviewed-by: David Chase <drchase@google.com> Reviewed-by: Junyang Shao <shaojunyang@google.com> Reviewed-by: abner chenc <chenguoqi@loongson.cn>
2025-03-10cmd/internal/obj/loong64: add {V,XV}SEQI, {V,XV}.{AND,OR,XOR,NOR} ↵Guoqi Chen
instructions support Go asm syntax: VSEQB $1, V2, V3 XVSEQB $2, X2, X3 V{AND,OR,XOR,NOR}B $1, V2, V3 XV{AND,OR,XOR,NOR}B $1, V2, V3 V{AND,OR,XOR,NOR,ANDN,ORN}V V1, V2, V3 XV{AND,OR,XOR,NOR,ANDN,ORN}V V1, V2, V3 Equivalent platform assembler syntax: vseqi.b v3, v2, $1 xvseqi.b x3, x2 ,$2 v{and,or,xor,nor}.b v3, v2, $1 xv{and,or,xor,nor}.b x3, x2, $1 v{and,or,xor,nor,andn,orn}v v3, v2, v1 xv{and,or,xor,nor,andn,orn}v x3, x2, x1 Change-Id: I56ae0db72c7f473755cbdc7f7171c1058a9def97 Reviewed-on: https://go-review.googlesource.com/c/go/+/635515 Reviewed-by: Meidan Li <limeidan@loongson.cn> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Junyang Shao <shaojunyang@google.com> Reviewed-by: David Chase <drchase@google.com>
2025-03-06cmd/internal/obj/loong64: add {V,XV}ILV{L/H}.{B/H/W/D} instructions supportXiaolin Zhao
Go asm syntax: VILV{L/H}{B/H/W/V} VK, VJ, VD XVILV{L/H}{B/H/W/V} XK, XJ, XD Equivalent platform assembler syntax: vilv{l/h}.{b/h/w/d} vd, vj, vk xvilv{l/h}.{b/h/w/d} xd, xj, xk Change-Id: I40e21737649d9fdbbc9a423e859f4c0a56d069fb Reviewed-on: https://go-review.googlesource.com/c/go/+/635936 Reviewed-by: Junyang Shao <shaojunyang@google.com> Reviewed-by: Michael Pratt <mpratt@google.com> Reviewed-by: abner chenc <chenguoqi@loongson.cn> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Auto-Submit: Junyang Shao <shaojunyang@google.com>
generated by cgit v1.3 (git 2.53.0) at 2026-04-15 12:07:19 +0000