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Right shift by 0 has bad semantics. Make sure if we try to right shift by 0,
do a left shift by 0 instead.
CL 549955 handled full instructions with this strange no-op encoding.
This CL handles the shift done to instruction register inputs.
(The former is implemented using the latter, but not until deep
inside the assembler.)
Update #64715
Change-Id: Ibfabb4b13e2595551e58b977162fe005aaaa0ad1
Reviewed-on: https://go-review.googlesource.com/c/go/+/550335
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Right shifts, for some odd reasons, can encode shifts of constant
1-32 instead of 0-31. Left shifts, however, can encode shifts 0-31.
When the shift amount is 0, arm recommends encoding right shifts
using left shifts.
Fixes #64715
Change-Id: Id3825349aa7195028037893dfe01fa0e405eaa51
Reviewed-on: https://go-review.googlesource.com/c/go/+/549955
Reviewed-by: Cherry Mui <cherryyz@google.com>
Reviewed-by: Cuong Manh Le <cuong.manhle.vn@gmail.com>
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ZR register can be used in register pair of LDP, LDPW and LDPSW
instructions, but now it's not allowed. This CL fixes this issue.
Change-Id: I8467502de4664214e0b7dad0295c44f6cff16ee6
Reviewed-on: https://go-review.googlesource.com/c/go/+/547815
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KMCTR encoding arguments incorrect way, which leading illegal instruction wherver we call KMCTR instruction.IBM z13 machine test's TestAESGCM test using gcmASM implementation, which uses KMCTR instruction to encrypt using AES in counter mode and the KIMD instruction for GHASH. z14+ machines onwards uses gcmKMA implementation for the same.
Fixes #63387
Change-Id: I86aeb99573c3f636a71908c99e06a9530655aa5d
Reviewed-on: https://go-review.googlesource.com/c/go/+/535675
Reviewed-by: Vishwanatha HD <vishwanatha.hd@ibm.com>
Reviewed-by: Keith Randall <khr@google.com>
Reviewed-by: Cherry Mui <cherryyz@google.com>
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Add support for PCALIGN directive on riscv.
This directive can be used within Go asm to align instruction
by padding NOP directives.
This patch also adds a test to verify the correctness of the PCALIGN
directive.
Original credit by Cooper Qu (Alibaba)
https://gitee.com/xuantie_riscv/xuantie-patch
Change-Id: I8b6524a2bf81a1baf7c9d04b7da2db6c1a7b428f
Reviewed-on: https://go-review.googlesource.com/c/go/+/541740
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Update #40724
Co-authored-by: Xiaolin Zhao <zhaoxiaolin@loongson.cn>
Change-Id: Ie92da57e29bae0e5cccb2a49a7cbeaf02cbf3a8d
Reviewed-on: https://go-review.googlesource.com/c/go/+/521787
Reviewed-by: Meidan Li <limeidan@loongson.cn>
Run-TryBot: David Chase <drchase@google.com>
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regABI arguments
Update #40724
Co-authored-by: Xiaolin Zhao <zhaoxiaolin@loongson.cn>
Change-Id: Ic7e2e7fb4c1d3670e6abbfb817aa6e4e654e08d3
Reviewed-on: https://go-review.googlesource.com/c/go/+/521777
Reviewed-by: David Chase <drchase@google.com>
Reviewed-by: Meidan Li <limeidan@loongson.cn>
Reviewed-by: Cherry Mui <cherryyz@google.com>
Reviewed-by: Than McIntosh <thanm@google.com>
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loong64
Updates #58784
Change-Id: Ic98d10a512fea0c3ca321ab52693d9f6775126a6
Reviewed-on: https://go-review.googlesource.com/c/go/+/480875
Reviewed-by: David Chase <drchase@google.com>
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Reviewed-by: Meidan Li <limeidan@loongson.cn>
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device for loong64
Add R21 to the allocatable registers, use R20 and R21 in duff
device. This CL is in preparation for subsequent regABI support.
Updates #40724
Co-authored-by: Xiaolin Zhao <zhaoxiaolin@loongson.cn>
Change-Id: If1661adc0f766925fbe74827a369797f95fa28a9
Reviewed-on: https://go-review.googlesource.com/c/go/+/521775
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This change introduces new options to set the floating point
mode on ARM targets. The GOARM version number can optionally be
followed by ',hardfloat' or ',softfloat' to select whether to
use hardware instructions or software emulation for floating
point computations, respectively. For example,
GOARM=7,softfloat.
Previously, software floating point support was limited to
GOARM=5. With these options, software floating point is now
extended to all ARM versions, including GOARM=6 and 7. This
change also extends hardware floating point to GOARM=5.
GOARM=5 defaults to softfloat and GOARM=6 and 7 default to
hardfloat.
For #61588
Change-Id: I23dc86fbd0733b262004a2ed001e1032cf371e94
Reviewed-on: https://go-review.googlesource.com/c/go/+/514907
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Change-Id: I179b50ae8e73677d4d408b83424afbbfe6aa17a1
GitHub-Last-Rev: 2e2d9c1e45556155d02db4df381b99f2d1bc5c0e
GitHub-Pull-Request: golang/go#63478
Reviewed-on: https://go-review.googlesource.com/c/go/+/534015
Auto-Submit: Dmitri Shuralyov <dmitshur@golang.org>
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getimpliedreg was used to set a default register in cases where
one was implied but not set by the assembler or compiler.
In most cases with constant values, R0 is implied, and is the value
0 by architectural design. In those cases, R0 is always used, so
treat 0 and REG_R0 as interchangeable in those encodings.
Similarly, the pseudo-register SP or FP is used to in place of the
stack pointer, always R1 on PPC64. Unconditionally set this during
classification of NAME_AUTO and NAME_PARAM as it may be 0.
The case where REGSB might be returned from getimpliedreg is never
used. REGSB is aliased to R2, but in practice it is either R0 or R2
depending on buildmode. See symbolAccess in asm9.go for an example.
Change-Id: I7283e66d5351f56a7fe04cee38714910eaa73cb3
Reviewed-on: https://go-review.googlesource.com/c/go/+/434775
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This halves the size of the xcmp lookup table.
Change-Id: I543fb72709ca45c026e9b7d8084a78f2a8fcd43e
Reviewed-on: https://go-review.googlesource.com/c/go/+/542295
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This optab matching rule was used to match signed 16 bit values shifted
left by 16 bits. Unsigned 16 bit values greater than 0x7FFF<<16 were
classified as C_U32CON which led to larger than necessary codegen.
Instead, rewrite logical/arithmetic operations in the preprocessor pass
to use the 16 bit shifted immediate operation (e.g ADDIS vs ADD). This
simplifies the optab matching rules, while also minimizing codegen size
for large unsigned values.
Note, ADDIS sign-extends the constant argument, all others do not.
For matching opcodes, this means:
MOVD $is<<16,Rx becomes ADDIS $is,Rx or ORIS $is,Rx
MOVW $is<<16,Rx becomes ADDIS $is,Rx
ADD $is<<16,[Rx,]Ry becomes ADDIS $is[Rx,]Ry
OR $is<<16,[Rx,]Ry becomes ORIS $is[Rx,]Ry
XOR $is<<16,[Rx,]Ry becomes XORIS $is[Rx,]Ry
Change-Id: I1a988d9f52517a04bb8dc2e41d7caf3d5fff867c
Reviewed-on: https://go-review.googlesource.com/c/go/+/536735
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Currently, instruction validation failure will result in a panic during
encoding. Furthermore, the errors generated do not include the PC or
file/line information that is normally present.
Fix this by:
- Tracking and printing the *obj.Prog associated with the instruction,
including the assembly instruction/opcode if it differs. This provides
the standard PC and file/line prefix, which is also expected by assembly
error end-to-end tests.
- Not proceeding with assembly if errors exist - with the current design,
errors are identified during validation, which is run via preprocess.
Attempts to encode invalid instructions will intentionally panic.
Add some additional riscv64 encoding errors, now that we can actually do so.
Change-Id: I64a7b83680c4d12aebdc96c67f9df625b5ef90d3
Reviewed-on: https://go-review.googlesource.com/c/go/+/523459
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For leaf but nonzero-frame functions.
Currently we're not restoring it properly. We also need to restore
it before popping the stack frame, so that the frame won't get
clobbered by a signal handler in the meantime.
Fixes #63830
Needs a test, but I'm not at all sure how we would actually do that. Leaving for inspiration.
Change-Id: I273a25f2a838f05a959c810145cccc5428eaf164
Reviewed-on: https://go-review.googlesource.com/c/go/+/538635
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Allow SUB and SUBW to be specified with a constant, which are mapped
to ADDI and ADDIW with negated values.
Change-Id: I7dc55692febc81ea87393b0a3a7d23a43c30313b
Reviewed-on: https://go-review.googlesource.com/c/go/+/538915
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Currently, the offset of JALR is zero all the time, which is transformed
from JAL with over ±1MB offset. This causes the segment fault for the
wrong address.
Change-Id: I4dcb3eb13bd1ea71e9eb27f07c03ffec376608ab
Reviewed-on: https://go-review.googlesource.com/c/go/+/538135
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"OR $0, R31, R31" is the execution serializing nop called "exser"
on ISA 3.1 processors such as Power10.
In general, the "OR $0, Rx, Rx" where Rx != 0 form should be avoided
unless used explicitly for the uarch side-effects.
Change-Id: Id76e3a703c902676ba4a3ffb64dd90dad9a320bf
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Refactor maskgen into decodeMask32. This is derived from
from combining encodePPC64RotateMask and isWordRotateMask.
Also, truncate me returned from decodeMask32/64 to
be within range of [0,32/64).
Change-Id: Ie9efff93d400b3066ac85276b1ad3c57c2fcf31b
Reviewed-on: https://go-review.googlesource.com/c/go/+/536298
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Running 'go fix' on the cmd+std packages handled much of this change.
Also update code generators to use only the new go:build lines,
not the old +build ones.
For #41184.
For #60268.
Change-Id: If35532abe3012e7357b02c79d5992ff5ac37ca23
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Converting and verifying a bitmask can be done much quicker
and simpler. Since this touches the MD-form opcodes, cleanup
their encoding too.
Change-Id: I9b1c1fdc4c9622e489ff6cf8181c5b647afae7c9
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Change-Id: I36a0f0989d37bef45ea8778da799b56a7e9a0c30
Reviewed-on: https://go-review.googlesource.com/c/go/+/529515
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Add a new form of RLDC which maps directly to the ISA definition
of rldc: RLDC Rs, $sh, $mb, Ra. This is used to generate mask
constants described below.
Using MOVD $-1, Rx; RLDC Rx, $sh, $mb, Rx, any mask constant
can be generated. A mask is a contiguous series of 1 bits, which
may wrap.
Change-Id: Ifcaae1114080ad58b5fdaa3e5fc9019e2051f282
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The Windows unhandled exception mechanism fails to call the callback
set in SetUnhandledExceptionFilter if the stack can't be correctly
unwound.
Some cgo glue code was not properly chaining the frame pointer, making
the stack unwind to fail in case of an exception inside a cgo call.
This CL fix that and adds a test case to avoid regressions.
Fixes #50951
Change-Id: Ic782b5257fe90b05e3def8dbf0bb8d4ed37a190b
Reviewed-on: https://go-review.googlesource.com/c/go/+/525475
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Check for shifted 16b constants, and transform them to avoid the load
penalty. This should be much faster than loading, and reduce binary
size by reducing the constant pool size.
Change-Id: I6834e08be7ca88e3b77449d226d08d199db84299
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For constant signed values which require 34b to represent,
the assembler will generate a pli instruction on
linux/power10/PPC64 instead of loading a constant.
Similarly, ADD is extended to support 34b signed constants.
On linux/power10/PPC64, this generates a paddi instruction.
For assembler consistency, a second form is added if paddi
cannot be used. The second form is provided for assembly
writers.
Change-Id: I98144306af766b02fbbe36b72856a23cdf51d247
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Change-Id: I6365cdf22ad5e669908519d0ee8b78d76ae8f1b9
Reviewed-on: https://go-review.googlesource.com/c/go/+/532075
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The end-to-end asm tests reinitialize the assembler using different
GOPPC64 values. This caused duplicate entries to amass from the
prefix and generated optab entries. This bug only affects the
asm end-to-end tests.
On reinitialization, optab contains the previous prefixedOptab
and optabGen entries, not just the initial values. Rework the
initialization to avoid the stale optab entries.
Change-Id: I310499915a5272ed0174ed8135d60788e6b4b716
Reviewed-on: https://go-review.googlesource.com/c/go/+/528316
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Change-Id: Id63e1e5ae7e225e4a6a721673bf2d43b6c398c25
Reviewed-on: https://go-review.googlesource.com/c/go/+/527701
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The riscv64 assembler and linker generate three types of calls.
Most calls are made via a single JAL instruction, however this is
limited to +/-1MB of text. In the case where a call target is
unreachable (or unknown), the JAL targets an AUIPC+JALR trampoline.
All other cases use AUIPC+JALR pairs, including the case where a
single function exceeds 1MB in text size, potentially making it
impossible to reach trampolines.
Currently, the single instruction JAL call is marked with R_RISCV_CALL
and the two instruction AUIPC+JALR call is marked with
R_RISCV_PCREL_ITYPE, which is also used for memory load instructions.
This means that we have no way to identify that the latter is a call.
Switch to using R_RISCV_CALL to mark the AUIPC+JALR pair (aligning
somewhat with the elf.R_RISCV_CALL, which is deprecated in favour of
elf.R_RISCV_CALL_PLT). Add R_RISCV_JAL and use this to mark the single
instruction JAL direct calls. This is clearer and allows us to map
elf.R_RISCV_CALL_PLT to Go's R_RISCV_CALL.
Add all three types to IsDirectCall, so that direct calls are correctly
identified when a function exceeds 1MB of text.
Fixes #62465
Change-Id: Id3eea09688a2b7d6e481eae9ed0aa0d1f9a3a48f
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Change immIFits to return an error in the case that it does not fit.
This allows for deduplication and consistency of error messages.
Additionally, since we've already calculated the min and max values,
we can easily include these in the message. Also provide and use
immEven, for the same reasons.
Change-Id: Ie680558744f3e9bc19d6913c4144ce9ddbd0429c
Reviewed-on: https://go-review.googlesource.com/c/go/+/523458
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If the rotate argument is the constant 0, rlwnm may be generated
instead of rlwinm. In all reasonable cases, this is OK as R0 should
hold 0. However, this could be problematic in some cases when
writing PPC64 assembly.
This consolidates the RLWNM and RLWMI optab entries. Invalid RLWMI
usage is still rejected, however the error will be be slightly
different. The invalid usage will be caught in oprrr instead of oplook.
Change-Id: I9958bd24660fea5f8fc9e3e50d51daa7349e3206
Reviewed-on: https://go-review.googlesource.com/c/go/+/527275
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The UnspillReg code should always be preemptible because all the arg registers will be saved by runtime.asyncpreempt.
Change-Id: Ie36b5d0cdd1275efcb95661354d83be2e1b00a86
Reviewed-on: https://go-review.googlesource.com/c/go/+/526235
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Replace a "fixme" with a more appropriate error. Also invert the condition
so that the error returns early, which is more Go idiomatic.
Change-Id: I03006572c4010fb47037bed3ee1fd7f92bfc20d3
Reviewed-on: https://go-review.googlesource.com/c/go/+/523457
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Change-Id: I68be4110216145ad1fb2e5095e1f2b143f9e69ac
Reviewed-on: https://go-review.googlesource.com/c/go/+/523456
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Rather than handling shift based scaling in two locations, rework logic
so there is a single exit path.
Change-Id: I832b4932d53183736050059a11019ced08281b3b
Reviewed-on: https://go-review.googlesource.com/c/go/+/523455
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Unlike RLWNM, the ISA only supports an immediate rotate operand.
Update optab and opirrr to avoid quietly assembling this insn.
Change-Id: I1472a431cb8a870d55d5fff79ab905c4c459f630
Reviewed-on: https://go-review.googlesource.com/c/go/+/449835
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This CL is to add assembly instruction mnemonics for the following instructions, mainly used in crypto packages.
* KMA - cipher message with authentication
* KMCTR - cipher message with counter
Fixes #61163
Change-Id: Iff9a69911aeb4fab4bca8755b23a106eaebb2332
Reviewed-on: https://go-review.googlesource.com/c/go/+/515195
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Change-Id: I8b3eb51e31139314d222d796b56ab7d42338797f
Reviewed-on: https://go-review.googlesource.com/c/go/+/525315
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Preparatory refactoring before next CL.
Change-Id: I06fb4670b933fddff1a2a70f3cf1eb124cbd86ee
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The old Go object file format used linker symbols like "gofile..foo"
to record references to the filename "foo". But the current object
file format has a dedicated section for file names, so we don't need
these useless prefixes anymore.
Also, change DWARF generation to pass around the src.Pos directly,
rather than the old file symbols, which it just turned back into a
file index before writing out anyway.
Finally, directly record the FileIndex into src.PosBase, so that we
can skip the map lookups.
Change-Id: Ia4a5ebfa95da271f2522e45befdb9f137c16d373
Reviewed-on: https://go-review.googlesource.com/c/go/+/523378
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This adds a modicum of type safety to these APIs, which are otherwise
quite confusing to follow.
Change-Id: I268a9a1a99a47dcfef6dc1e9e5be13673af3fb85
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cmd/asm and cmd/compile now always create symbols with the appropriate
package prefixes, so cmd/internal/dwarf and cmd/internal/obj can stop
worrying about qualifying names itself.
Change-Id: I9aee5d759bf0d41a61722c777e7f66fce957e79e
Reviewed-on: https://go-review.googlesource.com/c/go/+/523338
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This CL changes cmd/internal/obj to also implicitly set
ArgsPointerMaps and ArgInfo for assembly functions that are explicitly
package qualified (e.g., "pkg·name", not just "·name"). This is a
prerequisite for changing cmd/asm to stop emitting `"".`-prefixed
symbol names.
Change-Id: I4e14bc24c87cf4d7114a7aed9beaf0c8d1f9c07f
Reviewed-on: https://go-review.googlesource.com/c/go/+/523335
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We have obj.Link.Pkgpath, so we don't need to pass it redundantly in
places where we already have an *obj.Link.
Also, renaming the parser's "compilingRuntime" field to "allowABI", to
match the "AllowAsmABI" name used by objabi.LookupPkgSpecial.
Finally, push the handling of GOEXPERIMENT_* flags up to cmd/asm's
main entry point, by simply appending them to flags.D.
Change-Id: I6ada134522b0cbc90d35bcb145fbe045338fefb7
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pairs
Implement better classification for load and store pair operations. This in
turn allows us to avoid using pool literals when the offset fits in a 24 bit
unsigned immediate. In this case, the offset can be calculated using two
add immediate instructions, rather than loading the offset from the pool
literal and then adding the offset to the base register. This requires the
same number of instructions, however avoids a load from memory and does
not require the offset to be stored in the literal pool.
Updates #59615
Change-Id: I316ec3d54f1d06ae9d930e98d0c32471775fcb26
Reviewed-on: https://go-review.googlesource.com/c/go/+/515615
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Load large constants into vector registers from rodata, instead of placing them
in the literal pool. This treats VMOVQ/VMOVD/VMOVS the same as FMOVD/FMOVS and
makes use of the existing mechanism for storing values in rodata. Two additional
instructions are required for a load, however these instructions are used
infrequently and already have a high latency.
Updates #59615
Change-Id: I54226730267689963d73321e548733ae2d66740e
Reviewed-on: https://go-review.googlesource.com/c/go/+/515617
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Make it possible to internally link cgo on riscv64, which also adds
support for SDYNIMPORT calls without external linking being required.
This reduces the time of an ./all.bash run on a Sifive Hifive Unleashed by
approximately 20% (~140 minutes down to ~110 minutes).
Change-Id: I43f1348de31672718ae8676cc82f6fdc1dfee054
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Change-Id: I31ba6696e124dccf37d674d090fdf04ba0a049a3
Reviewed-on: https://go-review.googlesource.com/c/go/+/515616
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