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2026-02-03all: prealloc slice with possible minimum capabilitiesShulhan
2025-12-23cmd/asm/internal/asm: run riscv64 end-to-end tests for each profileJoel Sing
Currently, the end-to-end tests are only run for the profile set via GORISCV64. Run each of the end-to-end tests for each profile, increasing test coverage. Also rename tests to be RISCV64 specific, rather than RISCV. Change-Id: I15a70939064122c79ec5f2edcda1fa2a47c8cc95 Reviewed-on: https://go-review.googlesource.com/c/go/+/731921 Auto-Submit: Joel Sing <joel@sing.id.au> Reviewed-by: Cherry Mui <cherryyz@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Michael Knyszek <mknyszek@google.com> Reviewed-by: Mark Ryan <markdryan@rivosinc.com> Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com>
2025-12-23cmd/asm/internal/asm: abort end to end test if assembly failedJoel Sing
If errors are encountered during assembly, do not attempt to perform verification. In this case the output is unlikely to be correct and all verification fails, which means the real issue gets lost in the noise. Change-Id: I62c1bf09fa025b0df4c06f0bfa424fb5d328184b Reviewed-on: https://go-review.googlesource.com/c/go/+/731920 Reviewed-by: Cherry Mui <cherryyz@google.com> Auto-Submit: Joel Sing <joel@sing.id.au> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Michael Knyszek <mknyszek@google.com>
2025-11-26cmd/internal/obj/loong64: remove the incorrect unsigned instructionsXiaolin Zhao
The loong64 ISA does not support the 32-bit unsigned arithmetic instructions ADDU, SUBU and MULU. Change-Id: Ifa67de9c59aa12d08844189ed23e6daad0cc11ea Reviewed-on: https://go-review.googlesource.com/c/go/+/722760 Reviewed-by: abner chenc <chenguoqi@loongson.cn> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Dmitri Shuralyov <dmitshur@google.com> Reviewed-by: Cherry Mui <cherryyz@google.com>
2025-11-26cmd/internal/obj/loong64: add {,x}vmadd series instructions supportGuoqi Chen
Go asm syntax: VMADD{B, H, W, V} V1, V2, V3 VMSUB{B, H, W, V} V1, V2, V3 XVMADD{B, H, W, V} X1, X2, X3 XVMSUB{B, H, W, V} X1, X2, X3 VMADDWEV{HB, WH, VW,QV}{,U} V1, V2, V3 VMADDWOD{HB, WH, VW,QV}{,U} V1, V2, V3 XVMADDWEV{HB, WH, VW,QV}{,U} X1, X2, X3 XVMADDWOD{HB, WH, VW,QV}{,U} X1, X2, X3 VMADDWEV{HBUB, WHUH, VWUW, QVUV} V1, V2, V3 VMADDWOD{HBUB, WHUH, VWUW, QVUV} V1, V2, V3 XVMADDWEV{HBUB, WHUH, VWUW, QVUV} X1, X2, X3 XVMADDWOD{HBUB, WHUH, VWUW, QVUV} X1, X2, X3 Equivalent platform assembler syntax: vmadd.{b,h,w,d} v3, v2, v1 vmsub.{b,h,w,d} v3, v2, v1 xvmadd.{b,h,w,d} x3, x2, x1 xvmsub.{b,h,w,d} x3, x2, x1 vmaddwev.{h.b, w.h, d.w, q.d}{,u} v3, v2, v1 vmaddwod.{h.b, w.h, d.w, q.d}{,u} v3, v2, v1 xvmaddwev.{h.b, w.h, d.w, q.d}{,u} x3, x2, x1 xvmaddwod.{h.b, w.h, d.w, q.d}{,u} x3, x2, x1 vmaddwev.{h.bu.b, d.wu.w, d.wu.w, q.du.d} v3, v2, v1 vmaddwod.{h.bu.b, d.wu.w, d.wu.w, q.du.d} v3, v2, v1 xvmaddwev.{h.bu.b, d.wu.w, d.wu.w, q.du.d} x3, x2, x1 xvmaddwod.{h.bu.b, d.wu.w, d.wu.w, q.du.d} x3, x2, x1 Change-Id: I2f4aae51045e1596d4744e525a1589586065cf8e Reviewed-on: https://go-review.googlesource.com/c/go/+/724200 Reviewed-by: Cherry Mui <cherryyz@google.com> Reviewed-by: Meidan Li <limeidan@loongson.cn> Reviewed-by: Dmitri Shuralyov <dmitshur@google.com> Reviewed-by: sophie zhao <zhaoxiaolin@loongson.cn> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Auto-Submit: abner chenc <chenguoqi@loongson.cn>
2025-11-26cmd/internal/obj/loong64: add aliases to 32-bit arithmetic instructionsXiaolin Zhao
Both the MULW and MUL instructions point to the mul.w instruction in the loong64 ISA. Previously, MULW was not encoded; now it is encoded and used as an alias for MUL. The same applies to the following instructions: ADD, SUB, DIV. For consistency, we have added additional aliases for DIVU, REM and REMU. Change-Id: Iba201a3c4c2893ff7d301ef877fad9c81e54291b Reviewed-on: https://go-review.googlesource.com/c/go/+/721523 Reviewed-by: Cherry Mui <cherryyz@google.com> Auto-Submit: abner chenc <chenguoqi@loongson.cn> Reviewed-by: abner chenc <chenguoqi@loongson.cn> Reviewed-by: Meidan Li <limeidan@loongson.cn> Reviewed-by: Dmitri Shuralyov <dmitshur@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
2025-11-25cmd/internal/obj/loong64: add {,X}V{ADD,SUB}W{EV,OD}.{H.B,W.H,D.W,Q.D}{,U} ↵Guoqi Chen
instructions support Go asm syntax: VADDWEV{HB, WH, VW, QV}{,U} V1, V2, V3 VSUBWEV{HB, WH, VW, QV}{,U} V1, V2, V3 VADDWOD{HB, WH, VW, QV}{,U} V1, V2, V3 VSUBWOD{HB, WH, VW, QV}{,U} V1, V2, V3 XVADDWEV{HB, WH, VW, QV}{,U} X1, X2, X3 XVSUBWEV{HB, WH, VW, QV}{,U} X1, X2, X3 XVADDWOD{HB, WH, VW, QV}{,U} X1, X2, X3 XVSUBWOD{HB, WH, VW, QV}{,U} X1, X2, X3 Equivalent platform assembler syntax: vaddwev.{h.b, w.h, d.w, q.d}{,u} V3, V2, V1 vsubwev.{h.b, w.h, d.w, q.d}{,u} V3, V2, V1 vaddwod.{h.b, w.h, d.w, q.d}{,u} V3, V2, V1 vsubwod.{h.b, w.h, d.w, q.d}{,u} V3, V2, V1 xvaddwev.{h.b, w.h, d.w, q.d}{,u} X3, X2, X1 xvsubwev.{h.b, w.h, d.w, q.d}{,u} X3, X2, X1 xvaddwod.{h.b, w.h, d.w, q.d}{,u} X3, X2, X1 xvsubwod.{h.b, w.h, d.w, q.d}{,u} X3, X2, X1 Change-Id: I407dc65b32b89844fd303e265a99d8aafdf922ec Reviewed-on: https://go-review.googlesource.com/c/go/+/723620 Reviewed-by: Cherry Mui <cherryyz@google.com> Reviewed-by: Meidan Li <limeidan@loongson.cn> Reviewed-by: sophie zhao <zhaoxiaolin@loongson.cn> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Mark Freeman <markfreeman@google.com>
2025-11-20cmd/internal/obj/loong64: add {,X}VSLT.{B/H/W/V}{,U} instructions supportGuoqi Chen
Go asm syntax: VSLT{B,H,W,V} V1, V2, V3 VSLT{B,H,W,V}U V1, V2, V3 VSLT{B,H,W,V} $-2, V2, V3 VSLT{B,H,W,V}U $8, V2, V3 XVSLT{B,H,W,V} X1, X2, X3 XVSLT{B,H,W,V}U X1, X2, X3 XVSLT{B,H,W,V} $-16, X2, X3 XVSLT{B,H,W,V}U $31, X2, X3 Equivalent platform assembler syntax: vslt.{b,h,w,d} v3, v2, v1 vslt.{b,h,w,d}u v3, v2, v1 vslti.{b,h,w,d} v3, v2, $-2 vslti.{b,h,w,d}u v3, v2, $8 xvslt.{b,h,w,d} x3, x2, x1 xvslt.{b,h,w,d}u x3, x2, x1 xvslti.{b,h,w,d} x3, x2, $-16 xvslti.{b,h,w,d}u x3, x2, $31 Change-Id: Iccfb65c0c19b62d2c5ec279a077393c68e1bf7d4 Reviewed-on: https://go-review.googlesource.com/c/go/+/721620 Reviewed-by: Mark Freeman <markfreeman@google.com> Reviewed-by: Junyang Shao <shaojunyang@google.com> Reviewed-by: Meidan Li <limeidan@loongson.cn> Reviewed-by: sophie zhao <zhaoxiaolin@loongson.cn> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
2025-11-20cmd/internal/obj/x86: handle global reference in From3 in dynlink modeCherry Mui
In dynlink mode, we rewrite reference to a global variable to a load from the GOT. Currently this code does not handle the case that the global reference is in From3 of a Prog. Most instructions don't expect a memory operand in From3, but some do, like VGF2P8AFFINEQB. Handle this case. Change-Id: Ibb6773606e6967bcc629d9ef5dac6e050f4008ef Reviewed-on: https://go-review.googlesource.com/c/go/+/722181 LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Junyang Shao <shaojunyang@google.com>
2025-11-19cmd/internal/obj/loong64: add MULW.D.W[U] instructionsXiaolin Zhao
Go asm syntax: MULWVW RK, RJ, RD MULWVWU RK, RJ, RD Equivalent platform assembler syntax: mulw.d.w rd, rj, rk mulw.d.wu rd, rj, rk Change-Id: Ie46a21904a4c25d04200b0663f83072c38a76c6f Reviewed-on: https://go-review.googlesource.com/c/go/+/721521 LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: abner chenc <chenguoqi@loongson.cn> Reviewed-by: Meidan Li <limeidan@loongson.cn> Reviewed-by: Mark Freeman <markfreeman@google.com> Reviewed-by: Keith Randall <khr@google.com>
2025-11-18cmd/asm,cmd/compile,cmd/internal/obj/riscv: use compressed instructions on ↵Joel Sing
riscv64 Make use of compressed instructions on riscv64 - add a compress pass to the end of the assembler, which replaces non-compressed instructions with compressed alternatives if possible. Provide a `compressinstructions` compiler and assembler debug flag, such that the compression pass can be disabled via `-asmflags=all=-d=compressinstructions=0` and `-gcflags=all=-d=compressinstructions=0`. Note that this does not prevent the explicit use of compressed instructions via assembly. Note that this does not make use of compressed control transfer instructions - this will be implemented in later changes. Reduces the text size of a hello world binary by ~121KB and reduces the text size of the go binary on riscv64 by ~1.21MB (between 8-10% in both cases). Updates #71105 Cq-Include-Trybots: luci.golang.try:gotip-linux-riscv64 Change-Id: I24258353688554042c2a836deed4830cc673e985 Reviewed-on: https://go-review.googlesource.com/c/go/+/523478 Reviewed-by: Mark Ryan <markdryan@rivosinc.com> Reviewed-by: Mark Freeman <markfreeman@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Cherry Mui <cherryyz@google.com>
2025-11-13cmd/asm,cmd/internal/obj/riscv: add support for riscv compressed instructionsJoel Sing
Add support for compressed instructions in the RISC-V assembler. This implements instruction validation and encoding for all instructions in the "C" extension. It is worth noting that the validation and encoding of these instructions is far more convoluted then the typical instruction validation and encoding. While the current model has been followed for now, it would be worth revisiting this in the future and potentially switching to a table based or even per-instruction implementation. Additionally, the current instruction encoding is lacking some of the bits needed for compressed instructions - this is solved by compressedEncoding, which provides the missing information. This will also be addressed in the future, likely by changing the instruction encoding format. Updates #71105 Change-Id: I0f9359d63f93ebbdc6e708e79429b2d61eae220d Reviewed-on: https://go-review.googlesource.com/c/go/+/713020 Reviewed-by: Mark Ryan <markdryan@rivosinc.com> Reviewed-by: Junyang Shao <shaojunyang@google.com> Reviewed-by: Cherry Mui <cherryyz@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com>
2025-11-12cmd/internal/obj/loong64: add {,X}VS{ADD,SUB}.{B/H/W/V}{,U} instructions supportGuoqi Chen
Go asm syntax: VSADD{B,H,W,V} V1, V2, V3 VSADD{B,H,W,V}U V1, V2, V3 VSSUB{B,H,W,V} V1, V2, V3 VSSUB{B,H,W,V}U V1, V2, V3 XVSADD{B,H,W,V} X1, X2, X3 XVSADD{B,H,W,V}U X1, X2, X3 XVSSUB{B,H,W,V} X1, X2, X3 XVSSUB{B,H,W,V}U X1, X2, X3 Equivalent platform assembler syntax: vsadd.{b,h,w,d} v3, v2, v1 vsadd.{b,h,w,d}u v3, v2, v1 vssub.{b,h,w,d} v3, v2, v1 vssub.{b,h,w,d}u v3, v2, v1 xvsadd.{b,h,w,d} x3, x2, x1 xvsadd.{b,h,w,d}u x3, x2, x1 xvssub.{b,h,w,d} x3, x2, x1 xvssub.{b,h,w,d}u x3, x2, x1 Change-Id: Iab8c1a9bdc4940598936f3beac846466e913ffa2 Reviewed-on: https://go-review.googlesource.com/c/go/+/719200 LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Meidan Li <limeidan@loongson.cn> Reviewed-by: Junyang Shao <shaojunyang@google.com> Reviewed-by: sophie zhao <zhaoxiaolin@loongson.cn> Reviewed-by: Michael Pratt <mpratt@google.com>
2025-11-11std,cmd: go fix -any std cmdAlan Donovan
This change mechanically replaces all occurrences of interface{} by 'any' (where deemed safe by the 'any' modernizer) throughout std and cmd, minus their vendor trees. Since this fix is relatively numerous, it gets its own CL. Also, 'go generate go/types'. Change-Id: I14a6b52856c3291c1d27935409bca8d5fd4242a2 Reviewed-on: https://go-review.googlesource.com/c/go/+/719702 Commit-Queue: Alan Donovan <adonovan@google.com> Reviewed-by: Dmitri Shuralyov <dmitshur@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Dmitri Shuralyov <dmitshur@golang.org> Auto-Submit: Alan Donovan <adonovan@google.com>
2025-11-10cmd/internal/obj/arm64: shorten constant integer loadsKeith Randall
Large integer constants can take up to 4 instructions to encode. We can encode some large constants with a single instruction, namely those which are bit patterns (repetitions of certain runs of 0s and 1s). Often the constants we want to encode are *close* to those bit patterns, but don't exactly match. For those, we can use 2 instructions, one to load the close-by bit pattern and one to fix up any mismatches. The constants we use to strength reduce divides often fit this pattern. For unsigned divides by 1 through 15, this CL applies to the constant for N=3,5,6,10,12,15. Triggers 17 times in hello world. Change-Id: I623abf32961fb3e74d0a163f6822f0647cd94499 Reviewed-on: https://go-review.googlesource.com/c/go/+/717900 Auto-Submit: Keith Randall <khr@golang.org> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Keith Randall <khr@google.com> Reviewed-by: Cherry Mui <cherryyz@google.com>
2025-11-05cmd/internal/obj/loong64: add {,X}VSHUF.{B/H/W/V} instructions supportGuoqi Chen
Go asm syntax: VSHUFB V1, V2, V3, V4 XVSHUFB X1, X2, X3, X4 VSHUF{H/W/V} V1, V2, V3 XVSHUF{H/W/V} X1, X2, X3 Equivalent platform assembler syntax: vshuf.b v4, v3, v2, v1 xvshuf.b x4, x3, x2, x1 vshuf.{h/w/d} v3, v2, v1 xvshuf.{h/w/d} x3, x2, x1 Change-Id: I8983467495f587cf46083fd81cb024400c7dc2a7 Reviewed-on: https://go-review.googlesource.com/c/go/+/716804 Reviewed-by: Meidan Li <limeidan@loongson.cn> Reviewed-by: Michael Knyszek <mknyszek@google.com> Reviewed-by: Michael Pratt <mpratt@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: sophie zhao <zhaoxiaolin@loongson.cn>
2025-11-05cmd/internal/obj/loong64: add {,X}VEXTRINS.{B,H,W,V} instruction supportGuoqi Chen
Go asm syntax: VEXTRINS{B,H,W,V} $0x1b, vj,vd XVEXTRINS{B,H,W,V} $0x1b, vj,vd Equivalent platform assembler syntax: vextrins.{b,h,w,d} vd, vj, $0x1b xvextrins.{b,h,w,d} xd, xj, $0x1b Change-Id: Ibc0bf926befaa2f810cfedd9a40f7ad9a6a9d7fc Reviewed-on: https://go-review.googlesource.com/c/go/+/716803 LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: sophie zhao <zhaoxiaolin@loongson.cn> Reviewed-by: Michael Pratt <mpratt@google.com> Reviewed-by: Meidan Li <limeidan@loongson.cn> Reviewed-by: Michael Knyszek <mknyszek@google.com>
2025-11-03cmd/internal/obj/loong64: using {xv,v}slli.d to perform copying between ↵Guoqi Chen
vector registers Go asm syntax: VMOVQ Vj, Vd XVMOVQ Xj, Xd Equivalent platform assembler syntax: vslli.d vd, vj, 0x0 xvslli.d xd, xj, 0x0 Change-Id: Ifddc3d4d3fbaa6fee2e079bf2ebfe96a2febaa1c Reviewed-on: https://go-review.googlesource.com/c/go/+/716801 Reviewed-by: Michael Knyszek <mknyszek@google.com> Reviewed-by: Michael Pratt <mpratt@google.com> Reviewed-by: Meidan Li <limeidan@loongson.cn> Reviewed-by: sophie zhao <zhaoxiaolin@loongson.cn> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
2025-11-03cmd/internal/obj/loong64: add VPERMI.W, XVPERMI.{W,V,Q} instruction supportGuoqi Chen
Go asm syntax: VPERMIW $0x1b, vj, vd XVPERMI{W,V,Q} $0x1b, xj, xd Equivalent platform assembler syntax: vpermi.w vd, vj, $0x1b xvpermi.{w,d,q} xd, xj, $0x1b Change-Id: Ie23b2fdd09b4c93801dc804913206f1c5a496268 Reviewed-on: https://go-review.googlesource.com/c/go/+/716800 Reviewed-by: Michael Pratt <mpratt@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Meidan Li <limeidan@loongson.cn> Reviewed-by: sophie zhao <zhaoxiaolin@loongson.cn> Reviewed-by: Michael Knyszek <mknyszek@google.com>
2025-11-03cmd/internal/obj: support arm64 FMOVQ large offset encodingAlexander Musman
Support arm64 FMOVQ with large offset in immediate which is encoded using register offset instruction in opldrr or opstrr. This will help allowing folding immediate into new ssa ops FMOVQload and FMOVQstore. For example: FMOVQ F0, -20000(R0) is encoded as following: MOVD 3(PC), R27 FMOVQ F0, (R0)(R27) RET ffff b1e0 # constant value Change-Id: Ib71f92f6ff4b310bda004a440b1df41ffe164523 Reviewed-on: https://go-review.googlesource.com/c/go/+/716960 Reviewed-by: Cherry Mui <cherryyz@google.com> Auto-Submit: Michael Pratt <mpratt@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Michael Pratt <mpratt@google.com>
2025-10-27cmd/internal/obj, cmd/asm: reclassify the offset of memory access operations ↵Xiaolin Zhao
on loong64 This CL also fixes the encoding error of LL/SC[V] instruction and adds the handling of offset greater than 16 bits in MOV{W/V}P instructions. Change-Id: I7a8fab4b68a6839da81c5e59af1f42289d00ef61 Reviewed-on: https://go-review.googlesource.com/c/go/+/706435 Reviewed-by: David Chase <drchase@google.com> Reviewed-by: Meidan Li <limeidan@loongson.cn> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: abner chenc <chenguoqi@loongson.cn> Reviewed-by: Michael Knyszek <mknyszek@google.com>
2025-10-23cmd/internal/obj/riscv: simplify validation and encoding of raw instructionsJoel Sing
Use wantImmU/immU rather than handrolling the same code. This also corrects the validation output - add tests to ensure this is the case. Change-Id: Id48f459c7c0de09ddde7a10506f66a3a269f325f Reviewed-on: https://go-review.googlesource.com/c/go/+/702396 LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: David Chase <drchase@google.com> Reviewed-by: Cherry Mui <cherryyz@google.com>
2025-10-21all: eliminate unnecessary type conversionsJes Cok
Found by github.com/mdempsky/unconvert Change-Id: I88ce10390a49ba768a4deaa0df9057c93c1164de GitHub-Last-Rev: 3b0f7e8f74f58340637f33287c238765856b2483 GitHub-Pull-Request: golang/go#75974 Reviewed-on: https://go-review.googlesource.com/c/go/+/712940 LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Keith Randall <khr@golang.org> Auto-Submit: Keith Randall <khr@golang.org> Reviewed-by: Keith Randall <khr@google.com> Reviewed-by: David Chase <drchase@google.com>
2025-10-20cmd/asm: fix typo in commentJoel Sing
Change-Id: I1a7933bce70bcae1f93a45c6810da60d269f48f3 Reviewed-on: https://go-review.googlesource.com/c/go/+/713000 LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Michael Pratt <mpratt@google.com> Reviewed-by: Keith Randall <khr@google.com> Auto-Submit: Joel Sing <joel@sing.id.au>
2025-10-15cmd/internal/obj: move ARM64RegisterExtension from cmd/asm/internal/archVasily Leonenko
Change-Id: Iab41674953655efa7be3d306dfb3f5be486be501 Reviewed-on: https://go-review.googlesource.com/c/go/+/701455 Reviewed-by: Cherry Mui <cherryyz@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Keith Randall <khr@google.com>
2025-10-14cmd/internal/obj/arm64: add support for PAC instructionsBill Roberts
Add support for the Pointer Authentication Code instructions required for the ELF ABI when enabling PAC aware binaries. This allows for assembly writers to add PAC instructions where needed to support this ABI. Follow up work is to enable the compiler to emit these instructions in the appropriate places. The TL;DR for the Linux ABI is that the prologue of a function that pushes the link register (LR) to the stack, signs the LR with a key managed by the operating system and hardware using a PAC instruction, like "paciasp". The function epilog, when restoring the LR from the stack will verify the signature, using an instruction like "autiasp". This helps prevents attackers from modifying the return address on the stack, a common technique for ROP attacks. Details on PAC can be found here: - https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/enabling-pac-and-bti-on-aarch64 - https://developer.arm.com/documentation/109576/0100/Pointer-Authentication-Code The ABI details can be found here: - https://github.com/ARM-software/abi-aa/blob/main/aaelf64/aaelf64.rst Change-Id: I4516ed1294d19f9ff9d278833d542821b6642aa9 Reviewed-on: https://go-review.googlesource.com/c/go/+/676675 Reviewed-by: Cherry Mui <cherryyz@google.com> Reviewed-by: Joel Sing <joel@sing.id.au> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Dmitri Shuralyov <dmitshur@google.com>
2025-09-24cmd/internal/obj/riscv: add support for vector unit-stride fault-only-first ↵wangboyao
load instructions Add support for vector unit-stride fault-only-first load instructions to the RISC-V assembler. This includes vle8ff, vle16ff, vle32ff and vle64ff. Change-Id: I5575a1ea155663852f92194fb79f08b5d52203de Reviewed-on: https://go-review.googlesource.com/c/go/+/690115 Reviewed-by: Junyang Shao <shaojunyang@google.com> Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com> Reviewed-by: Cherry Mui <cherryyz@google.com> Reviewed-by: Joel Sing <joel@sing.id.au> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
2025-09-17cmd/internal/obj/riscv: add support for Zicond instructionslxq015
This patch implement assembler for the Zicond extension: CZEROEQZ and CZERONEZ. Follow-up to CL 631576 Updates #75350 Change-Id: Icf4be131fe61c3b7a3bde4811cf42dc807660907 GitHub-Last-Rev: 6539cc86cbf3c49c3247ed935bcbbb31bb886dea GitHub-Pull-Request: golang/go#75408 Reviewed-on: https://go-review.googlesource.com/c/go/+/702677 Reviewed-by: Mark Freeman <markfreeman@google.com> Reviewed-by: Joel Sing <joel@sing.id.au> Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com> Reviewed-by: Michael Knyszek <mknyszek@google.com> Reviewed-by: Mark Ryan <markdryan@rivosinc.com> TryBot-Bypass: Joel Sing <joel@sing.id.au>
2025-09-16cmd/internal/obj/riscv: improve handling of float point movesJoel Sing
Translate moves from an integer register to a floating point register, or from a floating point register to an integer register, to the appropriate move instruction (i.e. FMVXW/FMVWX/FMVXD/FMVDX). Add support for MOVF with a constant - we previously added support for MOVD but not for MOVF. Add special handling for 0.0, which we can translate to a move from the zero register to a floating point register (leveraging the above mentioned change). Change-Id: If8df2f5610e69b4ec0af85efb884951024685f5b Reviewed-on: https://go-review.googlesource.com/c/go/+/703216 Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com> Reviewed-by: Mark Freeman <markfreeman@google.com> Reviewed-by: Michael Knyszek <mknyszek@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Mark Ryan <markdryan@rivosinc.com>
2025-09-15cmd/internal/obj/riscv: implement vector segment load/store instructionswangboyao
https://github.com/riscv/riscv-opcodes/pull/361. After this pr was merged, riscv-opcode can generate RVV segment load/store instructions for Go. Implement vector segment load/store instuctions. Change-Id: I154bb75be70c0a45e2279a75c67f68b5bb57c36e Reviewed-on: https://go-review.googlesource.com/c/go/+/691695 Reviewed-by: Mark Freeman <markfreeman@google.com> Reviewed-by: Michael Knyszek <mknyszek@google.com> Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
2025-09-15cmd/asm: add double precision comparision testcases for riscv64Meng Zhuo
Change-Id: If8e03dfdb332a22ec9c6a0021d7e7955520f3ddc Reviewed-on: https://go-review.googlesource.com/c/go/+/702136 Reviewed-by: Mark Freeman <markfreeman@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Mark Ryan <markdryan@rivosinc.com> Reviewed-by: Joel Sing <joel@sing.id.au> Reviewed-by: Michael Knyszek <mknyszek@google.com>
2025-09-12cmd/asm, cmd/internal/obj: add riscv64 generic CSR opsMark Ryan
Support is added for the generic RISC-V CSR operations; CSRRC, CSRRCI, CSRRS, CSRRSI, CSRRW, CSRRWI. These instructions require special handling as their second operand is a symbolic CSR register name and not an immediate value or a register. CSR names are implemented as special operands. RISC-V CSRs are not currently saved and restored when a go routine is asynchronously pre-empted so it is only safe to use these instructions in hand written assembler. Note that CSRRS was already partially supported by the assembler so this restriction predates this commit. We mention it here as this commit makes CSRRS much easier to use. Change-Id: I9ff8d804328b418a879d463e7d9cc31f489c7a00 Reviewed-on: https://go-review.googlesource.com/c/go/+/630519 Reviewed-by: Junyang Shao <shaojunyang@google.com> Reviewed-by: Joel Sing <joel@sing.id.au> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com> Reviewed-by: Michael Pratt <mpratt@google.com>
2025-09-04cmd/internal/obj/loong64: add ADDU16I.D instruction supportXiaolin Zhao
Go asm syntax: ADDV16 $(1<<16), R4, R5 Equivalent platform assembler syntax: addu16i.d r5, r4, $1 Change-Id: Ica4a4e779d0a107cda3eade86027abd6458779a4 Reviewed-on: https://go-review.googlesource.com/c/go/+/699056 Reviewed-by: abner chenc <chenguoqi@loongson.cn> Reviewed-by: Michael Pratt <mpratt@google.com> Auto-Submit: Michael Pratt <mpratt@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Cherry Mui <cherryyz@google.com>
2025-09-04cmd/internal/obj/loong64: fix the usage of offset in the instructions ↵Xiaolin Zhao
[X]VLDREPL.{B/H/W/D} The previously defined usage of offset was ambiguous and not easy to understand. For example, to fetch 4 bytes of data from the address base+8 and broadcast it to each word element of vector register V5, the assembly implementation is as follows: previous: VMOVQ 2(base), V5.W4 current: VMOVQ 8(base), V5.W4 Change-Id: I8bc84e35033ab63bd10f4c61618789f94314f78c Reviewed-on: https://go-review.googlesource.com/c/go/+/699875 Reviewed-by: Cherry Mui <cherryyz@google.com> Reviewed-by: Michael Pratt <mpratt@google.com> Reviewed-by: abner chenc <chenguoqi@loongson.cn> Auto-Submit: Michael Pratt <mpratt@google.com> Reviewed-by: Meidan Li <limeidan@loongson.cn> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
2025-08-31cmd/internal/obj/loong64: add LDPTR.{W/D} and STPTR.{W/D} instructions supportXiaolin Zhao
Go asm syntax: MOVWP 4(R4), R5 MOVVP 8(R4), R5 MOVWP R4, 12(R5) MOVVP R4, 16(R5) Equivalent platform assembler syntax: ldptr.w r5, r4, $1 ldptr.d r5, r4, $2 stptr.w r4, r5, $3 stptr.d r4, r5, $4 Change-Id: I50a341cee2d875cb7c5da9db08b23799c9dc6c64 Reviewed-on: https://go-review.googlesource.com/c/go/+/699055 Reviewed-by: abner chenc <chenguoqi@loongson.cn> Reviewed-by: Meidan Li <limeidan@loongson.cn> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Carlos Amedee <carlos@golang.org> Reviewed-by: Cherry Mui <cherryyz@google.com>
2025-08-07cmd/internal/obj/loong64: change the immediate range of ALSL{W/WU/V}limeidan
When executing the alsl.w/wu/d family of instructions, the actual shift amount is the immediate value in the instruction encoding plus one. Therefore, this change is made to align the immediate value in the assembly code with the programmer's intended shift amount, and to include the result of the immediate value minus one in the final encoding. Change-Id: Ic82249251878eabde8372e183d841a03f963f9f9 Reviewed-on: https://go-review.googlesource.com/c/go/+/693475 Reviewed-by: Dmitri Shuralyov <dmitshur@google.com> Reviewed-by: Mark Freeman <markfreeman@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: abner chenc <chenguoqi@loongson.cn> Reviewed-by: sophie zhao <zhaoxiaolin@loongson.cn>
2025-08-07cmd/internal/obj/loong64: add support for FSEL instructionXiaolin Zhao
Go asm syntax: FSEL FCC, FK, FJ, FD Equivalent platform assembler syntax: fsel fd, fj, fk, ca Change-Id: If75f16fca0adfc03f4952f8a5143d22da33ed425 Reviewed-on: https://go-review.googlesource.com/c/go/+/693457 LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Meidan Li <limeidan@loongson.cn> Reviewed-by: abner chenc <chenguoqi@loongson.cn> Reviewed-by: Dmitri Shuralyov <dmitshur@google.com> Reviewed-by: Mark Freeman <markfreeman@google.com>
2025-08-05cmd/internal/obj/loong64: add new instructions ALSL{W/WU/V} for loong64limeidan
Go asm syntax: ALSL{W/WU/V} $3, R4, R5, R6 Equivalent platform assembler syntax: alsl.{w/wu/d} $r6, $r4, $r5, 3 Change-Id: Ic8364dfe2753bcea7de6cffe656ca0dde6875766 Reviewed-on: https://go-review.googlesource.com/c/go/+/692136 Reviewed-by: Dmitri Shuralyov <dmitshur@google.com> Reviewed-by: abner chenc <chenguoqi@loongson.cn> Reviewed-by: Mark Freeman <markfreeman@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: sophie zhao <zhaoxiaolin@loongson.cn>
2025-08-05cmd: remove dead codeqiulaidongfeng
Fixes #74076 Change-Id: Icc67b3d4e342f329584433bd1250c56ae8f5a73d Reviewed-on: https://go-review.googlesource.com/c/go/+/690635 Reviewed-by: Alan Donovan <adonovan@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Commit-Queue: Alan Donovan <adonovan@google.com> Reviewed-by: Keith Randall <khr@golang.org> Reviewed-by: Keith Randall <khr@google.com> Auto-Submit: Alan Donovan <adonovan@google.com> Reviewed-by: Dmitri Shuralyov <dmitshur@google.com>
2025-08-03cmd/internal/obj/loong64: add {V,XV}{BITCLR/BITSET/BITREV}[I].{B/H/W/D} ↵Xiaolin Zhao
instructions support Go asm syntax: V{BITCLR/BITSET/BITREV}{B/H/W/V} $1, V2, V3 XV{BITCLR/BITSET/BITREV}{B/H/W/V} $1, X2, X3 V{BITCLR/BITSET/BITREV}{B/H/W/V} VK, VJ, VD XV{BITCLR/BITSET/BITREV}{B/H/W/V} XK, XJ, XD Equivalent platform assembler syntax: v{bitclr/bitset/bitrev}i.{b/h/w/d} v3, v2, $1 xv{bitclr/bitset/bitrev}i.{b/h/w/d} x3, x2, $1 v{bitclr/bitset/bitrev}.{b/h/w/d} vd, vj, vk xv{bitclr/bitset/bitrev}.{b/h/w/d} xd, xj, xk Change-Id: I244f8ae316f72cc7ea01ca0139ac78c5616a3c5b Reviewed-on: https://go-review.googlesource.com/c/go/+/677435 Reviewed-by: Cherry Mui <cherryyz@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: abner chenc <chenguoqi@loongson.cn> Reviewed-by: Mark Freeman <mark@golang.org>
2025-08-03cmd/internal/obj/loong64: add [X]VLDREPL.{B/H/W/D} instructions supportXiaolin Zhao
Go asm syntax: VMOVQ offset(Rj), Vd.<T> XVMOVQ offset(Rj), Xd.<T> <T> can have the following values: B16, H8, W4, V2, B32, H16, W8, V4 Change-Id: I44af51d58bb62649d3fe360b3abb771565e78a8a Reviewed-on: https://go-review.googlesource.com/c/go/+/682895 Reviewed-by: abner chenc <chenguoqi@loongson.cn> Reviewed-by: Michael Knyszek <mknyszek@google.com> Reviewed-by: Meidan Li <limeidan@loongson.cn> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Mark Freeman <mark@golang.org>
2025-07-30cmd/compile: add floating point min/max intrinsics on s390xMichael Munday
Add the VECTOR FP (MINIMUM|MAXIMUM) instructions to the assembler and use them in the compiler to implement min and max. Note: I've allowed floating point registers to be used with the single element instructions (those with the W instead of V prefix) to allow easier integration into the compiler. Change-Id: I5f80a510bd248cf483cce95f1979bf63fbae7de6 Reviewed-on: https://go-review.googlesource.com/c/go/+/684715 Reviewed-by: Keith Randall <khr@golang.org> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Mark Freeman <mark@golang.org> Reviewed-by: Keith Randall <khr@google.com>
2025-07-24cmd/internal/obj/s390x: add MVCLE instructionkmvijay
MVCLE (Move Long Extended) instruction is used to move large data storage-to-storage. This change will add MVCLE into the Go asm for s390x architecture. Upcoming PR of runtime/memmove_s390x.s will use this instruction for performance improvement. Change-Id: I3bbb6668c736a36849917887398c74cebb1c3a99 Reviewed-on: https://go-review.googlesource.com/c/go/+/677455 Reviewed-by: Srinivas Pokala <Pokala.Srinivas@ibm.com> Reviewed-by: Keith Randall <khr@golang.org> Auto-Submit: Michael Knyszek <mknyszek@google.com> Reviewed-by: Keith Randall <khr@google.com> Reviewed-by: Michael Munday <mikemndy@gmail.com> Reviewed-by: Vishwanatha HD <vishwanatha.hd@ibm.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Michael Knyszek <mknyszek@google.com>
2025-05-21cmd/internal/obj/riscv: fix vector integer multiply addMark Ryan
The RISC-V integer vector multiply add instructions are not encoded correctly; the first and second arguments are swapped. For example, the instruction VMACCVV V1, V2, V3 encodes to b620a1d7 or vmacc.vv v3,v1,v2 and not b61121d7 or vmacc.vv v3,v2,v1 as expected. This is inconsistent with the argument ordering we use for 3 argument vector instructions, in which the argument order, as given in the RISC-V specifications, is reversed, and also with the vector FMA instructions which have the same argument ordering as the vector integer multiply add instructions in the "The RISC-V Instruction Set Manual Volume I". For example, in the ISA manual we have the following instruction definitions ; Integer multiply-add, overwrite addend vmacc.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vs2[i]) + vd[i] ; FP multiply-accumulate, overwrites addend vfmacc.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vs2[i]) + vd[i] It's reasonable to expect that the Go assembler would use the same argument ordering for both of these instructions. It currently does not. We fix the issue by switching the argument ordering for the vector integer multiply add instructions to match those of the vector FMA instructions. Change-Id: Ib98e9999617f991969e5c831734b3bb3324439f6 Reviewed-on: https://go-review.googlesource.com/c/go/+/670335 Reviewed-by: Carlos Amedee <carlos@golang.org> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com> Reviewed-by: Cherry Mui <cherryyz@google.com>
2025-05-15cmd/internal/obj/loong64: change the plan9 format of the prefetch ↵Guoqi Chen
instruction PRELDX before: MOVV $n + $offset, Roff PRELDX (Rbase)(Roff), $hint after: PRELDX offset(Rbase), $n, $hint This instruction is supported in CL 671875, but is not actually used Change-Id: I943d488ea6dc77781cd796ef480a89fede666bab Reviewed-on: https://go-review.googlesource.com/c/go/+/673155 Reviewed-by: Meidan Li <limeidan@loongson.cn> Reviewed-by: sophie zhao <zhaoxiaolin@loongson.cn> Reviewed-by: Michael Knyszek <mknyszek@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Cherry Mui <cherryyz@google.com>
2025-05-14cmd/intarnal/obj: add new assembly format for VANDV and VANDB on loong64Xiaolin Zhao
In order to make it easier to write in assembly and to be consistent with the usage of general instructions, a new assembly format is added for the instructions VANDV and VANDB. It also works for instructions XVAND{V,B}, [X]V{OR,XOR,NOR,ANDN,ORN}V and [X]V{OR,XOR,NOR}B. Change-Id: Ia75d607ac918950e58840ec627aaf0be45d837fe Reviewed-on: https://go-review.googlesource.com/c/go/+/671316 Reviewed-by: Cherry Mui <cherryyz@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Michael Knyszek <mknyszek@google.com>
2025-05-12cmd/internal/obj/loong64: Add preld{,x} instructions supportGuoqi Chen
Go asm syntax: PRELD 16(R4), $8 PRELDX (R4)(R5), $8 Equivalent platform assembler syntax: preld $8, $r4, 16 preldx $8, $r4, $r5 Change-Id: Ie81d22ebaf4153388a7e9d8fa0f618a0ae7a1c9f Reviewed-on: https://go-review.googlesource.com/c/go/+/671875 Reviewed-by: sophie zhao <zhaoxiaolin@loongson.cn> Reviewed-by: Meidan Li <limeidan@loongson.cn> Reviewed-by: Cherry Mui <cherryyz@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Michael Knyszek <mknyszek@google.com>
2025-05-11cmd/internal/obj/loong64: add [X]VFCLASS.{S/D} instructionsXiaolin Zhao
Go asm syntax: VFCLASS{F/D} VJ, VD XVFCLASS{F/D} XJ, XD Equivalent platform assembler syntax: vfclass.{s/d} vd, vj xvfclass.{s/d} xd, xj Change-Id: Iec373f393be315696d1fefc747a4a5882f993195 Reviewed-on: https://go-review.googlesource.com/c/go/+/670256 Reviewed-by: Cherry Mui <cherryyz@google.com> Reviewed-by: Dustin Turner <dustin.turner44@gmail.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Carlos Amedee <carlos@golang.org> Reviewed-by: abner chenc <chenguoqi@loongson.cn>
2025-05-08cmd/internal/obj/loong64: add [X]VF{ADD/SUB/MUL/DIV}.{S/D} instructionsXiaolin Zhao
Go asm syntax: V{ADD/SUB/MUL/DIV}{F/D} VK, VJ, VD XV{ADD/SUB/MUL/DIV}{F/D} XK, XJ, XD Equivalent platform assembler syntax: vf{add/sub/mul/div}.{s/d} vd, vj, vk xvf{add/sub/mul/div}.{s/d} xd, xj, xk Change-Id: I4607884212167ac97d7b6448ea3c849fc0fdd506 Reviewed-on: https://go-review.googlesource.com/c/go/+/670255 Reviewed-by: abner chenc <chenguoqi@loongson.cn> Reviewed-by: Carlos Amedee <carlos@golang.org> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Cherry Mui <cherryyz@google.com>
2025-05-08cmd/internal/obj/riscv: reject invalid vadc/vsbc encodingsMark Ryan
The RISC-V Instruction Set Manual Volume states that "for vadc and vsbc, the instruction encoding is reserved if the destination vector register is v0". The assembler currently allows instructions like VADCVVM V1, V2, V0, V0 to be assembled. It's not clear what the behaviour of such instructions will be on target hardware so it's best to disallow them. For reference, binutils (2.44-3.fc42) allows the instruction vadc.vvm v0, v4, v8, v0 to be assembled and the instruction actually executes on a Banana PI F3 without crashing. However, clang (20.1.2) refuses to assemble the instruction, producing the following error. error: the destination vector register group cannot be V0 vadc.vvm v0, v4, v8, v0 ^ Change-Id: Ia913cbd864ae8dbcf9227f69b963c93a99481cff Reviewed-on: https://go-review.googlesource.com/c/go/+/669315 Reviewed-by: Carlos Amedee <carlos@golang.org> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Cherry Mui <cherryyz@google.com> Reviewed-by: Joel Sing <joel@sing.id.au>
generated by cgit v1.3 (git 2.53.0) at 2026-04-15 09:37:14 +0000