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| author | Xiaolin Zhao <zhaoxiaolin@loongson.cn> | 2025-08-21 11:14:27 +0800 |
|---|---|---|
| committer | abner chenc <chenguoqi@loongson.cn> | 2025-08-24 18:14:28 -0700 |
| commit | 44c5956bf7454ca178c596eb87578ea61d6c9dee (patch) | |
| tree | 80603f8c61d46abf650112ff46c0082f38621abb /test/codegen | |
| parent | 0aa8019e943ce49afc2b655ea8d5f55cbaa72cef (diff) | |
| download | go-44c5956bf7454ca178c596eb87578ea61d6c9dee.tar.xz | |
test/codegen: add Mul2 and DivPow2 test for loong64
Change-Id: I29ccd105c5418955146a3f4873162963da489a70
Reviewed-on: https://go-review.googlesource.com/c/go/+/697935
LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
Reviewed-by: abner chenc <chenguoqi@loongson.cn>
Reviewed-by: David Chase <drchase@google.com>
Reviewed-by: Carlos Amedee <carlos@golang.org>
Diffstat (limited to 'test/codegen')
| -rw-r--r-- | test/codegen/floats.go | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/test/codegen/floats.go b/test/codegen/floats.go index 0cee497279..29969c8dc0 100644 --- a/test/codegen/floats.go +++ b/test/codegen/floats.go @@ -19,6 +19,7 @@ func Mul2(f float64) float64 { // amd64:"ADDSD",-"MULSD" // arm/7:"ADDD",-"MULD" // arm64:"FADDD",-"FMULD" + // loong64:"ADDD",-"MULD" // ppc64x:"FADD",-"FMUL" // riscv64:"FADDD",-"FMULD" return f * 2.0 @@ -29,6 +30,7 @@ func DivPow2(f1, f2, f3 float64) (float64, float64, float64) { // amd64:"MULSD",-"DIVSD" // arm/7:"MULD",-"DIVD" // arm64:"FMULD",-"FDIVD" + // loong64:"MULD",-"DIVD" // ppc64x:"FMUL",-"FDIV" // riscv64:"FMULD",-"FDIVD" x := f1 / 16.0 @@ -37,6 +39,7 @@ func DivPow2(f1, f2, f3 float64) (float64, float64, float64) { // amd64:"MULSD",-"DIVSD" // arm/7:"MULD",-"DIVD" // arm64:"FMULD",-"FDIVD" + // loong64:"MULD",-"DIVD" // ppc64x:"FMUL",-"FDIVD" // riscv64:"FMULD",-"FDIVD" y := f2 / 0.125 @@ -45,6 +48,7 @@ func DivPow2(f1, f2, f3 float64) (float64, float64, float64) { // amd64:"ADDSD",-"DIVSD",-"MULSD" // arm/7:"ADDD",-"MULD",-"DIVD" // arm64:"FADDD",-"FMULD",-"FDIVD" + // loong64:"ADDD",-"MULD",-"DIVD" // ppc64x:"FADD",-"FMUL",-"FDIV" // riscv64:"FADDD",-"FMULD",-"FDIVD" z := f3 / 0.5 |