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| author | cuishuang <imcusg@gmail.com> | 2026-01-07 13:46:43 +0800 |
|---|---|---|
| committer | Robert Griesemer <gri@google.com> | 2026-01-13 08:31:32 -0800 |
| commit | 7f6418bb4e44b1b11d428d402dd6935a2a1ea335 (patch) | |
| tree | 4a22ad6ceb4eb7bf91bb71e98f0aef56639dae1a /src/simd/archsimd/_gen | |
| parent | c16402d15b42cf494774796e606aba66c90d3d6b (diff) | |
| download | go-7f6418bb4e44b1b11d428d402dd6935a2a1ea335.tar.xz | |
all: fix misspellings in comments
Change-Id: I121847e7f68c602dd8e9ecddfc41b547f8a86f10
Reviewed-on: https://go-review.googlesource.com/c/go/+/734361
LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
Reviewed-by: Robert Griesemer <gri@google.com>
Reviewed-by: Junyang Shao <shaojunyang@google.com>
Diffstat (limited to 'src/simd/archsimd/_gen')
| -rw-r--r-- | src/simd/archsimd/_gen/simdgen/gen_simdMachineOps.go | 2 | ||||
| -rw-r--r-- | src/simd/archsimd/_gen/simdgen/gen_simdssa.go | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/src/simd/archsimd/_gen/simdgen/gen_simdMachineOps.go b/src/simd/archsimd/_gen/simdgen/gen_simdMachineOps.go index 3d99dd2a81..94b122ac39 100644 --- a/src/simd/archsimd/_gen/simdgen/gen_simdMachineOps.go +++ b/src/simd/archsimd/_gen/simdgen/gen_simdMachineOps.go @@ -181,7 +181,7 @@ func writeSIMDMachineOps(ops []Operation) *bytes.Buffer { } hasMerging = gOp.hasMaskedMerging(maskType, shapeOut) if hasMerging && !resultInArg0 { - // We have to copy the slice here becasue the sort will be visible from other + // We have to copy the slice here because the sort will be visible from other // aliases when no reslicing is happening. newIn := make([]Operand, len(op.In), len(op.In)+1) copy(newIn, op.In) diff --git a/src/simd/archsimd/_gen/simdgen/gen_simdssa.go b/src/simd/archsimd/_gen/simdgen/gen_simdssa.go index 876ffabe3d..96d096688f 100644 --- a/src/simd/archsimd/_gen/simdgen/gen_simdssa.go +++ b/src/simd/archsimd/_gen/simdgen/gen_simdssa.go @@ -133,7 +133,7 @@ func writeSIMDSSA(ops []Operation) *bytes.Buffer { if mem == NoMem && op.hasMaskedMerging(maskType, shapeOut) { regShapeMerging := regShape if shapeOut != OneVregOutAtIn { - // We have to copy the slice here becasue the sort will be visible from other + // We have to copy the slice here because the sort will be visible from other // aliases when no reslicing is happening. newIn := make([]Operand, len(op.In), len(op.In)+1) copy(newIn, op.In) |