[dev.fuzz] all: merge master into dev.fuzz

Change-Id: I5d8c8329ccc9d747bd81ade6b1cb7cb8ae2e94b2

23 files changed, 388 insertions, 157 deletions

diff --git a/src/internal/cpu/cpu.go b/src/internal/cpu/cpu.go
index 2829945af0..dab5d068ef 100644
--- a/src/internal/cpu/cpu.go
+++ b/src/internal/cpu/cpu.go
@@ -56,32 +56,17 @@ var ARM struct {
 // The booleans in ARM64 contain the correspondingly named cpu feature bit.
 // The struct is padded to avoid false sharing.
 var ARM64 struct {
-	_           CacheLinePad
-	HasFP       bool
-	HasASIMD    bool
-	HasEVTSTRM  bool
-	HasAES      bool
-	HasPMULL    bool
-	HasSHA1     bool
-	HasSHA2     bool
-	HasCRC32    bool
-	HasATOMICS  bool
-	HasFPHP     bool
-	HasASIMDHP  bool
-	HasCPUID    bool
-	HasASIMDRDM bool
-	HasJSCVT    bool
-	HasFCMA     bool
-	HasLRCPC    bool
-	HasDCPOP    bool
-	HasSHA3     bool
-	HasSM3      bool
-	HasSM4      bool
-	HasASIMDDP  bool
-	HasSHA512   bool
-	HasSVE      bool
-	HasASIMDFHM bool
-	_           CacheLinePad
+	_            CacheLinePad
+	HasAES       bool
+	HasPMULL     bool
+	HasSHA1      bool
+	HasSHA2      bool
+	HasCRC32     bool
+	HasATOMICS   bool
+	HasCPUID     bool
+	IsNeoverseN1 bool
+	IsZeus       bool
+	_            CacheLinePad
 }
 
 var MIPS64X struct {
diff --git a/src/internal/cpu/cpu.s b/src/internal/cpu/cpu.s
new file mode 100644
index 0000000000..3c770c132d
--- /dev/null
+++ b/src/internal/cpu/cpu.s
@@ -0,0 +1,6 @@
+// Copyright 2020 The Go Authors. All rights reserved.
+// Use of this source code is governed by a BSD-style
+// license that can be found in the LICENSE file.
+
+// This assembly file exists to allow internal/cpu to call
+// non-exported runtime functions that use "go:linkname".
\ No newline at end of file
diff --git a/src/internal/cpu/cpu_arm64.go b/src/internal/cpu/cpu_arm64.go
index efdb3b9e33..f64d9e4dd3 100644
--- a/src/internal/cpu/cpu_arm64.go
+++ b/src/internal/cpu/cpu_arm64.go
@@ -6,97 +6,23 @@ package cpu
 
 const CacheLinePadSize = 64
 
-// arm64 doesn't have a 'cpuid' equivalent, so we rely on HWCAP/HWCAP2.
-// These are initialized by archauxv and should not be changed after they are
-// initialized.
-var HWCap uint
-var HWCap2 uint
-
-// HWCAP/HWCAP2 bits. These are exposed by Linux.
-const (
-	hwcap_FP       = 1 << 0
-	hwcap_ASIMD    = 1 << 1
-	hwcap_EVTSTRM  = 1 << 2
-	hwcap_AES      = 1 << 3
-	hwcap_PMULL    = 1 << 4
-	hwcap_SHA1     = 1 << 5
-	hwcap_SHA2     = 1 << 6
-	hwcap_CRC32    = 1 << 7
-	hwcap_ATOMICS  = 1 << 8
-	hwcap_FPHP     = 1 << 9
-	hwcap_ASIMDHP  = 1 << 10
-	hwcap_CPUID    = 1 << 11
-	hwcap_ASIMDRDM = 1 << 12
-	hwcap_JSCVT    = 1 << 13
-	hwcap_FCMA     = 1 << 14
-	hwcap_LRCPC    = 1 << 15
-	hwcap_DCPOP    = 1 << 16
-	hwcap_SHA3     = 1 << 17
-	hwcap_SM3      = 1 << 18
-	hwcap_SM4      = 1 << 19
-	hwcap_ASIMDDP  = 1 << 20
-	hwcap_SHA512   = 1 << 21
-	hwcap_SVE      = 1 << 22
-	hwcap_ASIMDFHM = 1 << 23
-)
-
 func doinit() {
 	options = []option{
-		{Name: "evtstrm", Feature: &ARM64.HasEVTSTRM},
 		{Name: "aes", Feature: &ARM64.HasAES},
 		{Name: "pmull", Feature: &ARM64.HasPMULL},
 		{Name: "sha1", Feature: &ARM64.HasSHA1},
 		{Name: "sha2", Feature: &ARM64.HasSHA2},
 		{Name: "crc32", Feature: &ARM64.HasCRC32},
 		{Name: "atomics", Feature: &ARM64.HasATOMICS},
-		{Name: "fphp", Feature: &ARM64.HasFPHP},
-		{Name: "asimdhp", Feature: &ARM64.HasASIMDHP},
 		{Name: "cpuid", Feature: &ARM64.HasCPUID},
-		{Name: "asimdrdm", Feature: &ARM64.HasASIMDRDM},
-		{Name: "jscvt", Feature: &ARM64.HasJSCVT},
-		{Name: "fcma", Feature: &ARM64.HasFCMA},
-		{Name: "lrcpc", Feature: &ARM64.HasLRCPC},
-		{Name: "dcpop", Feature: &ARM64.HasDCPOP},
-		{Name: "sha3", Feature: &ARM64.HasSHA3},
-		{Name: "sm3", Feature: &ARM64.HasSM3},
-		{Name: "sm4", Feature: &ARM64.HasSM4},
-		{Name: "asimddp", Feature: &ARM64.HasASIMDDP},
-		{Name: "sha512", Feature: &ARM64.HasSHA512},
-		{Name: "sve", Feature: &ARM64.HasSVE},
-		{Name: "asimdfhm", Feature: &ARM64.HasASIMDFHM},
-
-		// These capabilities should always be enabled on arm64:
-		{Name: "fp", Feature: &ARM64.HasFP, Required: true},
-		{Name: "asimd", Feature: &ARM64.HasASIMD, Required: true},
+		{Name: "isNeoverseN1", Feature: &ARM64.IsNeoverseN1},
+		{Name: "isZeus", Feature: &ARM64.IsZeus},
 	}
 
-	// HWCAP feature bits
-	ARM64.HasFP = isSet(HWCap, hwcap_FP)
-	ARM64.HasASIMD = isSet(HWCap, hwcap_ASIMD)
-	ARM64.HasEVTSTRM = isSet(HWCap, hwcap_EVTSTRM)
-	ARM64.HasAES = isSet(HWCap, hwcap_AES)
-	ARM64.HasPMULL = isSet(HWCap, hwcap_PMULL)
-	ARM64.HasSHA1 = isSet(HWCap, hwcap_SHA1)
-	ARM64.HasSHA2 = isSet(HWCap, hwcap_SHA2)
-	ARM64.HasCRC32 = isSet(HWCap, hwcap_CRC32)
-	ARM64.HasATOMICS = isSet(HWCap, hwcap_ATOMICS)
-	ARM64.HasFPHP = isSet(HWCap, hwcap_FPHP)
-	ARM64.HasASIMDHP = isSet(HWCap, hwcap_ASIMDHP)
-	ARM64.HasCPUID = isSet(HWCap, hwcap_CPUID)
-	ARM64.HasASIMDRDM = isSet(HWCap, hwcap_ASIMDRDM)
-	ARM64.HasJSCVT = isSet(HWCap, hwcap_JSCVT)
-	ARM64.HasFCMA = isSet(HWCap, hwcap_FCMA)
-	ARM64.HasLRCPC = isSet(HWCap, hwcap_LRCPC)
-	ARM64.HasDCPOP = isSet(HWCap, hwcap_DCPOP)
-	ARM64.HasSHA3 = isSet(HWCap, hwcap_SHA3)
-	ARM64.HasSM3 = isSet(HWCap, hwcap_SM3)
-	ARM64.HasSM4 = isSet(HWCap, hwcap_SM4)
-	ARM64.HasASIMDDP = isSet(HWCap, hwcap_ASIMDDP)
-	ARM64.HasSHA512 = isSet(HWCap, hwcap_SHA512)
-	ARM64.HasSVE = isSet(HWCap, hwcap_SVE)
-	ARM64.HasASIMDFHM = isSet(HWCap, hwcap_ASIMDFHM)
+	// arm64 uses different ways to detect CPU features at runtime depending on the operating system.
+	osInit()
 }
 
-func isSet(hwc uint, value uint) bool {
-	return hwc&value != 0
-}
+func getisar0() uint64
+
+func getMIDR() uint64
diff --git a/src/internal/cpu/cpu_arm64.s b/src/internal/cpu/cpu_arm64.s
new file mode 100644
index 0000000000..d6e7f44373
--- /dev/null
+++ b/src/internal/cpu/cpu_arm64.s
@@ -0,0 +1,18 @@
+// Copyright 2020 The Go Authors. All rights reserved.
+// Use of this source code is governed by a BSD-style
+// license that can be found in the LICENSE file.
+
+#include "textflag.h"
+
+// func getisar0() uint64
+TEXT ·getisar0(SB),NOSPLIT,$0
+	// get Instruction Set Attributes 0 into R0
+	MRS	ID_AA64ISAR0_EL1, R0
+	MOVD	R0, ret+0(FP)
+	RET
+
+// func getMIDR() uint64
+TEXT ·getMIDR(SB), NOSPLIT, $0-8
+	MRS	MIDR_EL1, R0
+	MOVD	R0, ret+0(FP)
+	RET
diff --git a/src/internal/cpu/cpu_arm64_android.go b/src/internal/cpu/cpu_arm64_android.go
new file mode 100644
index 0000000000..3c9e57c52a
--- /dev/null
+++ b/src/internal/cpu/cpu_arm64_android.go
@@ -0,0 +1,11 @@
+// Copyright 2020 The Go Authors. All rights reserved.
+// Use of this source code is governed by a BSD-style
+// license that can be found in the LICENSE file.
+
+// +build arm64
+
+package cpu
+
+func osInit() {
+	hwcapInit("android")
+}
diff --git a/src/internal/cpu/cpu_arm64_darwin.go b/src/internal/cpu/cpu_arm64_darwin.go
new file mode 100644
index 0000000000..e094b97f97
--- /dev/null
+++ b/src/internal/cpu/cpu_arm64_darwin.go
@@ -0,0 +1,34 @@
+// Copyright 2020 The Go Authors. All rights reserved.
+// Use of this source code is governed by a BSD-style
+// license that can be found in the LICENSE file.
+
+// +build arm64
+// +build darwin
+// +build !ios
+
+package cpu
+
+func osInit() {
+	ARM64.HasATOMICS = sysctlEnabled([]byte("hw.optional.armv8_1_atomics\x00"))
+	ARM64.HasCRC32 = sysctlEnabled([]byte("hw.optional.armv8_crc32\x00"))
+
+	// There are no hw.optional sysctl values for the below features on Mac OS 11.0
+	// to detect their supported state dynamically. Assume the CPU features that
+	// Apple Silicon M1 supports to be available as a minimal set of features
+	// to all Go programs running on darwin/arm64.
+	ARM64.HasAES = true
+	ARM64.HasPMULL = true
+	ARM64.HasSHA1 = true
+	ARM64.HasSHA2 = true
+}
+
+//go:noescape
+func getsysctlbyname(name []byte) (int32, int32)
+
+func sysctlEnabled(name []byte) bool {
+	ret, value := getsysctlbyname(name)
+	if ret < 0 {
+		return false
+	}
+	return value > 0
+}
diff --git a/src/internal/cpu/cpu_arm64_freebsd.go b/src/internal/cpu/cpu_arm64_freebsd.go
new file mode 100644
index 0000000000..9de2005c2e
--- /dev/null
+++ b/src/internal/cpu/cpu_arm64_freebsd.go
@@ -0,0 +1,45 @@
+// Copyright 2020 The Go Authors. All rights reserved.
+// Use of this source code is governed by a BSD-style
+// license that can be found in the LICENSE file.
+
+// +build arm64
+
+package cpu
+
+func osInit() {
+	// Retrieve info from system register ID_AA64ISAR0_EL1.
+	isar0 := getisar0()
+
+	// ID_AA64ISAR0_EL1
+	switch extractBits(isar0, 4, 7) {
+	case 1:
+		ARM64.HasAES = true
+	case 2:
+		ARM64.HasAES = true
+		ARM64.HasPMULL = true
+	}
+
+	switch extractBits(isar0, 8, 11) {
+	case 1:
+		ARM64.HasSHA1 = true
+	}
+
+	switch extractBits(isar0, 12, 15) {
+	case 1, 2:
+		ARM64.HasSHA2 = true
+	}
+
+	switch extractBits(isar0, 16, 19) {
+	case 1:
+		ARM64.HasCRC32 = true
+	}
+
+	switch extractBits(isar0, 20, 23) {
+	case 2:
+		ARM64.HasATOMICS = true
+	}
+}
+
+func extractBits(data uint64, start, end uint) uint {
+	return (uint)(data>>start) & ((1 << (end - start + 1)) - 1)
+}
diff --git a/src/internal/cpu/cpu_arm64_hwcap.go b/src/internal/cpu/cpu_arm64_hwcap.go
new file mode 100644
index 0000000000..fdaf43e1a2
--- /dev/null
+++ b/src/internal/cpu/cpu_arm64_hwcap.go
@@ -0,0 +1,63 @@
+// Copyright 2020 The Go Authors. All rights reserved.
+// Use of this source code is governed by a BSD-style
+// license that can be found in the LICENSE file.
+
+// +build arm64
+// +build linux
+
+package cpu
+
+// HWCap may be initialized by archauxv and
+// should not be changed after it was initialized.
+var HWCap uint
+
+// HWCAP bits. These are exposed by Linux.
+const (
+	hwcap_AES     = 1 << 3
+	hwcap_PMULL   = 1 << 4
+	hwcap_SHA1    = 1 << 5
+	hwcap_SHA2    = 1 << 6
+	hwcap_CRC32   = 1 << 7
+	hwcap_ATOMICS = 1 << 8
+	hwcap_CPUID   = 1 << 11
+)
+
+func hwcapInit(os string) {
+	// HWCap was populated by the runtime from the auxiliary vector.
+	// Use HWCap information since reading aarch64 system registers
+	// is not supported in user space on older linux kernels.
+	ARM64.HasAES = isSet(HWCap, hwcap_AES)
+	ARM64.HasPMULL = isSet(HWCap, hwcap_PMULL)
+	ARM64.HasSHA1 = isSet(HWCap, hwcap_SHA1)
+	ARM64.HasSHA2 = isSet(HWCap, hwcap_SHA2)
+	ARM64.HasCRC32 = isSet(HWCap, hwcap_CRC32)
+	ARM64.HasCPUID = isSet(HWCap, hwcap_CPUID)
+
+	// The Samsung S9+ kernel reports support for atomics, but not all cores
+	// actually support them, resulting in SIGILL. See issue #28431.
+	// TODO(elias.naur): Only disable the optimization on bad chipsets on android.
+	ARM64.HasATOMICS = isSet(HWCap, hwcap_ATOMICS) && os != "android"
+
+	// Check to see if executing on a NeoverseN1 and in order to do that,
+	// check the AUXV for the CPUID bit. The getMIDR function executes an
+	// instruction which would normally be an illegal instruction, but it's
+	// trapped by the kernel, the value sanitized and then returned. Without
+	// the CPUID bit the kernel will not trap the instruction and the process
+	// will be terminated with SIGILL.
+	if ARM64.HasCPUID {
+		midr := getMIDR()
+		part_num := uint16((midr >> 4) & 0xfff)
+		implementor := byte((midr >> 24) & 0xff)
+
+		if implementor == 'A' && part_num == 0xd0c {
+			ARM64.IsNeoverseN1 = true
+		}
+		if implementor == 'A' && part_num == 0xd40 {
+			ARM64.IsZeus = true
+		}
+	}
+}
+
+func isSet(hwc uint, value uint) bool {
+	return hwc&value != 0
+}
diff --git a/src/internal/cpu/cpu_arm64_linux.go b/src/internal/cpu/cpu_arm64_linux.go
new file mode 100644
index 0000000000..2f7411ff1e
--- /dev/null
+++ b/src/internal/cpu/cpu_arm64_linux.go
@@ -0,0 +1,13 @@
+// Copyright 2020 The Go Authors. All rights reserved.
+// Use of this source code is governed by a BSD-style
+// license that can be found in the LICENSE file.
+
+// +build arm64
+// +build linux
+// +build !android
+
+package cpu
+
+func osInit() {
+	hwcapInit("linux")
+}
diff --git a/src/internal/cpu/cpu_arm64_other.go b/src/internal/cpu/cpu_arm64_other.go
new file mode 100644
index 0000000000..f191db28d2
--- /dev/null
+++ b/src/internal/cpu/cpu_arm64_other.go
@@ -0,0 +1,17 @@
+// Copyright 2020 The Go Authors. All rights reserved.
+// Use of this source code is governed by a BSD-style
+// license that can be found in the LICENSE file.
+
+// +build arm64
+// +build !linux
+// +build !freebsd
+// +build !android
+// +build !darwin ios
+
+package cpu
+
+func osInit() {
+	// Other operating systems do not support reading HWCap from auxiliary vector,
+	// reading privileged aarch64 system registers or sysctl in user space to detect
+	// CPU features at runtime.
+}
diff --git a/src/internal/cpu/cpu_mips.go b/src/internal/cpu/cpu_mips.go
index 0f821e44e7..14a9c975ea 100644
--- a/src/internal/cpu/cpu_mips.go
+++ b/src/internal/cpu/cpu_mips.go
@@ -5,3 +5,6 @@
 package cpu
 
 const CacheLinePadSize = 32
+
+func doinit() {
+}
diff --git a/src/internal/cpu/cpu_mipsle.go b/src/internal/cpu/cpu_mipsle.go
index 0f821e44e7..14a9c975ea 100644
--- a/src/internal/cpu/cpu_mipsle.go
+++ b/src/internal/cpu/cpu_mipsle.go
@@ -5,3 +5,6 @@
 package cpu
 
 const CacheLinePadSize = 32
+
+func doinit() {
+}
diff --git a/src/internal/cpu/cpu_no_init.go b/src/internal/cpu/cpu_no_init.go
deleted file mode 100644
index fb381e1ce2..0000000000
--- a/src/internal/cpu/cpu_no_init.go
+++ /dev/null
@@ -1,18 +0,0 @@
-// Copyright 2018 The Go Authors. All rights reserved.
-// Use of this source code is governed by a BSD-style
-// license that can be found in the LICENSE file.
-
-// +build !386
-// +build !amd64
-// +build !arm
-// +build !arm64
-// +build !ppc64
-// +build !ppc64le
-// +build !s390x
-// +build !mips64
-// +build !mips64le
-
-package cpu
-
-func doinit() {
-}
diff --git a/src/internal/cpu/cpu_no_name.go b/src/internal/cpu/cpu_no_name.go
new file mode 100644
index 0000000000..ce1c37a3c7
--- /dev/null
+++ b/src/internal/cpu/cpu_no_name.go
@@ -0,0 +1,19 @@
+// Copyright 2020 The Go Authors. All rights reserved.
+// Use of this source code is governed by a BSD-style
+// license that can be found in the LICENSE file.
+
+// +build !386
+// +build !amd64
+
+package cpu
+
+// Name returns the CPU name given by the vendor
+// if it can be read directly from memory or by CPU instructions.
+// If the CPU name can not be determined an empty string is returned.
+//
+// Implementations that use the Operating System (e.g. sysctl or /sys/)
+// to gather CPU information for display should be placed in internal/sysinfo.
+func Name() string {
+	// "A CPU has no name".
+	return ""
+}
diff --git a/src/internal/cpu/cpu_ppc64x.go b/src/internal/cpu/cpu_ppc64x.go
index 2487879c46..beb1765427 100644
--- a/src/internal/cpu/cpu_ppc64x.go
+++ b/src/internal/cpu/cpu_ppc64x.go
@@ -8,39 +8,14 @@ package cpu
 
 const CacheLinePadSize = 128
 
-// ppc64x doesn't have a 'cpuid' equivalent, so we rely on HWCAP/HWCAP2.
-// These are initialized by archauxv and should not be changed after they are
-// initialized.
-// On aix/ppc64, these values are initialized early in the runtime in runtime/os_aix.go.
-var HWCap uint
-var HWCap2 uint
-
-// HWCAP/HWCAP2 bits. These are exposed by the kernel.
-const (
-	// ISA Level
-	PPC_FEATURE2_ARCH_2_07 = 0x80000000
-	PPC_FEATURE2_ARCH_3_00 = 0x00800000
-
-	// CPU features
-	PPC_FEATURE2_DARN = 0x00200000
-	PPC_FEATURE2_SCV  = 0x00100000
-)
-
 func doinit() {
 	options = []option{
 		{Name: "darn", Feature: &PPC64.HasDARN},
 		{Name: "scv", Feature: &PPC64.HasSCV},
 		{Name: "power9", Feature: &PPC64.IsPOWER9},
-
-		// These capabilities should always be enabled on ppc64 and ppc64le:
-		{Name: "power8", Feature: &PPC64.IsPOWER8, Required: true},
 	}
 
-	// HWCAP2 feature bits
-	PPC64.IsPOWER8 = isSet(HWCap2, PPC_FEATURE2_ARCH_2_07)
-	PPC64.IsPOWER9 = isSet(HWCap2, PPC_FEATURE2_ARCH_3_00)
-	PPC64.HasDARN = isSet(HWCap2, PPC_FEATURE2_DARN)
-	PPC64.HasSCV = isSet(HWCap2, PPC_FEATURE2_SCV)
+	osinit()
 }
 
 func isSet(hwc uint, value uint) bool {
diff --git a/src/internal/cpu/cpu_ppc64x_aix.go b/src/internal/cpu/cpu_ppc64x_aix.go
new file mode 100644
index 0000000000..b840b823ba
--- /dev/null
+++ b/src/internal/cpu/cpu_ppc64x_aix.go
@@ -0,0 +1,21 @@
+// Copyright 2020 The Go Authors. All rights reserved.
+// Use of this source code is governed by a BSD-style
+// license that can be found in the LICENSE file.
+
+// +build ppc64 ppc64le
+
+package cpu
+
+const (
+	// getsystemcfg constants
+	_SC_IMPL     = 2
+	_IMPL_POWER9 = 0x20000
+)
+
+func osinit() {
+	impl := getsystemcfg(_SC_IMPL)
+	PPC64.IsPOWER9 = isSet(impl, _IMPL_POWER9)
+}
+
+// getsystemcfg is defined in runtime/os2_aix.go
+func getsystemcfg(label uint) uint
diff --git a/src/internal/cpu/cpu_ppc64x_linux.go b/src/internal/cpu/cpu_ppc64x_linux.go
new file mode 100644
index 0000000000..73b191436d
--- /dev/null
+++ b/src/internal/cpu/cpu_ppc64x_linux.go
@@ -0,0 +1,29 @@
+// Copyright 2020 The Go Authors. All rights reserved.
+// Use of this source code is governed by a BSD-style
+// license that can be found in the LICENSE file.
+
+// +build ppc64 ppc64le
+
+package cpu
+
+// ppc64 doesn't have a 'cpuid' equivalent, so we rely on HWCAP/HWCAP2.
+// These are initialized by archauxv and should not be changed after they are
+// initialized.
+var HWCap uint
+var HWCap2 uint
+
+// HWCAP bits. These are exposed by Linux.
+const (
+	// ISA Level
+	hwcap2_ARCH_3_00 = 0x00800000
+
+	// CPU features
+	hwcap2_DARN = 0x00200000
+	hwcap2_SCV  = 0x00100000
+)
+
+func osinit() {
+	PPC64.IsPOWER9 = isSet(HWCap2, hwcap2_ARCH_3_00)
+	PPC64.HasDARN = isSet(HWCap2, hwcap2_DARN)
+	PPC64.HasSCV = isSet(HWCap2, hwcap2_SCV)
+}
diff --git a/src/internal/cpu/cpu_riscv64.go b/src/internal/cpu/cpu_riscv64.go
index c49cab79fd..54b8c3378b 100644
--- a/src/internal/cpu/cpu_riscv64.go
+++ b/src/internal/cpu/cpu_riscv64.go
@@ -5,3 +5,6 @@
 package cpu
 
 const CacheLinePadSize = 32
+
+func doinit() {
+}
diff --git a/src/internal/cpu/cpu_s390x.go b/src/internal/cpu/cpu_s390x.go
index 526e074225..45d8ed27f0 100644
--- a/src/internal/cpu/cpu_s390x.go
+++ b/src/internal/cpu/cpu_s390x.go
@@ -6,6 +6,8 @@ package cpu
 
 const CacheLinePadSize = 256
 
+var HWCap uint
+
 // bitIsSet reports whether the bit at index is set. The bit index
 // is in big endian order, so bit index 0 is the leftmost bit.
 func bitIsSet(bits []uint64, index uint) bool {
@@ -95,8 +97,10 @@ const (
 	// vector facilities
 	vxe facility = 135 // vector-enhancements 1
 
-	// Note: vx and highgprs are excluded because they require
-	// kernel support and so must be fetched from HWCAP.
+	// Note: vx requires kernel support
+	// and so must be fetched from HWCAP.
+
+	hwcap_VX = 1 << 11 // vector facility
 )
 
 // facilityList contains the result of an STFLE call.
@@ -188,7 +192,14 @@ func doinit() {
 			S390X.HasEDDSA = kdsa.Has(eddsaVerifyEd25519, eddsaSignEd25519, eddsaVerifyEd448, eddsaSignEd448)
 		}
 	}
+
+	S390X.HasVX = isSet(HWCap, hwcap_VX)
+
 	if S390X.HasVX {
 		S390X.HasVXE = facilities.Has(vxe)
 	}
 }
+
+func isSet(hwc uint, value uint) bool {
+	return hwc&value != 0
+}
diff --git a/src/internal/cpu/cpu_s390x_test.go b/src/internal/cpu/cpu_s390x_test.go
index d910bbe695..ad86858db0 100644
--- a/src/internal/cpu/cpu_s390x_test.go
+++ b/src/internal/cpu/cpu_s390x_test.go
@@ -7,13 +7,13 @@ package cpu_test
 import (
 	"errors"
 	. "internal/cpu"
-	"io/ioutil"
+	"os"
 	"regexp"
 	"testing"
 )
 
 func getFeatureList() ([]string, error) {
-	cpuinfo, err := ioutil.ReadFile("/proc/cpuinfo")
+	cpuinfo, err := os.ReadFile("/proc/cpuinfo")
 	if err != nil {
 		return nil, err
 	}
diff --git a/src/internal/cpu/cpu_test.go b/src/internal/cpu/cpu_test.go
index e09bd2d8b9..2de7365732 100644
--- a/src/internal/cpu/cpu_test.go
+++ b/src/internal/cpu/cpu_test.go
@@ -15,9 +15,10 @@ import (
 )
 
 func TestMinimalFeatures(t *testing.T) {
+	// TODO: maybe do MustSupportFeatureDectection(t) ?
 	if runtime.GOARCH == "arm64" {
 		switch runtime.GOOS {
-		case "linux", "android":
+		case "linux", "android", "darwin":
 		default:
 			t.Skipf("%s/%s is not supported", runtime.GOOS, runtime.GOARCH)
 		}
@@ -36,6 +37,10 @@ func MustHaveDebugOptionsSupport(t *testing.T) {
 	}
 }
 
+func MustSupportFeatureDectection(t *testing.T) {
+	// TODO: add platforms that do not have CPU feature detection support.
+}
+
 func runDebugOptionsTest(t *testing.T, test string, options string) {
 	MustHaveDebugOptionsSupport(t)
 
@@ -58,6 +63,7 @@ func runDebugOptionsTest(t *testing.T, test string, options string) {
 }
 
 func TestDisableAllCapabilities(t *testing.T) {
+	MustSupportFeatureDectection(t)
 	runDebugOptionsTest(t, "TestAllCapabilitiesDisabled", "cpu.all=off")
 }
 
diff --git a/src/internal/cpu/cpu_wasm.go b/src/internal/cpu/cpu_wasm.go
index b459738770..2310ad6a48 100644
--- a/src/internal/cpu/cpu_wasm.go
+++ b/src/internal/cpu/cpu_wasm.go
@@ -5,3 +5,6 @@
 package cpu
 
 const CacheLinePadSize = 64
+
+func doinit() {
+}
diff --git a/src/internal/cpu/cpu_x86.go b/src/internal/cpu/cpu_x86.go
index da6cf67258..ba6bf69034 100644
--- a/src/internal/cpu/cpu_x86.go
+++ b/src/internal/cpu/cpu_x86.go
@@ -38,6 +38,8 @@ const (
 	cpuid_ADX  = 1 << 19
 )
 
+var maxExtendedFunctionInformation uint32
+
 func doinit() {
 	options = []option{
 		{Name: "adx", Feature: &X86.HasADX},
@@ -65,19 +67,30 @@ func doinit() {
 		return
 	}
 
+	maxExtendedFunctionInformation, _, _, _ = cpuid(0x80000000, 0)
+
 	_, _, ecx1, edx1 := cpuid(1, 0)
 	X86.HasSSE2 = isSet(edx1, cpuid_SSE2)
 
 	X86.HasSSE3 = isSet(ecx1, cpuid_SSE3)
 	X86.HasPCLMULQDQ = isSet(ecx1, cpuid_PCLMULQDQ)
 	X86.HasSSSE3 = isSet(ecx1, cpuid_SSSE3)
-	X86.HasFMA = isSet(ecx1, cpuid_FMA)
 	X86.HasSSE41 = isSet(ecx1, cpuid_SSE41)
 	X86.HasSSE42 = isSet(ecx1, cpuid_SSE42)
 	X86.HasPOPCNT = isSet(ecx1, cpuid_POPCNT)
 	X86.HasAES = isSet(ecx1, cpuid_AES)
+
+	// OSXSAVE can be false when using older Operating Systems
+	// or when explicitly disabled on newer Operating Systems by
+	// e.g. setting the xsavedisable boot option on Windows 10.
 	X86.HasOSXSAVE = isSet(ecx1, cpuid_OSXSAVE)
 
+	// The FMA instruction set extension only has VEX prefixed instructions.
+	// VEX prefixed instructions require OSXSAVE to be enabled.
+	// See Intel 64 and IA-32 Architecture Software Developer’s Manual Volume 2
+	// Section 2.4 "AVX and SSE Instruction Exception Specification"
+	X86.HasFMA = isSet(ecx1, cpuid_FMA) && X86.HasOSXSAVE
+
 	osSupportsAVX := false
 	// For XGETBV, OSXSAVE bit is required and sufficient.
 	if X86.HasOSXSAVE {
@@ -103,3 +116,48 @@ func doinit() {
 func isSet(hwc uint32, value uint32) bool {
 	return hwc&value != 0
 }
+
+// Name returns the CPU name given by the vendor.
+// If the CPU name can not be determined an
+// empty string is returned.
+func Name() string {
+	if maxExtendedFunctionInformation < 0x80000004 {
+		return ""
+	}
+
+	data := make([]byte, 0, 3*4*4)
+
+	var eax, ebx, ecx, edx uint32
+	eax, ebx, ecx, edx = cpuid(0x80000002, 0)
+	data = appendBytes(data, eax, ebx, ecx, edx)
+	eax, ebx, ecx, edx = cpuid(0x80000003, 0)
+	data = appendBytes(data, eax, ebx, ecx, edx)
+	eax, ebx, ecx, edx = cpuid(0x80000004, 0)
+	data = appendBytes(data, eax, ebx, ecx, edx)
+
+	// Trim leading spaces.
+	for len(data) > 0 && data[0] == ' ' {
+		data = data[1:]
+	}
+
+	// Trim tail after and including the first null byte.
+	for i, c := range data {
+		if c == '\x00' {
+			data = data[:i]
+			break
+		}
+	}
+
+	return string(data)
+}
+
+func appendBytes(b []byte, args ...uint32) []byte {
+	for _, arg := range args {
+		b = append(b,
+			byte((arg >> 0)),
+			byte((arg >> 8)),
+			byte((arg >> 16)),
+			byte((arg >> 24)))
+	}
+	return b
+}