diff options
| author | Junyang Shao <shaojunyang@google.com> | 2026-01-22 17:44:32 +0000 |
|---|---|---|
| committer | Junyang Shao <shaojunyang@google.com> | 2026-01-28 11:06:13 -0800 |
| commit | 83b232b0af1bd498d3df099eb68e3b1e40df2527 (patch) | |
| tree | 3d31013c9c8722c0370f970d6b47a7109b37da06 /src/internal/cpu/cpu.go | |
| parent | 6aef900af4eeb4a35d3ff1237a41cf3f63c56c24 (diff) | |
| download | go-83b232b0af1bd498d3df099eb68e3b1e40df2527.tar.xz | |
cmd/compile, simd: capture VAES instructions and fix AVX512VAES feature
The code previously filters out VAES-only instructions, this CL added
them back.
This CL added the VAES feature check following the Intel xed data:
XED_ISA_SET_VAES: vaes.7.0.ecx.9 # avx.1.0.ecx.28
This CL also found out that the old AVX512VAES feature check is not
checking the correct bits, it also fixes it:
XED_ISA_SET_AVX512_VAES_128: vaes.7.0.ecx.9 aes.1.0.ecx.25 avx512f.7.0.ebx.16 avx512vl.7.0.ebx.31
XED_ISA_SET_AVX512_VAES_256: vaes.7.0.ecx.9 aes.1.0.ecx.25 avx512f.7.0.ebx.16 avx512vl.7.0.ebx.31
XED_ISA_SET_AVX512_VAES_512: vaes.7.0.ecx.9 aes.1.0.ecx.25 avx512f.7.0.ebx.16
It restricts to the most strict common set - includes avx512vl for even
512-bits although it doesn't requires it.
Change-Id: I4e2f72b312fd2411589fbc12f9ee5c63c09c2e9a
Reviewed-on: https://go-review.googlesource.com/c/go/+/738500
Reviewed-by: Cherry Mui <cherryyz@google.com>
LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
Diffstat (limited to 'src/internal/cpu/cpu.go')
| -rw-r--r-- | src/internal/cpu/cpu.go | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/internal/cpu/cpu.go b/src/internal/cpu/cpu.go index 4dffeadb22..52459be3bb 100644 --- a/src/internal/cpu/cpu.go +++ b/src/internal/cpu/cpu.go @@ -56,6 +56,7 @@ var X86 struct { HasSSSE3 bool HasSSE41 bool HasSSE42 bool + HasVAES bool _ CacheLinePad } |