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| author | Joel Sing <joel@sing.id.au> | 2023-08-28 02:08:56 +1000 |
|---|---|---|
| committer | Joel Sing <joel@sing.id.au> | 2023-11-09 13:39:57 +0000 |
| commit | e816eb50140841c524fd07ecb4eaa078954eb47c (patch) | |
| tree | cf153a885c4ab014c38f904a60f50f47ad450890 /src/cmd/asm/internal | |
| parent | 7a1fce8751b04f66f758c7aac0efd5937bc670dc (diff) | |
| download | go-e816eb50140841c524fd07ecb4eaa078954eb47c.tar.xz | |
cmd/internal/obj/riscv: improve handling of invalid assembly
Currently, instruction validation failure will result in a panic during
encoding. Furthermore, the errors generated do not include the PC or
file/line information that is normally present.
Fix this by:
- Tracking and printing the *obj.Prog associated with the instruction,
including the assembly instruction/opcode if it differs. This provides
the standard PC and file/line prefix, which is also expected by assembly
error end-to-end tests.
- Not proceeding with assembly if errors exist - with the current design,
errors are identified during validation, which is run via preprocess.
Attempts to encode invalid instructions will intentionally panic.
Add some additional riscv64 encoding errors, now that we can actually do so.
Change-Id: I64a7b83680c4d12aebdc96c67f9df625b5ef90d3
Reviewed-on: https://go-review.googlesource.com/c/go/+/523459
Run-TryBot: Joel Sing <joel@sing.id.au>
Reviewed-by: Mark Ryan <markdryan@rivosinc.com>
Reviewed-by: Heschi Kreinick <heschi@google.com>
TryBot-Result: Gopher Robot <gobot@golang.org>
Run-TryBot: M Zhuo <mzh@golangcn.org>
Reviewed-by: Cherry Mui <cherryyz@google.com>
Reviewed-by: M Zhuo <mzh@golangcn.org>
Diffstat (limited to 'src/cmd/asm/internal')
| -rw-r--r-- | src/cmd/asm/internal/asm/testdata/riscv64error.s | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/src/cmd/asm/internal/asm/testdata/riscv64error.s b/src/cmd/asm/internal/asm/testdata/riscv64error.s index cdb8a028bd..2dc9db3fb1 100644 --- a/src/cmd/asm/internal/asm/testdata/riscv64error.s +++ b/src/cmd/asm/internal/asm/testdata/riscv64error.s @@ -38,5 +38,8 @@ TEXT errors(SB),$0 SLLIW $-1, X5, X6 // ERROR "shift amount out of range 0 to 31" SRLIW $-1, X5, X6 // ERROR "shift amount out of range 0 to 31" SRAIW $-1, X5, X6 // ERROR "shift amount out of range 0 to 31" - + SD X5, 4294967296(X6) // ERROR "constant 4294967296 too large" + SRLI $1, X5, F1 // ERROR "expected integer register in rd position but got non-integer register F1" + SRLI $1, F1, X5 // ERROR "expected integer register in rs1 position but got non-integer register F1" + FNES F1, (X5) // ERROR "needs an integer register output" RET |