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| author | Junxian Zhu <zhujunxian@oss.cipunited.com> | 2023-08-03 14:44:01 +0800 |
|---|---|---|
| committer | Joel Sing <joel@sing.id.au> | 2023-08-08 12:17:12 +0000 |
| commit | 24f83ed4e29495d5b8b6375aeaa2d34d14629c7d (patch) | |
| tree | 932f6991ef81eecd665e8eadea98c4274c92463b /src/cmd/asm/internal | |
| parent | 87fe5faffca1bce0db513a3c1bb640ccf6a04bc7 (diff) | |
| download | go-24f83ed4e29495d5b8b6375aeaa2d34d14629c7d.tar.xz | |
cmd/internal/obj/mips: add SEB/SEH instructions
Add support for SEB/SEH instructions, which are introduced in mips32r2.
SEB/SEH can be used to sign-extend byte/halfword in registers directly without passing through memory.
Ref: The MIPS32 Instruction Set, Revision 5.04: https://s3-eu-west-1.amazonaws.com/downloads-mips/documents/MD00086-2B-MIPS32BIS-AFP-05.04.pdf
Updates #60072
Change-Id: I33175ae9d943ead5983ac004bd2a158039046d65
Reviewed-on: https://go-review.googlesource.com/c/go/+/515475
TryBot-Result: Gopher Robot <gobot@golang.org>
Reviewed-by: Michael Knyszek <mknyszek@google.com>
Reviewed-by: Cherry Mui <cherryyz@google.com>
Run-TryBot: Joel Sing <joel@sing.id.au>
Diffstat (limited to 'src/cmd/asm/internal')
| -rw-r--r-- | src/cmd/asm/internal/asm/testdata/mips.s | 4 | ||||
| -rw-r--r-- | src/cmd/asm/internal/asm/testdata/mips64.s | 4 |
2 files changed, 8 insertions, 0 deletions
diff --git a/src/cmd/asm/internal/asm/testdata/mips.s b/src/cmd/asm/internal/asm/testdata/mips.s index 1ded0b072d..f65eba07ba 100644 --- a/src/cmd/asm/internal/asm/testdata/mips.s +++ b/src/cmd/asm/internal/asm/testdata/mips.s @@ -428,8 +428,12 @@ label4: NEGW R1, R2 // 00011023 CLZ R1, R2 // 70221020 CLO R1, R2 // 70221021 + WSBH R1, R2 // 7c0110a0 + SEB R1, R2 // 7c011420 + SEH R1, R2 // 7c011620 + // to (Hi, Lo) MADD R2, R1 // 70220000 MSUB R2, R1 // 70220004 diff --git a/src/cmd/asm/internal/asm/testdata/mips64.s b/src/cmd/asm/internal/asm/testdata/mips64.s index 573e3d31a6..ea4bb80aec 100644 --- a/src/cmd/asm/internal/asm/testdata/mips64.s +++ b/src/cmd/asm/internal/asm/testdata/mips64.s @@ -590,10 +590,14 @@ label4: // unary operation NEGW R1, R2 // 00011023 NEGV R1, R2 // 0001102f + WSBH R1, R2 // 7c0110a0 DSBH R1, R2 // 7c0110a4 DSHD R1, R2 // 7c011164 + SEB R1, R2 // 7c011420 + SEH R1, R2 // 7c011620 + RET // MSA VMOVI |